Planar Capacitor Patents (Class 438/393)
  • Patent number: 10937856
    Abstract: A semiconductor device and a manufacturing method thereof, the semiconductor device including an insulation layer; a metal resistance pattern on the insulation layer; a spacer on a side wall of the metal resistance pattern; and a gate contact spaced apart from the spacer, the gate contact extending into the insulation layer, wherein the insulation layer includes a projection projecting therefrom, the projection contacting the gate contact.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: March 2, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Hun Choi, Young Tak Kim, Da Il Eom, Sun Jung Lee
  • Patent number: 10840325
    Abstract: Integrated circuits including metal-insulator-metal capacitors (MIMCAPs) generally include a diffusion barrier layer on the top and bottom surfaces of the electrode and a self-formed oxide layer on sidewalls of the electrode. The diffusion barrier layers and the self-formed oxide layers on the sidewalls of the electrode prevent diffusion of the metal defining the electrode into the interlayer dielectric. Also described are processes for fabricating the MIMCAPs.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph F. Maniscalco, Koichi Motoyama, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10468507
    Abstract: The present invention is in the field of spintronics, and relates to a highly efficient spin filter device, such as a spin-polarizer or a spin valve, and a method for fabrication thereof.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: November 5, 2019
    Assignee: YEDA RESEARCH AND DEVELOPMENT CO. LTD.
    Inventors: Oren Tal, Ran Vardimon, Marina Klionsky
  • Patent number: 9905707
    Abstract: Capacitive structures in the device level of sophisticated MOS devices may be formed so as to exhibit a significantly reduced capacitance/voltage variability. To this end, a highly doped semiconductor region may be formed in the “channel” of the capacitive structure. For example, for a specified concentration of the dopant species and a specified range of the vertical dimension of the highly doped semiconductor region, a reduced variability of approximately 3% or less may be obtained for a voltage range of, for example, ±5 V.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: February 27, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andrei Sidelnicov, Alban Zaka, El Mehdi Bazizi, Venkata Naga Ranjith Kumar Nelluri, Juergen Faul
  • Patent number: 9728719
    Abstract: An integrated circuit device includes a resistive random access memory (RRAM) cell or a MIM capacitor cell having a dielectric layer, a top conductive layer, and a bottom conductive layer. The dielectric layer includes a peripheral region adjacent an edge of the dielectric layer and a central region surrounded by the peripheral region. The top conductive layer abuts and is above dielectric layer. The bottom conductive layer abuts and is below the dielectric layer in the central region, but does not abut the dielectric layer the peripheral region of the cell. Abutment can be prevented by either an additional dielectric layer between the bottom conductive layer and the dielectric layer that is exclusively in the peripheral region or by cutting of the bottom electrode layer short of the peripheral region. Damage or contamination at the edge of the dielectric layer does not result in leakage currents.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: August 8, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming Chyi Liu, Yuan-Tai Tseng, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 9646659
    Abstract: A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and second bit lines in response to a bit line equalization signal; a sense-amplifier power control unit suitable for providing a plurality of powers to the bit line sense-amplifier in response to a power control signal; and a second precharge unit suitable for individually changing each voltage level of the first and second bit lines based on a precharge control signal.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: May 9, 2017
    Assignee: SK Hynix Inc.
    Inventor: Hee Sang Kim
  • Patent number: 9478601
    Abstract: In a semiconductor device, plate-shaped upper electrodes are formed on a lower electrode with a dielectric film interposed therebetween. The lower electrode, the dielectric film, and the upper electrodes constitute MIM capacitors. One of the upper electrodes and another upper electrode that are adjacent to each other are arranged at an equal distance, without the guard ring being interposed therebetween. The upper electrodes positioned on the outermost periphery and the guard ring positioned outside those upper electrodes are arranged at a distance equal to the distance from each other.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: October 25, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuo Tomita, Keiichi Yamada
  • Patent number: 9355983
    Abstract: A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Zigmund Ramirez Camacho, Emmanuel Espiritu, Bartholomew Liao Chung Foh, Dao Nguyen Phu Cuong, Jeffrey David Punzalan
  • Patent number: 9349788
    Abstract: A substrate comprising a capacitor comprising metal electrodes and a ceramic or metal oxide dielectric layer, the capacitor being embedded in a polymer based encapsulating material and connectable to a circuit via a via post standing on said capacitor.
    Type: Grant
    Filed: August 8, 2013
    Date of Patent: May 24, 2016
    Assignee: Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd.
    Inventors: Dror Hurwitz, Alex Huang
  • Patent number: 9349723
    Abstract: A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A passive device is formed on the substrate by depositing a first conductive layer over the substrate, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the insulating layer. The passive device is a metal-insulator-metal capacitor. The deposition of the insulating layer and first and second conductive layers is performed without photolithography. An under bump metallization (UBM) layer is formed on the substrate in electrical contact with the plurality of active devices. A solder bump is formed over the UBM layer. The passive device can also be a resistor by depositing a resistive layer over the first conductive layer and depositing a third conductive layer over the resistive layer. The passive device electrically contacts the solder bump.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: May 24, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Haijing Cao, Qing Zhang, Robert C. Frye
  • Patent number: 9306450
    Abstract: Various embodiments of a high voltage charge pump are described. One embodiment is a charge pump circuit that comprises a plurality of switching stages each including a clock input, a clock input inverse, a clock output, and a clock output inverse. The circuit further comprises a plurality of pumping capacitors, wherein one or more pumping capacitors are coupled to a corresponding switching stage. The circuit also comprises a maximum selection circuit coupled to a last switching stage among the plurality of switching stages, the maximum selection circuit configured to filter noise on the output clock and the output clock inverse of the last switching stage, the maximum selection circuit further configured to generate a DC output voltage based on the output clock and the output clock inverse of the last switching stage.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: April 5, 2016
    Assignee: King Abdullah University of Science and Technology
    Inventors: Ahmed A. Emira, Mohamed Abdelghany, Mohannad Yomn Elsayed, Amro M. Elshurafa, Khaled Nabil Salama
  • Patent number: 9105580
    Abstract: A semiconductor device includes a semiconductor construct including a semiconductor substrate and an external connection electrode provided to protrude on a surface of the semiconductor substrate, a base plate on which the semiconductor construct is installed, and a sealing layer stacked on the semiconductor substrate except for the external connection electrode and on the base plate including a side surface of the semiconductor substrate.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: August 11, 2015
    Assignee: TERA PROBE, INC.
    Inventor: Shinji Wakisaka
  • Patent number: 9064927
    Abstract: A semiconductor device manufacturing method includes forming a first capacitance film formed on the lower electrode; forming an intermediate electrode in a first region on the first capacitance film, wherein the first capacitance is interposed between the intermediate electrode and the lower electrode; forming a second capacitance film on the intermediate electrode to be interposed between the first capacitance film and the second capacitance film; and forming an upper electrode, wherein at least a portion of the second capacitance film is interposed between the upper electrode and the intermediate electrode; the upper electrode extending to a second region outside the first region, and having at least the first capacitance film interposed between the upper electrode and the lower electrode in the second region.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: June 23, 2015
    Assignee: ROHM CO., LTD.
    Inventor: Satoshi Kageyama
  • Patent number: 9059192
    Abstract: A metal-insulation-metal (MIM) device including a first metal layer, a first insulation layer, a second metal layer, and a second insulation layer is provided. The first insulation layer is disposed on the first metal layer. The second metal layer is disposed on a part of the first insulation layer. The second insulation layer is disposed on a side wall of the second metal layer and on another part of the first insulation layer. A width of the first insulation layer under the second metal layer and the second insulation layer parallel to the first metal layer is greater than a with of the second metal layer parallel to the first metal layer. A manufacture method of an MIM device is also provided.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: June 16, 2015
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Hung-Sui Lin, Mao-Hsiung Lin
  • Publication number: 20150147824
    Abstract: A silicon precursor composition is described, including a silylene compound selected from among: silylene compounds of the formula: wherein each of R and R1 is independently selected from organo substituents; amidinate silylenes; and bis(amidinate) silylenes. The silylene compounds are usefully employed to form high purity, conformal silicon-containing films of Si02, Si3N4, SiC and doped silicates in the manufacture of microelectronic device products, by vapor deposition processes such as CVD, pulsed CVD, ALD and pulsed plasma processes. In one implementation, such silicon precursors can be utilized in the presence of oxidant, to seal porosity in a substrate comprising porous silicon oxide by depositing silicon oxide in the porosity at low temperature, e.g., temperature in a range of from 50° C. to 200° C.
    Type: Application
    Filed: May 22, 2013
    Publication date: May 28, 2015
    Applicant: ADVANCED TECHNOLOGY MATERIALS, INC.
    Inventors: Thomas M. Cameron, Susan V. DiMeo, Bryan C. Hendrix, Weimin Li
  • Publication number: 20150137201
    Abstract: A methods for fabricating a capacitor structure includes fabricating polysilicon structures on a semiconductor substrate. The method further includes fabricating M1 to diffusion (MD) interconnects on the semiconductor substrate. The polysilicon structures are disposed in an interleaved arrangement with the MD interconnects. The method also includes selectively connecting the interleaved arrangement of the MD interconnects and/or the polysilicon structures as the capacitor structure.
    Type: Application
    Filed: April 29, 2014
    Publication date: May 21, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Bruce Sokki LEE, Seyfollah Seyfollahi BAZARJANI, Liang DAI
  • Patent number: 9018060
    Abstract: A variable capacitance sensor includes a first conductive electrode comprising electrically interconnected first conductive sheets; a second conductive electrode comprising electrically interconnected second conductive sheets, wherein the first conductive sheets are at least partially interleaved with the second conductive sheets, and wherein the second conductive electrode is electrically insulated from the first conductive electrode; and microporous dielectric material at least partially disposed between and contacting the first conductive sheets and the second conductive sheets. A method of making a variable capacitance sensor by replacing ceramic in a ceramic capacitor with a microporous material is also disclosed.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: April 28, 2015
    Assignee: 3M Innovative Properties Company
    Inventors: Stefan H. Gryska, Michael C. Palazzotto
  • Patent number: 9012297
    Abstract: Structures and methods of forming moisture barrier capacitor on a semiconductor component are disclosed. The capacitor is located on the periphery of a semiconductor chip and includes an inner plate electrically connected to a voltage node, an outer plate with fins for electrically connecting to a different voltage node.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 21, 2015
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Helmut Horst Tews
  • Patent number: 9012299
    Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: April 21, 2015
    Assignee: Spansion LLC
    Inventors: Steven Avanzino, Tzu-Ning Fang, Swaroop Kaza, Dong-Xiang Liao, Wai Lo, Christie Marrian, Sameer Haddad
  • Patent number: 9000562
    Abstract: A method for forming a metal-insulator-metal (MIM) capacitor includes forming a capacitor bottom plate and a metal interconnect feature on a substrate. A dielectric layer having a predetermined thickness is then formed. The dielectric layer has a first portion overlying the capacitor bottom plate and a second portion overlying the metal interconnect feature. The dielectric layer is processed to adjust the thickness of the first portion of the dielectric layer relative the thickness of the second portion of the dielectric layer. Processing can include etching the first portion of the dielectric layer or adding dielectric material to the second portion of the dielectric layer. A capacitor top plate is formed over the first portion of the dielectric layer to complete the MIM structure.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shean-Ren Horng, Kuo-Nan Hou, Feng-Liang Lai
  • Patent number: 8980723
    Abstract: An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: March 17, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Kaiping Liu, Imran Mahmood Khan, Richard Allen Faust
  • Patent number: 8980709
    Abstract: A resistive-switching memory element is described. The memory element includes a first electrode, a porous layer over the first electrode including a point defect embedded in a plurality of pores of the porous layer, and a second electrode over the porous layer, wherein the nonvolatile memory element is configured to switch between a high resistive state and a low resistive state.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: March 17, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Tony P. Chiang, Chi-I Lang, Prashant B. Phatak
  • Patent number: 8975135
    Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: March 10, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Kaiping Liu, Amitava Chatterjee, Imran Mahmood Khan
  • Patent number: 8962347
    Abstract: A ferroelectric capacitor formed above a semiconductor substrate includes a lower electrode, a dielectric film (ferroelectric film) having ferroelectric characteristics, and an upper electrode. The upper electrode includes a conductive oxide film made of a ferroelectric material to which conductivity is provided by adding a conductive material such as Ir, and the conductive oxide film is in contact with the dielectric film.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8957500
    Abstract: A high-voltage metal capacitor with easy integration into existing semiconductor manufacturing processes can provide isolation capacitors up to several kilovolts. The capacitor includes a support layer with internal structure, including a lower place, a bond pad on the support layer, an upper plate disposed on the support layer, the upper plate being arranged above the lower plate, a dielectric layer, at least part of which is between the lower and upper plates, and a passivation layer, at least part of which covers at least part of the upper plate and part of the dielectric layer. A first opening extends from the surface through the passivation and dielectric layers to the lower plate, and a second opening extends from the surface through the passivation layer to the upper plate. A method of manufacturing the capacitor.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: February 17, 2015
    Assignee: NXP B.V.
    Inventors: Jerôme Guillaume Anna Dubois, Piet Wessels
  • Publication number: 20150037960
    Abstract: A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor.
    Type: Application
    Filed: October 15, 2014
    Publication date: February 5, 2015
    Inventors: Chun Hua CHANG, Der-Chyang YEH, Kuang-Wei CHENG, Yuan-Hung LIU, Shang-Yun HOU, Wen-Chih CHIOU, Shin-Puu JENG
  • Patent number: 8946046
    Abstract: A method of forming a non-volatile memory device, includes forming a first electrode above a substrate, forming a dielectric layer overlying the first electrode, forming an opening structure in a portion of the dielectric layer to expose a surface of the first electrode having an aspect ratio, forming a resistive switching material overlying the dielectric layer and filling at least a portion of the opening structure using a deposition process, the resistive switching material having a surface region characterized by a planar region and an indent structure, the indent structure overlying the first electrode, maintaining a first thickness of resistive switching material between the planar region and the first electrode, maintaining a second thickness of resistive switching material between the indent structure and the first electrode, wherein the first thickness is larger than the second thickness, and forming a second electrode overlying the resistive switching material including the indent structure.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: February 3, 2015
    Assignee: Crossbar, Inc.
    Inventor: Sung Hyun Jo
  • Publication number: 20140377933
    Abstract: A method for producing a metal structure in a semiconductor substrate includes: producing an opening in the rear side of the semiconductor substrate in the area of the metal structure to be produced, which extends to the front side layer structure; filling the opening at least partially with a metal so that a metal structure is created which extends from the rear side of the semiconductor substrate to the front side layer structure; masking the rear side of the semiconductor substrate for a trench process for exposing the metal structure in such a way that the trench mask includes a lattice structure in an area adjacent to the metal structure; producing an isolation trench adjacent to the metal structure, the metal structure acting as a lateral etch stop and the lattice structure being laterally undercut in the trench mask; and applying a sealing layer to the mask.
    Type: Application
    Filed: June 16, 2014
    Publication date: December 25, 2014
    Applicant: ROBERT BOSCH GMBH
    Inventor: Heribert WEBER
  • Patent number: 8906704
    Abstract: A lower electrode film is formed above a substrate. A ferroelectric film is formed above the lower electrode film. An amorphous intermediate film of a perovskite-type conductive oxide is formed above the ferroelectric film. A first upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the intermediate film. The intermediate film is crystallized by carrying out a first heat treatment in an atmosphere containing an oxidizing gas after the formation of the first upper electrode film. After the first heat treatment, a second upper electrode film comprising oxide of at least one metal selected from a group of Pt, Pd, Rh, Ir, Ru, and Os is formed on the first upper electrode film, at a temperature lower than the growth temperature for the first upper electrode film.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: December 9, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Wensheng Wang
  • Patent number: 8901704
    Abstract: An integrated circuit and a manufacturing method thereof are provided. A chip size can be reduced by forming a memory device in which a ferroelectric capacitor region is laminated on a DRAM. The integrated circuit includes a cell array region having a capacitor, a peripheral circuit region, and a ferroelectric capacitor region being formed on an upper layer of the cell array region and the peripheral circuit region, and having a ferroelectric capacitor device.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 2, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hee Bok Kang
  • Patent number: 8884288
    Abstract: The present invention provides a semiconductor structure for testing MIM capacitors. The semiconductor structure comprises: a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween and connected with the second circuit area; a top plate located within the first dielectric layer closer to the first metal layer and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate with an insulation layer therebetween and connected with the second circuit area. The second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 11, 2014
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Qiang Li, Zhuanlan Sun, Changhui Yang
  • Patent number: 8877521
    Abstract: A manufacturing method for a semiconductor device, the method including forming a thin film transistor by forming a polysilicon thin film on an insulating substrate, forming a gate electrode via a gate insulating film, and forming source/drain regions and a channel region by ion implantation in the polysilicon thin film by using the gate electrode as a mask, forming an interconnection layer on an interlayer dielectric film covering this thin film transistor and forming a first contact to be connected to the thin film transistor through the interlayer dielectric film, forming a silicon hydronitride film on the interlayer dielectric film so as to cover the interconnection layer, forming a lower electrode on this silicon hydronitride film and forming a second contact to be connected to the interconnection layer through the silicon hydronitride film, and forming a ferroelectric layer on the lower electrode.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: November 4, 2014
    Assignee: Gold Charm Limited
    Inventor: Hiroshi Tanabe
  • Patent number: 8872238
    Abstract: The present invention is related to a method for manufacturing a low defect interface between a dielectric material and an III-V compound. More specifically, the present invention relates to a method for manufacturing a passivated interface between a dielectric material and an III-V compound. The present invention is also directed to a device comprising a low defect interface between a dielectric material and an III-V compound that has improved performance.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: October 28, 2014
    Assignee: IMEC
    Inventor: Clement Merckling
  • Patent number: 8865559
    Abstract: Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: October 21, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes, Arup Bhattacharyya
  • Publication number: 20140295640
    Abstract: Methods of forming semiconductor devices. The method includes forming a capacitor array comprising a plurality of cells in a two-dimensional grid. The step of forming includes forming a plurality of operational capacitors in a first subset of the plurality of cells along a diagonal of the array, the plurality of operational capacitors comprising a first operational capacitor formed in a cell at a first edge of the capacitor array and at a first edge of the diagonal of the capacitor array. The step of forming also includes forming a plurality of dummy patterns about the plurality of operational capacitors in the capacitor array in a second subset of the plurality of cells to achieve symmetry in the grid about the diagonal. The method also includes electrically coupling each one of the plurality of operational capacitors to another one of the plurality of operational capacitors.
    Type: Application
    Filed: June 12, 2014
    Publication date: October 2, 2014
    Inventors: Chi-Feng HUANG, Chia-Chung CHEN
  • Patent number: 8847353
    Abstract: Capacitance blocks (first block and second block) respectively formed on two different adjacent common pad electrodes are electrically connected in series through an upper electrode. A distance between two adjacent capacitance blocks connected in series through an upper electrode film for the upper electrode corresponds to a distance between opposing lower electrodes disposed in an outermost perimeter of each capacitance block, and is two or less times than a total film thickness of the upper electrode film embedded between the two adjacent capacitance blocks.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 30, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Eiji Hasunuma
  • Patent number: 8841747
    Abstract: A method for using a metal bilayer is disclosed. First, a bottom electrode is provided. Second, a dielectric layer which is disposed on and is in direct contact with the lower electrode is provided. Then, a metal bilayer which serves as a top electrode in a capacitor is provided. The metal bilayer is disposed on and is in direct contact with the dielectric layer. The metal bilayer consists of a noble metal in direct contact with the dielectric layer and a metal nitride in direct contact with the noble metal.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: September 23, 2014
    Assignee: Nanya Technology Corp.
    Inventors: Vassil Antonov, Vishwanath Bhat, Chris Carlson
  • Publication number: 20140252547
    Abstract: The present invention relates to a semiconductor device and a process for fabricating the same. In one embodiment, the semiconductor device includes a substrate and a plurality of integrated passive devices. The integrated passive devices are disposed on the substrate and include at least two capacitors which have different capacitance values.
    Type: Application
    Filed: March 8, 2013
    Publication date: September 11, 2014
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: ADVANCED SEMICONDUCTOR ENGINEERING, Inc.
  • Patent number: 8828838
    Abstract: An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a capacitor having a doped region disposed in a semiconductor substrate, a dielectric layer disposed over the doped region, and an electrode disposed over the dielectric layer. At least one post feature embedded in the electrode.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Ming Zhu
  • Patent number: 8828837
    Abstract: In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. In alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: September 9, 2014
    Assignee: Spansion LLC
    Inventors: Steven Avanzino, Tzu-Ning Fang, Swaroop Kaza, Dongxiang Liao, Wai Lo, Christie Marrian, Sameer Haddad
  • Patent number: 8822235
    Abstract: An electronic component is provided on a substrate. A thin-film capacitor is attached to the substrate, the thin-film capacitor includes a pyrochlore or perovskite dielectric layer between a plurality of electrode layers, the electrode layers being formed from a conductive thin-film material. A reactive barrier layer is deposited over the thin-film capacitor. The reactive barrier layer includes an oxide having an element with more than one valence state, wherein the element with more than one valence state has a molar ratio of the molar amount of the element that is in its highest valence state to its total molar amount in the barrier of 50% to 100%. Optionally layers of other materials may intervene between the capacitor and reactive barrier layer. The reactive barrier layer may be paraelectric and the electronic component may be a tunable capacitor.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 2, 2014
    Assignee: BlackBerry Limited
    Inventors: Marina Zelner, Mircea Capanu, Paul Bun Cheuk Woo, Susan C. Nagy
  • Publication number: 20140239448
    Abstract: Disclosed are an interdigitated capacitor and an interdigitated vertical native capacitor, each having a relatively low (e.g., zero) net coefficient of capacitance with respect to a specific parameter. For example, the capacitors can have a zero net linear temperature coefficient of capacitance (Tcc) to limit capacitance variation as a function of temperature or a zero net quadratic voltage coefficient of capacitance (Vcc2) to limit capacitance variation as a function of voltage. In any case, each capacitor can incorporate at least two different plate dielectrics having opposite polarity coefficients of capacitance with respect to the specific parameter due to the types of dielectric materials used and their respective thicknesses. As a result, the different dielectric plates will have opposite effects on the capacitance of the capacitor that cancel each other out such that the capacitor has a zero net coefficient of capacitance with respect to specific parameter.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Frederick G. Anderson, Natalie B. Feilchenfeld, Zhong-Xiang He, Theodore J. Letavic, Yves T. Ngu
  • Patent number: 8815678
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: August 26, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Patent number: 8772847
    Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 8753973
    Abstract: According to one embodiment, a method of fabricating a semiconductor memory device includes patterning a first memory cell layer and a first interconnect layer to form a first structure of a linear pattern in a first region and a second structure in a second region, forming a second interconnect layer and a second memory cell layer, and patterning the second memory cell layer and the second interconnect layer to form, in the first region, a third structure having a linear pattern and having a folded pattern immediately on the second structure. The method further includes removing the second memory cell layer and the second interconnect layer in the folded pattern, and the first memory cell layer of the second structure positioned under the folded pattern.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hironobu Furuhashi
  • Patent number: 8753950
    Abstract: A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Douglas D. Coolbaugh, Keith E. Downes, Peter J. Lindgren, Anthony K. Stamper
  • Patent number: 8749022
    Abstract: A capacitor device includes a substrate including a first well having a first conductivity type and a first voltage applied thereto and a second well having a second conductivity type and a second voltage applied thereto; and a gate electrode disposed on an upper portion of the first well or an upper portion of the second well in such a way that the gate electrode is insulated from the first well or the second well, wherein capacitances of the capacitor device include a first capacitance between the first well and the second well and a second capacitance between the first well or the second well and the gate electrode.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Ryul Chang, Hwa-Sook Shin
  • Patent number: 8735954
    Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film that is formed over the semiconductor substrate; a capacitor that is formed over the first insulating film and is formed by sequentially stacking a lower electrode, a capacitor dielectric film, and an upper electrode; a second insulating film that is formed over the capacitor and has a hole including the entire region of the upper electrode in plan view; and a conductor plug that is formed in the hole and contains tungsten.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: May 27, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoya Sashida
  • Patent number: 8722504
    Abstract: A method for reducing leakage current in DRAM capacitor stacks by introducing dielectric interface layers between the electrodes and the bulk dielectric material. The dielectric interface layers are typically amorphous dielectric materials with a k value between about 10 and about 30 and are less than about 1.5 nm in thickness. Advantageously, the thickness of each of the dielectric interface layers is less than 1.0 nm. In some cases, only a single dielectric interface layer is used between the bulk dielectric material and the second electrode.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: May 13, 2014
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Wim Deweerd, Hiroyuki Ode
  • Patent number: 8703552
    Abstract: A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: April 22, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni