Abstract: A semiconductor device includes an internal circuit and a cell-type power decoupling capacitor. The cell-type power decoupling capacitor is formed on a semiconductor substrate using a stack cell capacitor process. The cell-type power decoupling capacitor stabilizes a supply voltage to provide the stabilized supply voltage to the internal circuit. Accordingly, the semiconductor device including the cell-type power decoupling capacitor may be insensitive to power noise and may occupy a small area on a chip.

Abstract: An organic light emitting diode display includes a substrate; a first capacitor electrode provided over the substrate and including polysilicon; an insulating layer provided over the first capacitor electrode; and a second capacitor electrode provided over the insulating layer and including a first lower metal layer overlapping with the first capacitor electrode and a first upper metal layer. The first upper metal layer includes a doping opening configured to expose at least a portion of the first lower metal layer.

Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming spacers adjoining sidewalls of the gate stacks, wherein at least one of the spacers extends beyond an edge the isolation feature. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.

Abstract: In one general aspect, a semiconductor processing method can include forming an N-type silicon region disposed within a P-type silicon substrate. The method can also include forming a field oxide (FOX) layer in the P-type silicon substrate where the FOX layer includes an opening exposing at least a portion of the N-type silicon region. The method can further include forming a reduced surface field (RESURF) oxide (ROX) layer having a first portion disposed on the exposed N-type silicon region and a second portion disposed on the FOX layer where the ROX layer includes a first dielectric layer in contact with the exposed N-type silicon region and a second dielectric layer disposed on the first dielectric layer. The method can further include forming a doped polysilicon layer having a first portion disposed on the first portion of the ROX layer and a second portion disposed on the second portion of the ROX layer.

Abstract: A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.

Abstract: The semiconductor device comprises a device isolation region formed in a semiconductor substrate, a lower electrode formed in a device region defined by the device isolation region and formed of an impurity diffused layer, a dielectric film of a thermal oxide film formed on the lower electrode, an upper electrode formed on the dielectric film, an insulation layer formed on the semiconductor substrate, covering the upper electrode, a first conductor plug buried in a first contact hole formed down to the lower electrode, and a second conductor plug buried in a second contact hole formed down to the upper electrode, the upper electrode being not formed in the device isolation region. The upper electrode is not formed in the device isolation region, whereby the short-circuit between the upper electrode and the lower electrode in the cavity can be prevented.

Abstract: A capacitor device includes a substrate including a first well having a first conductivity type and a first voltage applied thereto and a second well having a second conductivity type and a second voltage applied thereto; and a gate electrode disposed on an upper portion of the first well or an upper portion of the second well in such a way that the gate electrode is insulated from the first well or the second well, wherein capacitances of the capacitor device include a first capacitance between the first well and the second well and a second capacitance between the first well or the second well and the gate electrode.

Abstract: A method of forming a field effect transistor (FET) capacitor includes forming a channel region; forming a gate stack over the channel region; forming a first extension region on a first side of the gate stack, the first extension region being formed by implanting a first doping material at a first angle such that a shadow region exists on a second side of the gate stack; and forming a second extension region on the second side of the gate stack, the second extension region being formed by implanting a second doping material at a second angle such that a shadow region exists on the first side of the gate stack.

Abstract: Methods for capacitor fabrication include doping a capacitor region of a semiconductor layer in a semiconductor-on-insulator substrate; partially etching the semiconductor layer to produce a first terminal layer comprising doped semiconductor fins on a remaining base of doped semiconductor; forming a dielectric layer over the first terminal layer; and forming a second terminal layer over the dielectric layer in a finFET process.

Abstract: A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater degree than any lateral trimming of width of the spaced first features while laterally trimming width of the spaced second features. After laterally trimming of the second features, spacers are formed on sidewalls of the spaced first features and on sidewalls of the spaced second features. The spacers are of some different composition from that of the spaced first features and from that of the spaced second features. After forming the spacers, the spaced first features and the spaced second features are removed from the substrate. The substrate is processed through a mask pattern comprising the spacers. Other embodiments are disclosed.

Abstract: A method of forming a capacitor structure comprises: forming a doped polysilicon layer on an underlying dielectric layer; forming a dielectric stack on the doped polysilicon layer; forming a contact hole in the dielectric stack to expose a surface region of the doped polysilicon layer; forming a conductive contact plug that fills the contact hole and is in contact with the exposed surface of the doped polysilicon layer; forming a plurality of trenches in the dielectric stack such that each trench exposes a corresponding surface region of the doped polysilicon layer; forming a conductive bottom capacitor plate on exposed surfaces of the of the dielectric stack and on exposed surfaces of the doped polysilicon layer; forming a capacitor dielectric layer on the bottom capacitor plate; and forming a conductive top capacitor plate on the capacitor dielectric layer.

Abstract: A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost regions which are different in composition from elevationally outermost regions of the second spaced features. The first and second spaced features alternate with one another. Every other first feature is removed from the substrate and pairs of immediately adjacent second features are formed which alternate with individual of remaining of the first features. After such act of removing, the substrate is processed through a mask pattern comprising the pairs of immediately adjacent second features which alternate with individual of the remaining of the first features. Other embodiments are disclosed.

Abstract: A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.

Abstract: An integrated circuit includes a substrate and a first metal-insulator-metal (MIM) capacitor disposed over the substrate. The MIM capacitor includes a first metallic capacitor plate disposed over the substrate. At least one first insulator layer is disposed over the first metallic capacitor plate. A second metallic capacitor plate is disposed over the at least one first insulator layer. At least one first dielectric layer is disposed over the substrate. At least a portion of the at least one first dielectric layer is disposed between the first metallic capacitor plate and the at least one first insulator layer.

Abstract: Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The first and third doped regions are of the same type sandwiching the second doped region of the second type. A first input terminal is coupled to the first and third doped regions and a second terminal is coupled to the second doped region. At the interfaces of the doped regions are first and second depletion regions whose width can be varied by varying the voltage across the terminals from zero to full reverse bias.

Abstract: The present invention is a method for producing a capacitor. The method includes applying a dielectric substance (ex.—silicon nitride) to a first gold seed layer, the first gold seed layer being formed on a wafer. A second gold seed layer is formed upon the dielectric substance and first gold seed layer. Gold is electroplated into a photoresist to form a first set of 3-D capacitor elements on the second gold seed layer. A first copper layer is electroplated onto the second gold seed layer. Gold is electroplated into a photoresist to form a second set of 3-D capacitor elements, the second set of 3-D elements being formed at least partially within the first copper layer and being connected to the first set of 3-D elements. A second copper layer is electroplated onto the first copper layer. Then, both copper layers are removed to provide (ex.—form) the capacitor.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: The semiconductor device comprises a device isolation region formed in a semiconductor substrate, a lower electrode formed in a device region defined by the device isolation region and formed of an impurity diffused layer, a dielectric film of a thermal oxide film formed on the lower electrode, an upper electrode formed on the dielectric film, an insulation layer formed on the semiconductor substrate, covering the upper electrode, a first conductor plug buried in a first contact hole formed down to the lower electrode, and a second conductor plug buried in a second contact hole formed down to the upper electrode, the upper electrode being not formed in the device isolation region. The upper electrode is not formed in the device isolation region, whereby the short-circuit between the upper electrode and the lower electrode in the cavity can be prevented.

Abstract: Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.

Abstract: A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost regions which are different in composition from elevationally outermost regions of the second spaced features. The first and second spaced features alternate with one another. Every other first feature is removed from the substrate and pairs of immediately adjacent second features are formed which alternate with individual of remaining of the first features. After such act of removing, the substrate is processed through a mask pattern comprising the pairs of immediately adjacent second features which alternate with individual of the remaining of the first features. Other embodiments are disclosed.

Abstract: The present invention provides an integrated high voltage capacitor, a method of manufacture therefore, and an integrated circuit chip including the same. The integrated high voltage capacitor, among other features, includes a first capacitor plate (120) located over or in a semiconductor substrate (105), and an insulator (130) located over the first capacitor plate (120), at least a portion of the insulator (130) comprising an interlevel dielectric layer (135, 138, 143, or 148). The integrated high voltage capacitor further includes capacitance uniformity structures (910) located at least partially within the insulator (130) and a second capacitor plate (160) located over the insulator (130).

Abstract: A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater degree than any lateral trimming of width of the spaced first features while laterally trimming width of the spaced second features. After laterally trimming of the second features, spacers are formed on sidewalls of the spaced first features and on sidewalls of the spaced second features. The spacers are of some different composition from that of the spaced first features and from that of the spaced second features. After forming the spacers, the spaced first features and the spaced second features are removed from the substrate. The substrate is processed through a mask pattern comprising the spacers. Other embodiments are disclosed.

Abstract: A decoupling capacitor includes a pair of MOS capacitors formed in wells of opposite plurality. Each MOS capacitor has a set of well-ties and a high-dose implant, allowing high frequency performance under accumulation or depletion biasing. The top conductor of each MOS capacitor is electrically coupled to the well-ties of the other MOS capacitor and biased consistently with logic transistor wells. The well-ties and/or the high-dose implants of the MOS capacitors exhibit asymmetry with respect to their dopant polarities.

Abstract: A method and system in which an embedded memory is fabricated in accordance with a conventional logic process includes one or more non-volatile memory cells, each having an access transistor and a capacitor, which share a common floating gate electrode. The coupling capacitor is provided with a dielectric layer having a thickness greater than the dielectric layer of the access transistor. Regions under the capacitor are implanted with a high dose implant to form an electrically shorted doped area in the channel region of the capacitor. The high dose implant improves the coupling ratio of the capacitor and enhances the uniformity of the capacitor's oxide layer.

Abstract: A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.

Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.

Abstract: A buried decoupling capacitor apparatus and method are provided. According to various embodiments, a buried decoupling capacitor apparatus includes a semiconductor-on-insulator substrate having a buried insulator region and top semiconductor region on the buried insulator region. The apparatus embodiment also includes a first capacitor plate having a doped region in the top semiconductor region in the semiconductor-on-insulator substrate. The apparatus embodiment further includes a dielectric material on the first capacitor plate, and a second capacitor plate on the dielectric material. According to various embodiments, the first capacitor plate, the dielectric material and the second capacitor plate form a decoupling capacitor for use in an integrated circuit.

Abstract: A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.

Abstract: Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, as well as a method of forming components with segments polysilicon elements.

Abstract: According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor.

Abstract: A method for making a device including a capacitive structure is disclosed. One embodiment provides a carrier layer having a surface. A first dielectric layer is formed on the surface. A silicon layer including silicon grains is formed on the first dielectric layer using a deposition process. A second dielectric layer is formed on the second silicon layer. A layer of an electrically conductive material is formed on the dielectric layer. A temperature process for heating at least the first dielectric layer is performed. The temperature and duration of the temperature process is selected such that the first dielectric layer is modified so that the silicon layer is electrically connected to the carrier layer.

Abstract: Methods of making thin film capacitors formed on foil by forming onto a thin film dielectric in a single deposition event an integrally complete top electrode having a minimum thickness of at least 1 micron.

Abstract: A phase change device may be formed by forming a phase change material and an electrode in a pore in an insulator. The phase change material fills less of the pore than the electrode.

Abstract: A capacitive element, includes: an active region parted by an element isolation region formed in a semiconductor substrate; a first electrode formed of a diffusion layer in the active region; an insulating layer formed on the first electrode; and a second electrode formed on a planar surface of the first electrode via the insulating layer, wherein the second electrode is formed within the active region and within the first electrode in a planar layout.

Abstract: The nitride film forming method comprises the first step of loading a semiconductor substrate 12 into a reaction furnace, and decompressing the inside of the reaction furnace 14 to remove oxygen and water from the inside of the reaction furnace 14 and the semiconductor substrate 12, the second step of heating the reaction furnace 14 to further remove the oxygen and the water from the reaction furnace 14 and the semiconductor substrate 12, and the third step of purifying nitrogen gas to have the oxygen concentration to be 1 ppb or below, and performing thermal processing with the purified nitrogen gas being fed into the reaction furnace to form a nitride film 56 over the semiconductor substrate 12. The thermal nitriding is performed using an ultrahigh-purity nitrogen gas of an oxygen concentration of 1 ppb or below, whereby nitrogen film of very good quality can be formed without setting the thermal processing temperature very high.

Abstract: Methods for processing a substrate in a processing chamber using dual RF frequencies are provided herein. In some embodiments, a method of processing a substrate includes forming a plasma of a polymer forming chemistry to etch a feature into a substrate disposed on a substrate support in a process chamber while depositing a polymer on at least portions of the feature being etched. A low frequency and a high frequency RF signal are applied to an electrode disposed in the substrate support. The method further includes controlling the level of polymer formation on the substrate, wherein controlling the level of polymer formation comprises adjusting a power ratio of the high frequency to the low frequency RF signal.

Abstract: A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.

Abstract: A semiconductor device may include a capacitor and a transistor on a silicon-on-insulator (SOI) substrate and a method for manufacturing the semiconductor device may include forming such a structure. A semiconductor device, formed on a silicon-on-insulator structure including first and second silicon layers and a insulating layer buried between the first and the second silicon layers, may include a capacitor including one electrode formed in a doped region of the first silicon layer and the other electrode formed in a well region of the second silicon layer.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; depositing a first protective layer made of carbon or made of a carbon containing material over said memory cell region and peripheral device region; forming a mask layer on said first protective layer in said memory cell region; exposing said cap of said at least one gate stack in said peripheral device region by removing said first protective layer in said peripheral device region in an etch step wherein said mask layer acts as a mask in said memory cell region; removing said mask layer and said first protective layer from said memory cell region; for

Abstract: Laser scan annealing of integrated circuits offers advantages compared to rapid thermal annealing and furnace annealing, but can induce overheating in regions of components with polysilicon layers. Segmented polysilicon elements to reduce overheating is disclosed, as well as a method of forming components with segments polysilicon elements.

Abstract: A method for manufacturing passive components is disclosed. First, a substrate is provided, and a connecting region, a capacitor region and an inductance region are defined in the substrate. The substrate includes a first metal layer and an insulating layer on the first metal layer. Subsequently, the insulating layer is etched, and then the first metal layer is etched. Thus, an outer connecting pad in the connecting region and a bottom electrode in the capacitor region are formed simultaneously, and a part of the insulating layer on the bottom electrode remains. Thereafter, a dielectric layer is deposited, and then a dual damascene copper process is performed to form an inductance structure and a top electrode of a capacitor in the dielectric layer simultaneously. Next, a passive layer is deposited and an etching process is thereafter performed to expose the outer connecting pad.

Abstract: Provided are a capacitor of a semiconductor device using a TiO2 dielectric layer and a method of fabricating the capacitor. The capacitor includes a Ru bottom electrode formed on a semiconductor substrate, an rutile-structures RuO2 pretreated layer which is formed by oxidizing the Ru bottom electrode, a TiO2 dielectric layer which has a rutile crystal structure corresponding to the rutile crystal structure of the RuO2 pretreated layer and is doped with an impurity, and a top electrode formed on the TiO2 dielectric layer. The method includes forming a Ru bottom electrode on a semiconductor substrate, forming a rutile-structured RuO2 pretreated layer by oxidizing a surface of the Ru bottom electrode, forming a TiO2 dielectric layer to have a rutile crystal structure corresponding to the rutile crystal structure of the RuO2 pretreated layer on the a RuO2 pretreated layer and doping the TiO2 dielectric layer with an impurity, and forming a top electrode on the TiO2 dielectric layer.

Abstract: A semiconductor device includes a first MOS type capacitor having a first insulating film and a first electrode that are formed on a semiconductor substrate, and a second MOS type capacitor having a second insulating film and a second electrode that are formed on the semiconductor substrate. The first electrode has a first concentration difference as a difference when an impurity concentration in an interface region with the first insulating film is subtracted from an impurity concentration in a top portion of the first electrode. The second electrode has a second concentration difference as a difference when an impurity concentration in an interface region with the second insulating film is subtracted from an impurity concentration in a top portion of the second electrode. The second concentration difference is larger than the first concentration difference.

Abstract: A method is provided for fabricating a semiconductor component that includes a capacitor having a high capacitance per unit area. The component is formed in and on a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The method comprises forming a first capacitor electrode in the first semiconductor layer and depositing a dielectric layer comprising Ba1-xCaxTi1-yZryO3 overlying the first capacitor electrode. A conductive material is deposited and patterned to form a second capacitor electrode overlying the dielectric layer, thus forming a capacitor having a high dielectric constant dielectric. An MOS transistor in then formed in a portion of the second semiconductor layer, the MOS transistor, and especially the gate dielectric of the MOS transistor, formed independently of forming the capacitor and electrically isolated from the capacitor.

Abstract: The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiO2 film that is to be a gate insulation film of a high voltage MOS transistor is formed on a whole surface of a P-type semiconductor substrate. A photoresist layer is selectively formed in a high voltage MOS transistor formation region and on a part of a SiO2 film covering edges of trench isolation films adjacent to a capacitor formation region, and the SiO2 film is removed by etching using this photoresist layer as a mask. Since the photoresist layer functions as a mask in this etching, the edges of the trench isolation films adjacent to the capacitor are not cut too deep. The SiO2 film remaining in this etching and a SiO2 film to be formed thereafter form a capacitor insulation film.

Abstract: A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; forming a first contact hole between two neighboring gate stacks in said memory cell region; depositing a first protective layer over said memory cell region and peripheral device region; exposing said cap of said at least one gate stack in said peripheral device region; modifying said exposed cap of said at least one gate stack in said peripheral device region in a process step wherein said first protective layer acts as a mask in said memory cell region; forming a second protective layer over said modified cap in said peripheral device region; partly

Abstract: A capacitor comprising: a metal plate a doped semiconductor plate; and a dielectric sandwiched therebetween.

Abstract: The invention includes a method of forming a metal-comprising mass for a semiconductor construction. A semiconductor substrate is provided, and a metallo-organic precursor is provided proximate the substrate. The precursor is exposed to a reducing atmosphere to release metal from the precursor, and subsequently the released metal is deposited over the semiconductor substrate. The invention also includes capacitor constructions, and methods of forming capacitor constructions.

Abstract: An integrated circuit biases the substrate and well using voltages other than those used for power and ground. Tap cells inside the standard cell circuits are removed. New tap cells used to bias the substrate and well reside outside the standard cell circuits. The location of the new voltage power rails is designated prior to placement of the tap cells in the integrated circuit. The tap cells are then strategically placed near the power rails such that metal connections are minimized. Circuit density is thus not adversely impacted by the addition of the new power rails. Transistors are also placed inside the tap cells to address electrostatic discharge issues during fabrication.