Abstract: There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face and a magnetization direction thereof varies corresponding to information; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face and becomes a reference for the information stored in the memory layer; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer and is formed of a non-magnetic layer, wherein an electron that is spin-polarized is injected in a lamination direction of a layered structure having the memory layer, the insulating layer, and the magnetization-fixed layer, and thereby the magnetization direction varies and a recording of information is performed with respect to the memory layer, and a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer.

Abstract: A method of manufacturing a bearing device component is provided. The bearing device includes a shaft and a sleeve that surrounds the shaft, and at least either one of the shaft and the sleeve is referred to as a work. The method includes: a process of forming a coating of an anti-sticking-lube polymer on the work; a process of applying a photoluminescence material to a range overlapping a range where the coating of the anti-sticking-lube polymer is formed; and a condition detecting process of causing the photoluminescence material to emit light by causing the work to be irradiated with excitation light that excites the photoluminescence material, and detecting an applied condition of the photoluminescence material based on the light emission of the photoluminescence material, thereby detecting a condition of the coating of the anti-sticking-lube polymer.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements formed utilizing two etches through all epitaxially grown layers. Each of these etches can be split to two separate processes specific to CMOS transistor etch and to memory element etch. The memory array device includes a plurality of gate conductors configured along a first axis, in parallel. Each FET of the memory cells adjacent to two gate conductors. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis.

Abstract: A method of manufacturing a magnetoresistive effect element includes forming a first electrode above a substrate, forming a metal layer of a metal material above the first electrode, forming a first magnetic layer above the metal layer, forming a tunnel insulating film above the first magnetic layer, forming a second magnetic layer above the tunnel insulating film, forming a second electrode layer above the second magnetic layer, patterning the second electrode layer, patterning the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer, while depositing sputtered particles of the metal film on side walls of the second magnetic layer, the tunnel insulating film, the first magnetic layer and the metal layer to form a sidewall metal layer, and oxidizing the sidewall metal layer to form an insulative sidewall metal oxide layer.

Abstract: A resistive memory device includes a stack comprising conductor layers and insulator layers, with the edges of the conductor layers and insulating layers exposed on the sides of the stack. An insulator is disposed on a first side of the stack to cover exposed edges of the conductor layers on the first side of the stack. A memory layer disposed over the stack and insulator, such that the memory layer is in electrical contact with edges of the conductor layers on a second side of the stack but is insulated from edges on the first side of the stack by the insulator. A conductive ribbon is disposed over the memory layer to form programmable memory elements where the conductive ribbon crosses edges of the conductor layers on the second side of the stack.

Abstract: Chemical modification of non-volatile magnetic random access memory (MRAM) magnetic tunnel junctions (MTJs) for film stack etching is described. In an example, a method of etching a MTJ film stack includes modifying one or more layers of the MTJ film stack with a phosphorous trifluoride (PF3) source to provide modified regions of the MTJ film stack. The modified regions of the MTJ film stack are removed by a plasma etch process.

Abstract: The present invention is directed to a method for manufacturing spin transfer torque magnetic random access memory (STTMRAM) devices. The method, which utilizes in-situ annealing and etch-back of the magnetic tunnel junction (MTJ) film stack, comprises the steps of depositing a barrier layer on top of a bottom magnetic layer and then depositing an interface magnetic layer on top of the barrier layer to form an MTJ film stack; annealing the MTJ film stack at a first temperature and then cool the MTJ film stack to a second temperature lower than the first temperature; etching away a top portion of the interface magnetic layer; and depositing at least one top layer on top of the etched interface magnetic layer. The method may further include the step of annealing the MTJ film stack at a third temperature between the first and second temperature after the step of depositing at least one top layer.

Abstract: A STT-MRAM comprises apparatus and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of a three-terminal magnetoresistive memory element having a voltage-gated recording. The first terminal, a bit line, is connected to the top magnetic reference layer, and the second terminal is located at the middle recording layer which is connected to the underneath select CMOS transistor through a VIA and the third one, a digital line, is a voltage gate with a narrow pillar underneath the memory layer across an insulating functional layer which is used to reduce the write current by manipulating the perpendicular anisotropy of the recording layer. The fabrication includes formation of a bottom electrode, formation of digital line, formation of memory cell & VIA connection and formation of the top bit line. Photolithography patterning and hard mask etch are used to form the digital line pillar and small memory pillar.

Abstract: A method of fabricating a miniaturized semiconductor device so as to form MTJ elements therein include the steps of depositing a magnetic tunnel junction (MTJ) precursor layer on a substrate and planarizing the precursor layer; forming a sacrificial and patternable dielectric layer on the MTJ precursor layer; patterning the sacrificial dielectric layer in accordance with predetermined placements and shapes of a to-be-formed hard mask, the patterning forming corresponding openings in the sacrificial dielectric layer; depositing an etch-resistant conductive material such as Cu in the openings for example by way of plating, and selectively removing the sacrificial dielectric layer so as to leave behind the etch-resistant conductive material in the form of a desired hard mask. Using the hard mask to etch and thus pattern the MTJ precursor layer so as to form MTJ elements having desired locations, sizes and shapes.

Abstract: Semiconductor memory devices are provided. The device may include may include first and second selection lines connected to each other to constitute a selection line group, a plurality of word lines sequentially stacked on each of the first and second selection lines, vertical electrodes arranged in a row between the first and second selection lines, a plurality of bit line plugs arranged in a row at each of both sides of the selection line group, and bit lines crossing the word lines and connecting the bit line plugs with each other.

Abstract: An ammonia-free method of depositing silicon nitride by way of plasma-enhanced chemical vapor deposition (PECVD). Source gases of silane (SiH4) and nitrogen (N2) are provided to a parallel-plate plasma reactor, in which energy is capacitively coupled to the plasma, and in which the wafer being processed has been placed at a support electrode. Low-frequency RF energy (e.g., 360 kHz) is applied to the support electrode; high-frequency RF energy (e.g., 13.56 MHz) is optionally provided to the parallel electrode. Process temperature is above 350° C., at a pressure of about 2.5 torr. Any hydrogen present in the resulting silicon nitride film is bound by N—H bonds rather than Si—H bonds, and is thus more strongly bound to the film. The silicon nitride can serve as passivation for ferroelectric material that may degrade electrically if contaminated by hydrogen.

Abstract: A semiconductor device and a method of manufacture are provided, such as a MTJ device and a method of manufacturing a MTJ device. The MTJ device may include a bottom electrode, a MTJ stack, and a top electrode, wherein the top electrode is formed using a hole-filling technique. The top electrode may have slanted sidewalls. The MTJ stack may be formed by depositing corresponding MTJ layers. A patterned mask may be formed and patterned over the MTJ layers to form an opening defining the top electrode. The opening is filled with a conductive material to form the top electrode. The top electrode is then used as a mask to pattern the MTJ layers, thereby forming a MTJ stack.

Abstract: An electronic component is provided on a substrate. A thin-film capacitor is attached to the substrate, the thin-film capacitor includes a pyrochlore or perovskite dielectric layer between a plurality of electrode layers, the electrode layers being formed from a conductive thin-film material. A reactive barrier layer is deposited over the thin-film capacitor. The reactive barrier layer includes an oxide having an element with more than one valence state, wherein the element with more than one valence state has a molar ratio of the molar amount of the element that is in its highest valence state to its total molar amount in the barrier of 50% to 100%. Optionally layers of other materials may intervene between the capacitor and reactive barrier layer. The reactive barrier layer may be paraelectric and the electronic component may be a tunable capacitor.

Abstract: A magnetic body structure including: a magnetic layer pattern; and a conductive pattern including a metallic glass alloy and covering at least a portion of the magnetic body structure.

Abstract: Embodiments relate to current sensors and methods. In an embodiment, a current sensor comprises a leadframe; a semiconductor die coupled to the leadframe; a conductor comprising a metal layer on the semiconductor die, the conductor comprising at least one bridge portion and at least two slots, a first slot having a first tip and a second slot having a second tip, a distance between the first and second tips defining a width of one of the at least one bridge portion, wherein the conductor is separated from the leadframe by at least a thickness of the semiconductor die, and the thickness is about 0.2 millimeters (mm) to about 0.7 mm; and at least one magnetic sensor element arranged on the die relative to and spaced apart from the one of the at least one bridge portion and more proximate the conductor than the leadframe.

Abstract: A STT-MRAM comprises apparatus and a method of manufacturing a spin-torque magnetoresistive memory and a plurality of a three-terminal magnetoresistive memory element having a voltage-gated recording. A bit line is coupled to the memory element through an upper electrode provided on the top surface of a reference layer, a select CMOS is coupled to the recording layer of the memory element through a middle second electrode and a VIA and a digital line is coupled to a voltage gate which is insulated from the recording layer by a dielectric layer and is used to adjust the switching write current. The fabrication includes formation of bottom digital line, formation of memory cell & VIA connection, formation of top bit line. Dual photolithography patterning and hard mask etch are used to form a small memory pillar. Ion implantation is used to convert a buried dielectric VIA into an electrical conducting path between middle memory cell and underneath CMOS device.

Abstract: A method for forming magnetic conductors includes forming a metal structure on a substrate. Plating surfaces are prepared on the metal structure for electroless plating by at least one of: masking surfaces of the metal structure to prevent electroless plating on masked surfaces and/or activating a surface of the metal structure. Magnetic material is electrolessly plated directly on the plating surfaces to form a metal and magnetic material structure.

Abstract: A magnetoresistive device includes an MR element including a metal layer, and an insulating portion made of magnesium oxide and in contact with the MR element. A method of manufacturing the magnetoresistive device includes the step of removing an unwanted magnesium oxide film that is formed by the magnesium oxide in the process of forming the insulating portion. In this step, the unwanted magnesium oxide film is wet etched by using an etchant containing an aqueous ammonia solution.

Abstract: A semiconductor device according to the present invention includes: an unit element which includes a first switch and a second switch, wherein each of the first switch and the second switch includes an electrical resistance changing layer whose state of electrical resistance is changed according to a polarity of an applied voltage, and each of the first switch and the second switch has two electrodes, and wherein one electrode of the first switch and one electrode of the second switch are connected each other to form a common node, and the other electrode of the first switch forms a first node, and the other electrode of the second switch forms a second node; a first wiring which is connected with the first node and forms a signal transmission line; and a second wiring which is connected with the second node and is connected with the first wiring through the unit element.

Abstract: A method of manufacturing a touch sensing panel includes providing a substrate, forming a plurality of first electrodes arranged on the substrate, the first electrodes being separated from each other, forming a photoresist layer on the plurality of first electrodes, forming a plurality of photoresist removing regions positioned to intersect the first electrodes and to be separated from each other on the photoresist layer, and forming a tunneling magnetoresistance (TMR) element layer and a second electrode layer comprising a plurality of second electrodes on the photoresist layer. The method provides a touch sensing panel capable of being driven at high speed and reduces manufacturing cost and time.

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

Abstract: According to embodiments of the present invention, a magnetoresistive device is provided. The magnetoresistive device includes a fixed magnetic layer structure having a fixed magnetization orientation along a first easy axis, a free magnetic layer structure having a variable magnetization orientation along a second easy axis, and an offsetting magnetic layer structure having a magnetization orientation along an axis at least substantially non-parallel to at least one of the first easy axis or the second easy axis, wherein the fixed magnetic layer structure, the free magnetic layer structure and the offsetting magnetic layer structure are arranged one over the other. According to further embodiments of the present invention, a method of forming a magnetoresistive device is also provided.

Abstract: A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.

Abstract: The present application relates to a ferroelectric memory device having a multilevel polarization (MLP) state generated due to adjustment of a displacement current and to a method for manufacturing the ferroelectric memory device.

Abstract: A magnetic random access memory (MRAM), and methods of manufacturing and operating the MRAM, include a switching element and a storage node connected to the switching element, and a magnetic node configured to simultaneously store two opposite bits.

Abstract: A method for fabricating a semiconductor device includes forming a magnetic tunnel junction (MTJ) element on a substrate, forming a first capping layer along the shape of the MTJ element, forming an insulating layer on the first capping layer, forming a trench exposing a portion of the first capping layer above the MTJ element by selectively etching the insulating layer, forming a second capping layer on sidewalls of the trench, removing the exposed portion of the first capping layer using the second capping layer as an etching mask to expose an upper surface of the MTJ element, and forming a conductive layer in the trench, wherein the conductive layer contacts the upper surface of the MTJ element.

Abstract: A thermoelectric conversion element includes: a magnetic body having a magnetization; and an electromotive body formed of material exhibiting a spin orbit coupling and jointed to the magnetic body. The magnetic body has an upper joint surface jointed to the electromotive body. The upper joint surface has concavities and convexities.

Abstract: A memory cell includes an elongated first electrode coupled to a magnetic tunnel junction (MTJ) structure and an elongated second electrode aligned with the elongated first electrode coupled to the MTJ structure. The elongated electrodes are configured to direct mutually additive portions of a switching current induced magnetic field through the MTJ. The mutually additive portions enhance switching of the MTJ in response to application of the switching current.

Abstract: A memory element includes a layered structure: a memory layer having a changeable magnetization direction, the magnetization direction being changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer, including a first ferromagnetic layer having a magnetization direction that is inclined from a direction perpendicular to a film face, a bonding layer laminated on the first ferromagnetic layer, and a second ferromagnetic layer laminated on the bonding layer and bonded to the first ferromagnetic layer via the bonding layer, having a magnetization direction that is inclined from the direction perpendicular to the film face, a magnetization-fixed layer having a fixed magnetization direction, an intermediate layer that is provided between the memory layer and the magnetization-fixed layer, and is contacted with the first ferromagnetic layer, and a cap layer that is contacted with the second ferromagnetic layer.

Abstract: Embodiments of the present disclosure are a method of forming a magnetic tunnel junction (MTJ) device and methods of forming a magnetic random access memory (MRAM) device. An embodiment is a method of forming a magnetic tunnel junction (MTJ) device, the method comprising forming an MTJ layer over a bottom electrode, forming a top electrode layer over the MTJ layer, and selectively etching the top electrode layer to form a top electrode over the MTJ layer. The method further comprises patterning an upper portion of the MTJ layer with an ion beam etch (IBE) process.

Abstract: A thermoelectric conversion element of the present invention includes: a magnetic layer; and an electrode layer formed on the magnetic layer. The electrode layer includes: a first region, and a second region having lower spin current—electric current conversion efficiency and resistivity than those of the first region.

Abstract: A method and system provide and program a nonvolatile logic device. The nonvolatile logic device includes input and output magnetic junctions and at least one magnetic junction between the input and output magnetic junctions. The input magnetic junction includes an input junction free layer having an input junction easy axis. The input magnetic junction may be switchable using a current driven through the magnetic junction. The output magnetic junction includes an output junction free layer having an output junction easy axis. Each of the magnetic junction(s) includes a free layer having an easy axis. The input magnetic junction is magnetically coupled to the output magnetic junction through the magnetic junction(s). In some aspects, the method includes switching the magnetic moment(s) of the input magnetic junction from a first state to a second state, applying and then removing magnetic field(s) along the hard axis of the at least one magnetic junction.

Abstract: Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO2-x), and reacts with the PZT material being deposited.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming a magnetic tunnel junction (MTJ) device, and a process tool. An embodiment is a process tool comprising an ion beam etch (IBE) chamber, an encapsulation chamber, a transfer module interconnecting the IBE chamber and the encapsulation chamber, the transfer module being capable of transferring a workpiece from the IBE chamber to the encapsulation chamber without exposing the workpiece to an external environment.

Abstract: A method for making a current-perpendicular-to-the-plane (CPP) magnetoresistive (MR) sensor that has a reference layer with low coercivity includes first depositing, within a vacuum chamber, a seed layer and an antiferromagnetic layer on a substrate without the application of heat. The substrate with deposited layers is then heated to between 200-600° C. for between 1 to 120 minutes. The substrate with deposited layers is then cooled, preferably to room temperature (i.e., below 50° C., but to at least below 100° C., in the vacuum chamber. After cooling of the antiferromagnetic layer, the ferromagnetic reference layer is deposited on the antiferromagnetic layer. Then the substrate with deposited layers is removed from the vacuum chamber and subjected to a second annealing, in the presence of a magnetic field, by heating to a temperature between 200-400° C. for between 0.5-50 hours.

Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.

Abstract: Multi-step deposition of lead-zirconium-titanate (PZT) ferroelectric material. An initial portion of the PZT material is deposited by metalorganic chemical vapor deposition (MOCVD) at a low deposition rate, for example at a temperature below about 640 deg C. from vaporized liquid precursors of lead, zirconium, and titanium, and a solvent at a collective flow rate below about 1.1 ml/min, in combination with an oxidizing gas. Following deposition of the PZT material at the low flow rate, the remainder of the PZT film is deposited at a high deposition rate, attained by changing one or more of precursor and solvent flow rate, oxygen concentration in the oxidizing gas, A/B ratio of the precursors, temperature, and the like.

Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device, a method of forming an MRAM device, and a method of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a second layer over a first layer, and performing a first etch process on the second layer to define a feature, wherein the first etch process forms a film on a surface of the feature. The method further comprises performing an ion beam etch process on the feature, wherein the ion beam etch removes the film from the surface of the feature.

Abstract: The invention provides a novel class of room-temperature, single-phase, magnetoelectric multiferroic (PbFe0.67W0.33O3)x (PbZr0.53Ti0.47O3)1-x (0.2?x?0.8) (PFWx?PZT1-x) thin films that exhibit high dielectric constants, high polarization, weak saturation magnetization, broad dielectric temperature peak, high-frequency dispersion, low dielectric loss and low leakage current. These properties render them to be suitable candidates for room-temperature multiferroic devices. Methods of preparation are also provided.

Abstract: An object of the invention is to ensure the thermal stability of magnetization even when a magnetic memory element is miniaturized. A magnetic memory element includes a first magnetic layer (22), an insulating layer (21) that is formed on the first magnetic layer (22), and a second magnetic layer (20) that is formed on the insulating layer (21). At least one of the first magnetic layer (22) and the second magnetic layer (20) is strained and deformed so as to be elongated in an easy magnetization axis direction of the magnetic layer (22) or (20) or compressive strain (101) remains in any direction in the plane of at least one of the first magnetic layer and the second magnetic layer.

Abstract: Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.

Abstract: A phase change random access memory includes a semiconductor substrate having a bottom electrode formed over the semiconductor substrate; and a phase change layer formed over the bottom electrode. The phase change layer a first phase change layer formed over the bottom electrode and including at least one of a first element, a second element, and a third element; and a second phase change layer formed over a surface of the first phase change layer and formed of the first element to prevent an area of the first phase change layer from increasing through diffusion.

Abstract: A method for manufacturing a magnetic write pole of a magnetic write head that achieves improved write pole definition reduced manufacturing cost and improves ease of photoresist mask re-work. The method includes the use of a novel bi-layer hard mask beneath a photoresist mask. The bi-layer mask includes a layer of silicon dielectric, and a layer of carbon over the layer of silicon dielectric. The carbon layer acts as an anti-reflective coating layer that is unaffected by the photolithographic patterning process used to pattern the write pole and also acts as an adhesion layer for resist patterning. In the event that the photoresist patterning is not within specs and a mask re-work must be performed, the bi-layer mask can remain intact and need not be removed and re-deposited. In addition, the low cost and ease of use silicon dielectric and carbon reduce manufacturing cost and increase throughput.

Abstract: A storage node of a magnetic memory device includes: a lower magnetic layer, a tunnel barrier layer formed on the lower magnetic layer, and a free magnetic layer formed on the tunnel barrier. The free magnetic layer has a magnetization direction that is switchable in response to a spin current. The free magnetic layer has a cap structure surrounding at least one material layer on which the free magnetic layer is formed.

Abstract: In a particular embodiment, a method of forming a magnetic tunnel junction (MTJ) device includes forming an MTJ cap layer on an MTJ structure and forming a top electrode layer coupled to the MTJ cap layer. The top electrode layer includes at least two layers and one layer of the two layers includes a nitrified metal.

Abstract: A spin-torque magnetoresistive memory element has a high magnetoresistance and low current density. A free magnetic layer is positioned between first and second spin polarizers. A first tunnel barrier is positioned between the first spin polarizer and the free magnetic layer and a second tunnel barrier is positioned between the second spin polarizer and the free magnetic layer. The magnetoresistance ratio of the second tunnel barrier has a value greater than double the magnetoresistance ratio of the first tunnel barrier.

Abstract: A STT-MRAM comprises a method to form magnetic random access memory (MRAM) element array having ultra small dimensions using double photo exposures and etch of their hard masks. The memory cells are located at the cross section of two ultra-narrow photo-resist lines suspended between two large photo-resist bases. Array of MRAM cells with small dimension is formed by a third magnetic etch.

Abstract: The performance of an MR device has been improved by inserting one or more Magneto-Resistance Enhancing Layers (MRELs) into approximately the center of one or more of the magnetic layers such as an inner pinned (AP1) layer, spin injection layer (SIL), field generation layer (FGL), and a free layer. An MREL is a layer of a low band gap, high electron mobility semiconductor such as ZnO or a semimetal such as Bi. The MREL may further comprise a first conductive layer that contacts a bottom surface of the semiconductor or semimetal layer, and a second conductive layer that contacts a top surface of the semiconductor or semimetal layer.

Abstract: Disclosed herein are a method of improving sensitivity of a terrestrial magnetism sensor and an apparatus using the same. A method of forming a terrestrial magnetism sensor includes: cleaning a surface of the terrestrial magnetism sensor; and depositing a thermoelectric material as a thin film on the cleaned surface of the terrestrial magnetism sensor. Therefore, a sensing error of the terrestrial magnetism sensor that has been generated due to heat in the prior art is decreased, thereby making it possible to allow the terrestrial magnetism sensor to calculate an accurate sensing value.

Abstract: A planar STT-MRAM comprises apparatus, a method of operating a spin-torque magnetoresistive memory and a plurality of magnetoresistive memory element having spin-transfer torques acting on a recording layer from a MTJ stack and a novel magnetoresistance with a spin-valve layer. The spin-valve layer is field-reversible between two stable magnetization states either parallel or anti-parallel to the fixed reference layer magnetization through a set/reset current pulse along a conductive line provided by a control circuitry, accordingly, the magnetoresistive element is pre-configured into a reading mode having canceled spin-transfer torques or a recording mode having additive spin-transfer torques.