Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a first magnetic layer having a variable magnetization direction. A first nonmagnetic layer is provided on the first magnetic layer. A second magnetic layer having a fixed magnetization direction is provided on the first nonmagnetic layer. The first magnetic layer, the first nonmagnetic layer and the second magnetic layer are preferredly oriented in a cubical crystal (111) plane.

Abstract: A method of fabricating a magnetic memory according to an embodiment includes: forming a separation layer on a first substrate; sequentially forming a first ferromagnetic layer, a first nonmagnetic layer, and a second ferromagnetic layer on the separation layer, at least one of the first and the second ferromagnetic layers having a single crystal structure; forming a first conductive bonding layer on the second ferromagnetic layer; forming a second conductive bonding layer on a second substrate, on which a transistor and a wiring are formed, the second conductive bonding layer electrically connecting to the transistor; arranging the first and second substrate so that the first conductive bonding layer and the second conductive bonding layer are opposed to each other, and bonding the first and the second conductive bonding layers to each other; and separating the first substrate from the first ferromagnetic layer by using the separation layer.

Abstract: A ferroelectric field-effect transistor device includes: a semiconductor layer; a ferroelectric layer; and an ion conductor layer arranged between the semiconductor layer and the ferroelectric layer and in contact with the semiconductor layer. Methods for producing the ferroelectric field-effect transistor device and using the ferroelectric field-effect transistor device in non-volatile memory devices are also disclosed.

Abstract: A thermally assisted magnetic memory cell device includes a substrate, a first electrode disposed on the substrate, a magnetic tunnel junction disposed on the first electrode, a second electrode disposed on the magnetic tunnel junction, a conductive hard mask disposed on the second electrode and a parallel shunt path coupled to the magnetic tunnel junction, thereby electrically coupling the first and second electrodes.

Abstract: Semiconductor packages including magnetic core inductor (MCI) structures for integrated voltage regulators are described. In an example, a semiconductor package includes a package substrate and a semiconductor die coupled to a first surface of the package substrate. The semiconductor die has a first plurality of metal-insulator-metal (MIM) capacitor layers thereon. The semiconductor package also includes a magnetic core inductor (MCI) die coupled to a second surface of the package substrate. The MCI die includes one or more slotted inductors and has a second plurality of MIM capacitor layers thereon.

Abstract: An integrated circuit having an indirect sensor and a direct sensor formed on a common semiconductor substrate is disclosed. The direct sensor requires the parameter being measured to be directly applied to the direct sensor. Conversely, the indirect sensor can have the parameter being measured to be indirectly applied to the indirect sensor. The parameter being measured by the direct sensor is different than the parameter being measured by the indirect sensor. In other words, the direct sensor and indirect sensor are of different types. An example of a direct sensor is a pressure sensor. The pressure being measured by the pressure sensor must be applied to the pressure sensor. An example of an indirect sensor is an accelerometer. The rate of change of velocity does not have to be applied directly to the accelerometer. In one embodiment, the direct and indirect sensors are formed using photolithographic techniques.

Abstract: A method of manufacturing magnetoresistive random access memory (MRAM) device includes foaming first and second patterns on a substrate in an alternating and repeating arrangement, forming a first capping layer on top surfaces of the first and second patterns, and removing first portions of the first capping layer and a portion of the second patterns thereunder to form first openings exposing the substrate. The method further includes forming source lines filling lower portions of the first openings, respectively, forming second capping layer patterns filling upper portions of the first openings, respectively, and removing second portions of the first capping layer and a portion of the second patterns thereunder to form second openings exposing the substrate. Then, contact plugs and pad layers are integrally formed and sequentially stacked on the substrate to fill the second openings.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements formed utilizing two etches through all epitaxially grown layers. Each of these etches can be split to two separate processes specific to CMOS transistor etch and to memory element etch. The memory array device includes a plurality of gate conductors configured along a first axis, in parallel. Each FET of the memory cells adjacent to two gate conductors. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis.

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

Abstract: A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space.

Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). The device includes a magnetic tunnel junction configured to store data, a first multilayer contact structure positioned on one end of the magnetic tunnel junction, and a second multilayer contact structure positioned on an opposite end of the magnetic tunnel junction. The first multilayer contact structure and the second multilayer contact structure each include multiple layers of metals. The multiple layers of metals are structured to inhibit thermal conductivity between the magnetic tunnel junction and surrounding structures, and the multiple layers of metals are structured to electrically conduct electrical current.

Abstract: In a method of an MRAM device, first and second patterns are formed on a substrate alternately and repeatedly in a second direction. Each first pattern and each second pattern extend in a first direction perpendicular to the second direction. Some of the second patterns are removed to form first openings extending in the first direction. Source lines filling the first openings are formed. A mask is formed on the first and second patterns and the source lines. The mask includes second openings in the first direction, each of which extends in the second direction. Portions of the second patterns exposed by the second openings are removed to form third openings. Third patterns filling the third openings are formed. The second patterns surrounded by the first and third patterns are removed to form fourth openings. Contact plugs filling the fourth openings are formed.

Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a reference layer, a nonmagnetic spacer layer and a free layer. The nonmagnetic spacer layer is between the reference layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. A portion of the magnetic junction includes at least one magnetic substructure. The magnetic substructure includes at least one Fe layer and at least one nonmagnetic insertion layer. The at least one Fe layer shares at least one interface with the at least one nonmagnetic insertion layer. Each of the at least one nonmagnetic insertion layer consists of at least one of W, I, Hf, Bi, Zn, Mo, Ag, Cd, Os and In.

Abstract: A micro-electromechanical device and method of manufacture are disclosed. A sacrificial layer is formed on a silicon substrate. A metal layer is formed on a top surface of the sacrificial layer. Soft magnetic material is electrolessly deposited on the metal layer to manufacture the micro-electromechanical device. The sacrificial layer is removed to produce a metal beam separated from the silicon substrate by a space.

Abstract: Memory devices and methods for forming the device are disclosed. The device includes a substrate having an array surface and a non-array surface and a memory array having a plurality of memory cells interconnected by first conductors in a first direction and second conductors in a second direction. The memory array is disposed on the array surface of the substrate. The device further includes through silicon via (TSV) contacts disposed in the substrate. The TSV contacts extend from the array surface to the non-array surface, enabling electrical connections to the array from the non-array surface.

Abstract: A vertical Hall Effect element includes one or more of: a low voltage P-well region disposed at a position between pickups of the vertical Hall Effect element, Light-N regions disposed under the pickups, a pre-epi implant region, or two epi regions to result in an improved sensitivity of the vertical Hall Effect element. A method results in the vertical Hall Effect element having the improved sensitivity.

Abstract: The present disclosure provides one embodiment of a semiconductor structure that includes a first metal layer formed on a semiconductor substrate, wherein the first metal layer includes a first metal feature in a first region and a second metal feature in a second region; a second metal layer disposed on the first metal layer, wherein the second metal layer includes a third metal feature in the first region and a fourth metal feature in a second region; a magneto-resistive memory device sandwiched between the first metal feature and the third metal feature; and a capacitor sandwiched between the second metal feature and the fourth metal feature.

Abstract: A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors. For example, a two turn inductor and a three turn inductor may share masks for interconnects and coils, while only masks necessary for connections between the interconnects and coils may need to be newly developed.

Abstract: A TMR (tunneling magnetoresistive) read sensor is formed in which a portion of the sensor stack containing the ferromagnetic free layer and the tunneling barrier layer is patterned to define a narrow trackwidth, but a synthetic antiferromagnetic pinning/pinned layer is left substantially unpatterned and extends in substantially as-deposited form beyond the lateral edges bounding the patterned portion. The narrow trackwidth of the patterned portion permits high resolution for densely recorded data. The larger pinning/pinned layer significantly improves magnetic stability and reduces thermal noise, while the method of formation eliminates possible ion beam etch (IBE) or reactive ion etch (RIE) damage to the edges of the pinning/pinned layer.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory elements formed utilizing two etches through all epitaxially grown layers. Each of these etches can be split to two separate processes specific to CMOS transistor etch and to memory element etch. The memory array device includes a plurality of gate conductors configured along a first axis, in parallel. Each FET of the memory cells adjacent to two gate conductors. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis.

Abstract: Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one magnetic region (e.g., a free region or a fixed region) configured to exhibit a vertical magnetic orientation, at least one oxide-based region, which may be a tunnel junction region or an oxide capping region, and at least one magnetic interface region, which may comprise or consist of iron (Fe). In some embodiments, the magnetic interface region is spaced from at least one oxide-based region by a magnetic region. The presence of the magnetic interface region enhances the perpendicular magnetic anisotropy (PMA) strength of the magnetic cell core. In some embodiments, the PMA strength may be enhanced more than 50% compared to that of the same magnetic cell core structure lacking the magnetic interface region.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array device includes a plurality of gate conductors configured a first axis, in parallel. Each gate conductor laterally surrounds a plurality of FETs of the memory cells along the first axis. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. Embodiments of the memory array preserve alignment of crystal lattices beginning from the bottom layers in the FET up to the top active layers in memory element, thus preserving crystal lattice alignment between transistor and memory element.

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.

Abstract: A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap.

Abstract: A method of forming a magnetic tunnel junction device is disclosed that includes forming a trench in a substrate, the trench including a plurality of sidewalls and a bottom wall. The method includes depositing a first conductive material within the trench proximate to one of the sidewalls and depositing a second conductive material within the trench. The method further includes depositing a material to form a magnetic tunnel junction (MTJ) structure within the trench. The MTJ structure includes a fixed magnetic layer having a magnetic field with a fixed magnetic orientation, a tunnel junction layer, and a free magnetic layer having a magnetic field with a configurable magnetic orientation. The method further includes selectively removing a portion of the MTJ structure to create an opening in the MTJ structure.

Abstract: In one aspect, a method includes processing a metal substrate, performing a first etch on a first surface of the metal substrate to form, for an integrated circuit package, secondary leads and a curved component having two primary leads and performing a second etch, on a second surface of the substrate opposite the first surface, at locations on the secondary leads and locations on the curved component to provide a locking mechanism. Each primary lead located at a respective end of the curved component.

Abstract: Magnetic field sensor designs that provide both increased directionality and proximate coupling desirable for improved directionality and sensitivity and methods for fabricating them.

Abstract: A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap.

Abstract: A thermally assisted magnetic memory cell device includes a substrate, a first electrode disposed on the substrate, a magnetic tunnel junction disposed on the first electrode, a second electrode disposed on the magnetic tunnel junction, a conductive hard mask disposed on the second electrode and a parallel shunt path coupled to the magnetic tunnel junction, thereby electrically coupling the first and second electrodes.

Abstract: A system and method for fabricating a memory array device. An example memory array device includes a plurality of memory cells, each including a FET over a substrate and a memory element over the FET. Each memory element includes a plurality of epitaxially grown memory element layers. The memory array device includes a plurality of gate conductors configured a first axis, in parallel. Each gate conductor laterally surrounds a plurality of FETs of the memory cells along the first axis. The memory array device includes a plurality of bit lines configured along a second axis, in parallel, and electrically coupled to a plurality of memory elements along the second axis. Embodiments of the memory array preserve alignment of crystal lattices beginning from the bottom layers in the FET up to the top active layers in memory element, thus preserving crystal lattice alignment between transistor and memory element.

Abstract: Embodiments are directed to providing a spin hall effect (SHE) assisted spin transfer torque magnetic random access memory (STT-MRAM) device by coupling a magnetic tunnel junction (MTJ) to a SHE material, and coupling the SHE material to a transistor. Embodiments are directed to a spin transfer torque magnetic random access memory (STT-MRAM) device comprising: a magnetic tunnel junction (MTJ) coupled to a spin hall effect (SHE) material, and a transistor coupled to the SHE material.

Abstract: A method for manufacturing a semiconductor apparatus includes forming a semiconductor device on a principal surface of a substrate, in which the semiconductor device includes an interconnect layer, forming a buffer film which covers the semiconductor device and prevents diffusion of a magnetic material, and forming a magnetic shielding film which covers the buffer film and includes the magnetic material.

Abstract: A magnetic device includes a first electrode portion, a free layer portion arranged on the first electrode portion, the free layer portion including a magnetic insulating material, a reference layer portion contacting the free layer portion, the reference layer portion including a magnetic metallic layer, and a second electrode portion arranged on the reference layer portion.

Abstract: A donor film 40 including an organic donor layer 42 and a transfer target substrate 12 including a lower electrode 7 are prepared. The organic donor layer 42 is thermally transferred to the top of the lower electrode 7 of the transfer target substrate 12 to form an organic layer 17 by placing the donor film 40 between the transfer target substrate 12 and a thermal head 38 and bringing the transfer target substrate 12 and the thermal head 38 into close contact with each other by magnetic attraction of a magnetic body 4, and then an upper electrode is formed on the organic layer 17, to obtain an organic EL element. This provides an organic EL element with excellent quality free from unevenness in the transfer of the organic donor layer from the donor film even when the transfer target substrate is large in size.

Abstract: The present disclosure provides a spin device including: a graphene; a first ferromagnetic electrode and a second electrode that are in electrical contact with and sandwich the graphene; a third ferromagnetic electrode and a fourth electrode that sandwich the graphene at a position apart from the first and second electrodes in electrical contact with the graphene; a current applying portion that applies an electric current between the first ferromagnetic electrode and the second electrode; and a voltage-signal detecting portion that detects spin accumulation information as a voltage signal via the third ferromagnetic electrode and the fourth electrode. The spin accumulation information is generated, by application of the electric current, in a part of the graphene that is sandwiched between the third and fourth electrodes. The first and third ferromagnetic electrodes are disposed on the same surface of the graphene, and the second and fourth electrodes are non-magnetic or ferromagnetic electrodes.

Abstract: A method for manufacturing a semiconductor device includes forming a mask film on a partial region of a semiconductor substrate; forming a mask member above the semiconductor substrate in both the region where the mask film is formed and a region where the mask film is not formed; patterning the mask film and an upper portion of the semiconductor substrate by performing etching using the mask member as a mask. The method further includes removing part of the patterned upper portion of the semiconductor substrate by performing etching using the patterned mask film as a mask.

Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.

Abstract: Magnetoresistive elements, and memory devices including the same, include a pinned layer having a fixed magnetization direction, a free layer corresponding to the pinned layer, and a protruding element protruding from the free layer and having a changeable magnetization direction. The free layer has a changeable magnetization direction. The protruding element is shaped in the form of a tube. The protruding element includes a first protruding portion and a second protruding portion protruding from ends of the free layer facing in different directions.

Abstract: A manufacturing method to form a memory device includes forming a hard mask on a magnetic stack. A first magnetic stack etch is performed to form exposed magnetic layers. A liner is applied to the exposed magnetic layers to form protected magnetic layers. A second magnetic stack etch forms a magnetic random access memory (MRAM) cell, where the liner prevents shunting between the protected magnetic layers.

Abstract: Methods for testing magnetoresistance of test devices with layer stacks, such as MTJs, fabricated on a wafer are described. The test devices can be fabricated along with arrays of similarly structured memory cells on a production wafer to allow in-process testing. The test devices with contact pads at opposite ends of the bottom electrode allow resistance across the bottom electrode to be measured as a surrogate for measuring resistance between the top and bottom electrodes. An MTJ test device according to the invention has a measurable magnetoresistance (MR) between the two contact pads that is a function of the magnetic orientation of the free layer and varies with the length and width of the MTJ strip in each test device. The set of test MTJs can include a selected range of lengths to allow the tunnel magnetoresistance (TMR) and resistance area product (RA) to be estimated or predicted.

Abstract: Provided are a magnetic sensor and a method of fabricating the same. The magnetic sensor includes: hall elements disposed in a substrate, a protection layer disposed on the substrate, a seed layer disposed on the protection layer, and an integrated magnetic concentrator (IMC) formed on the seed layer, the seed layer and the IMC each having an uneven surface.

Abstract: A method for fabricating a magnetic film structure is provided. The method comprises forming a magnetic structure on a bottom electrode layer, the magnetic structure comprising at least one pinned bottom magnetic film layer having a fixed magnetic orientation; at least one top magnetic film layer whose magnetic orientation can be manipulated by a current; and a tunneling layer between the bottom magnetic film layer and the top magnetic film layer; forming a metallic hard mask atop the magnetic structure; patterning and etching the metallic hard mask to define exposed areas of the magnetic structure; selectively etching the exposed areas of the magnetic structure by a chemical etch process based on a CO etch chemistry to form discrete magnetic bits.

Abstract: A communications structure comprises a first semiconductor substrate having a first coil, and a second semiconductor substrate having a second coil above the first semiconductor substrate. Inner edges of the first and second coils define a boundary of a volume that extends below the first coil and above the second coil. A ferromagnetic core is positioned at least partially within the boundary, such that a mutual inductance is provided between the first and second coils for wireless transmission of signals or power between the first and second coils.

Abstract: A spin-transfer-torque magnetoresistive memory comprises apparatus and method of manufacturing a three terminal magnetoresistive memory element having highly conductive bottom electrodes overlaid on top of a SHE-metal layer in the regions outside of an MTJ stack. The memory cell comprises a bit line positioned adjacent to selected ones of the plurality of magnetoresistive memory elements to supply a reading current across the magnetoresistive element stack and two highly conductive bottom electrodes overlaid and electrically contacting on top of a SHE-metal layer in the outside of an MTJ region and to supply a bi-directional spin Hall effect recording current, and accordingly to switch the magnetization of the recording layer. Thus magnetization of a recording layer can be readily switched or reversed to the direction in accordance with a direction of a current along the SHE-metal layer by applying a low write current.

Abstract: Methods and apparatus for MEMS release are disclosed. A method is described including providing a substrate including at least one MEMS device supported by a sacrificial layer; performing an etch in solution to remove the sacrificial layer from at least one MEMS device; immersing the substrate including the at least one MEMS device in an organic solvent; and while the substrate is immersed in the organic solvent, removing water from the organic solvent until the water remaining in the organic solvent is less than a predetermined threshold. An apparatus is disclosed for performing the methods. Additional alternative methods are disclosed.

Abstract: A wrap around shield structure is disclosed for biasing a free layer in a sensor and includes a bottom shield, side shields, and top shield in which each shield element comprises a high moment layer with a magnetization saturation greater than that of Ni70Fe30. The high moment layers provide a better micro read width performance. Side shield structure includes a stack of antiferromagnetically (AFM) coupled magnetic layers on a second high moment layer. A first (lower) magnetic layer in each side shield is ferromagnetically coupled to the second high moment layer, and to a first high moment layer in the bottom shield. A third (upper) magnetic layer in each side shield is ferromagnetically coupled to a third high moment layer in the top shield for improved stabilization. Sensor sidewalls may terminate at a top surface of a reference layer to decrease reader shield spacing.

Abstract: A composite side shield structure is disclosed for providing biasing to a free layer in a sensor structure. The sensor is formed between a bottom shield and top shield each having a magnetization in a first direction that is parallel to an ABS. The side shield is stabilized by an antiferromagnetic (AFM) coupling scheme wherein a bottom (first) magnetic layer is AFM coupled to a second magnetic layer which in turn is AFM coupled to an uppermost (third) magnetic layer. First and third magnetic layers each have a magnetization aligned in the first direction and are coupled to bottom and top shields, respectively, for additional stabilization. The top shield may be modified to include an AFM scheme for providing additional stabilization and guidance to magnetic moments within AFM coupled magnetic layers in the top shield, and to the third magnetic layer in the side shield.

Abstract: A Magnetoresistive Tunnel Junction (MTJ) device includes an elongated MTJ structure formed onto a substrate, the MTJ structure including a magnetic reference layer and a tunnel barrier layer. The MTJ device also includes a number of discrete free magnetic regions disposed onto the tunnel barrier layer. The ratio of length to width of the elongated MTJ structure is such that the magnetic field of the magnetic reference layer is pinned in a single direction.

Abstract: A magnetic electronic device comprises a substrate, a buffer layer, a first CoFeB layer, a first metal oxidation layer and a capping layer. The buffer layer is disposed above the substrate. The first CoFeB layer is disposed above the buffer layer. The first metal oxidation layer is disposed above the first CoFeB layer. The capping layer is disposed above the first metal oxidation layer and covers the first metal oxidation layer. A manufacturing method of the magnetic electronic device is also disclosed.

Abstract: A method for fabricating a nonvolatile memory device is provided. The method includes forming a transistor including an impurity region formed in a substrate, forming a first interlayer insulation layer covering the transistor, the first interlayer insulation layer including a protrusion overlapping the impurity region, and forming an information storage unit on the protrusion, the information storage unit exposing side surfaces of the protrusion using point cusp magnetron-physical vapor deposition (PCM-PVD) and electrically connected to the impurity region.