Repair Or Restoration Patents (Class 438/4)
  • Patent number: 10991571
    Abstract: Atomic layer deposition (ALD) process formation of silicon oxide with temperature>500° C. is disclosed.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: April 27, 2021
    Assignee: Versum Materials US, LLC
    Inventors: Haripin Chandra, Meiliang Wang, Manchao Xiao, Xinjian Lei, Ronald Martin Pearlstein, Mark Leonard O'Neill
  • Patent number: 10930508
    Abstract: Disclosed are methods of forming devices. One method may include providing a first set of fins and a second set of fins extending from a substrate, and providing a dummy oxide over the first set of fins and the second set of fins. The method may further include performing a thermal implant to the second set of fins, wherein the thermal implant is an angled ion implant impacting the dummy oxide. The method may further include removing the dummy oxide from the first set of fins and the second set of fins, and forming a first work function (WF) metal over the first set of fins and a second WF metal over the second set of fins.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: February 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Qintao Zhang, Kyu-Ha Shim
  • Patent number: 10930201
    Abstract: Methods and systems for testing a display having an array of microdrivers arranged in multiple of rows and columns including setting a testing mode of a microdriver of the array of microdrivers using multiple pins of the microdriver that are used in scanning or operation modes of the microdriver. The microdriver is configured to light one or more connected micro light emitting diode pixels coupled to the microdriver during the testing mode. Testing also includes operating the microdriver in the testing mode and determining functionality of the one or more connected micro light emitting diode pixels or the microdriver based on the testing mode.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 23, 2021
    Assignee: Apple Inc.
    Inventors: Mahdi Farrokh Baroughi, Bo Yang, Xiang Lu, Hopil Bae
  • Patent number: 10867875
    Abstract: A pixel structure includes a substrate, an active device layer, a first insulating layer disposed on the active device layer, a first light emitting element and a second light emitting element disposed on the first insulating layer, a plurality of first signal lines disposed on the first insulating layer, and a plurality of second signal lines. The first signal lines are electrically connected to the active device layer, and the first signal lines are electrically insulated from the first light emitting element. The second signal lines are electrically connected to the first signal lines and the second light emitting element. The second light emitting element overlaps with a portion of the first light emitting element in a first direction. Electrodes of the first light emitting element and electrodes of the second light emitting element are disposed facing the first direction. A repairing method of the pixel structure is also provided.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 15, 2020
    Assignee: Au Optronics Corporation
    Inventor: Ze-Yu Yen
  • Patent number: 10847324
    Abstract: The present invention relates to a method which can effectively remove perovskite light absorbers, hole transport layers, metal electrodes, and the like by immersing a waste perovskite-based photoelectric conversion element module in a cleaning solution under predetermined conditions. The present invention can recover a substrate from the waste module and manufacture a photoelectric conversion element having a photoelectric conversion efficiency level comparable to the initially high level again, using the same.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: November 24, 2020
    Assignees: GLOBAL FRONTIER CENTER FOR MULTISCALE ENERGY, RESEARCH & BUSINESS FOUNDATION SUNGYUNKWAN
    Inventors: Hyun Suk Jung, Byeong Jo Kim, Dong Hoe Kim, Seung Lee Kwon, Dong Geon Lee, Young Un Jin, So Yeon Park
  • Patent number: 10847624
    Abstract: Methods and apparatus to form GaN-based transistors during back-end-of-line processing are disclosed. An example integrated circuit includes a first transistor formed on a first semiconductor substrate. The example integrated circuit includes a dielectric material formed on the first semiconductor substrate. The dielectric material extends over the first transistor. The example integrated circuit further includes a second semiconductor substrate formed on the dielectric material. The example integrated circuit also includes a second transistor formed on the second semiconductor substrate.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then
  • Patent number: 10692744
    Abstract: In one embodiment, a vaporizer is connected to a chamber of a substrate processing apparatus through a gas supply line and a gas introduction port. An exhaust device is connected to the gas supply line. The substrate processing apparatus includes a pressure sensor that obtains a measurement value of a pressure of the gas supply line. A method according to the embodiment includes supplying a processing gas to the chamber from the vaporizer through the gas supply line, and monitoring a change of the measurement value obtained by the pressure sensor in a state in which supply of the processing gas to the gas supply line is stopped.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 23, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Risako Miyoshi
  • Patent number: 10573538
    Abstract: Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The the at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Bing Dang, Jeffrey Donald Gelorme, Li-Wen Hung, John U. Knickerbocker, Cornelia Tsang Yang
  • Patent number: 10325785
    Abstract: Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Bing Dang, Jeffrey Donald Gelorme, Li-Wen Hung, John U. Knickerbocker, Cornelia Tsang Yang
  • Patent number: 10224219
    Abstract: Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Bing Dang, Jeffrey Donald Gelorme, Li-Wen Hung, John U. Knickerbocker, Cornelia Tsang Yang
  • Patent number: 10112305
    Abstract: A failure diagnosis device for a mechanical device provided with a motor as a source to drive a motion axis, and configured to acquire a moving position of the motion axis and a disturbance torque value applied to the motion axis every predetermined period, and to diagnose that a failure is occurring when the disturbance torque value is larger than a failure determination threshold, includes a maintenance effect determination unit configured to calculate a change in the disturbance torque value before and after conducting of a maintenance task when the maintenance task is conducted on the motion axis, and a failure diagnosis unit configured to re-set the failure determination threshold only when the change in the disturbance torque value is larger than a predetermined threshold.
    Type: Grant
    Filed: May 25, 2015
    Date of Patent: October 30, 2018
    Assignee: NISSAN MOTOR CO., LTD.
    Inventor: Masaki Kuno
  • Patent number: 10103284
    Abstract: Apparatus for the industrial production of photovoltaic concentrator modules, consisting of a module frame, a lens disc, a sensor carrier disc and an electrical line routing arrangement, comprising the following features: a) a mount for the stress-free mounting of a module frame by means of clamping elements on both longitudinal sides and stop elements on both transverse sides, wherein the setting of the clamping elements takes place by means of the displacement and rotation of a switching rod, b) a device for a punctiform application of acrylic and a linear application of silicone onto the bearing surfaces of the module frame, c) a respective device for placing the sensor carrier disc or the lens disc, wherein these discs are transported in a stress-free fashion by means of special suction apparatuses and are emplaced with a centrally starting, predetermined contact pressure, d) a device for measuring the respective disc position and for positioning a sensor carrier disc or a lens disc, e) a device for the f
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: October 16, 2018
    Assignee: Saint-Augustin Canada Electric Inc.
    Inventors: Gerrit Lange, Karl Friedrich Haarburger, Eckart Gerster
  • Patent number: 10049886
    Abstract: A method embodiment for forming a semiconductor device includes providing a dielectric layer having a damaged surface and repairing the damaged surface of the dielectric layer. Repairing the damaged surface includes exposing the damaged surface of the dielectric layer to a precursor chemical, activating the precursor chemical using light energy, and filtering out a spectrum of the light energy while activating the precursor chemical.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hung Lin, Sheng-Shin Lin, Ying-Chieh Hung, Yu-Ting Huang, Tze-Liang Lee
  • Patent number: 10005991
    Abstract: The present disclosure relates to a method for removing a hard mask consisting essentially of TiN, TaN, TiNxOy, TiW, W, Ti and alloys of Ti and W from a semiconductor substrate. The method comprising contacting the semiconductor substrate with a removal composition. The removal composition comprises 0.1 wt % to 90 wt % of an oxidizing agent; 0.0001 wt % to 50 wt % of a carboxylate; and the balance up to 100 wt % of the removal composition comprising deionized water.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: June 26, 2018
    Assignees: EKC TECHNOLOGY INC, E I DU PONT DE NEMOURS AND COMPANY
    Inventor: Hua Cui
  • Patent number: 9935236
    Abstract: An optoelectronic light emission device is provided that includes a gain region of at least one type III-V semiconductor layer that is present on a lattice mismatched semiconductor substrate. The gain region of the type III-V semiconductor layer has a nanoscale area using nano-cavities. The optoelectronic light emission device is free of defects.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: April 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Ning Li, Tak H. Ning, Jean-Oliver Plouchart, Devendra K. Sadana
  • Patent number: 9876060
    Abstract: A bank repair method in a manufacturing process of an organic EL display device including first and second banks forming a matrix over a substrate. When a defect portion of a first bank is detected, in each of adjacent concave spaces between which the first bank having the defect portion is located, a candidate forming position is set and a dam portion partitioning the concave space into a first space in a vicinity of the defect portion and a second space outside the vicinity of the defect portion is formed. When denoting sub-pixel region surface area as H and denoting a surface area of a region of a candidate first space overlapping with a sub-pixel region as I, the dam portion is formed at the candidate forming position according to a first forming method when I<?×H is fulfilled, where 0.05<?<0.9.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: January 23, 2018
    Assignees: JOLED INC., JAPAN DISPLAY INC.
    Inventor: Toshiaki Onimaru
  • Patent number: 9818809
    Abstract: An examination is performed of whether or not a bank having a defect portion is present. When a bank having a defect portion is present, the bank having the defect portion is repaired by forming a dam in each of adjacent concave spaces between which the bank having the defect portion is located. A dam formed in a concave space partitions the concave space into a first space in a vicinity of the defect portion and a second space outside the vicinity of the defect portion. The dam, at a portion thereof with lowest height, satisfies (h/H)+0.1W?1.5, 0.5?(h/H)?2.0, and 5?W?50, where a ratio of the height h of the dam to a height H of the banks is denoted as h/H, and a width of the dam is denoted as W ?m.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: November 14, 2017
    Assignee: JOLED INC.
    Inventors: Kazuhiro Kobayashi, Toshiaki Onimaru, Yoshiki Hayashida, Takayuki Shimamura
  • Patent number: 9691143
    Abstract: A first output value evaluation device obtains an average value of output values of optical image data for each of unit regions and creates a distribution map of an average value in an inspected region. A first defect history management device creates a distribution map related with the shape of the pattern from the distribution map of the average value and holds the created distribution map. A second output value evaluation device obtains at least one of a variation value and deviation of the output value of each pixel in the unit region. A defect determination device compares the obtained value with a threshold value. A second defect history management device holds information of the output value determined as a defect in the defect determination device. A defect/defect history analysis device analyzes, and checks the information from the first defect history management device and the second defect history management device.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: June 27, 2017
    Assignee: NUFLARE TECHNOLOGY, INC.
    Inventors: Hiromu Inoue, Nobutaka Kikuiri
  • Patent number: 9634087
    Abstract: A method is provided for fabricating a FinFET. The method includes providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate, wherein a position of the hard mask layer may corresponds to a position of subsequently formed fin; forming a doping region in the semiconductor substrate by using the hard mask layer as a mask to perform an anti-punch-through ion implantation process; forming an anti-punch-through region by performing an annealing process onto the doping region, such that impurity ions in the doping region diffuse into the semiconductor substrate under the hard mask layer; and forming a trench by using the hard mask layer as a mask to etch the semiconductor substrate and the doping region, wherein the semiconductor substrates between the adjacent trenches constitutes a fin.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: April 25, 2017
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Xinyun Xie
  • Patent number: 9634189
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: April 25, 2017
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Patent number: 9406615
    Abstract: Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer may be reduced temporarily by stuffing its pores with a sacrificial pore-stuffing material, such as titanium nitride (TiN), titanium dioxide (TiO2), or other suitable sacrificial material having a high etch selectivity compared to the metallization and dielectric material of the interconnect. After interconnect formation within the stuffed dielectric layer, the sacrificial pore-stuffing material can be removed from the pores of the host dielectric. In some cases, removal and curing can be performed with minimal or otherwise negligible effect on the dielectric constant (?-value), leakage performance, and/or time-dependent dielectric breakdown (TDDB) properties of the host dielectric layer.
    Type: Grant
    Filed: December 24, 2013
    Date of Patent: August 2, 2016
    Assignee: INTEL CORPORATION
    Inventors: Christopher J. Jezewski, David J. Michalak, Kanwal Jit Singh, Alan M. Myers
  • Patent number: 9337378
    Abstract: A system and method for applying an electrical bias to a photovoltaic device in a temperature control chamber, in which the temperature of the photovoltaic device is controlled according to a temperature profile. The temperature profile may include at least one hot phase and at least one cool phase.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: May 10, 2016
    Assignee: First Solar, Inc.
    Inventors: Scott Edmonson, Yacov Elgar, Dhruv Gajaria, Weston Gerwin, Scott Jacoby, Imran Khan, Anthony Maher, Stephen P. Murphy, Gregory A. Ritz
  • Patent number: 9330900
    Abstract: Embodiments of the present invention generally relate to methods of forming carbon-doped oxide films. The methods generally include generating hydroxyl groups on a surface of the substrate using a plasma, and then performing silylation on the surface of the substrate. The hydroxyl groups on the surface of the substrate are then regenerated using a plasma in order to perform an additional silylation. Multiple plasma treatments and silylations may be performed to deposit a layer having a desired thickness.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: May 3, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Kelvin Chan
  • Patent number: 9324560
    Abstract: A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: April 26, 2016
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Rakesh Jain, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Patent number: 9290391
    Abstract: A silicon component in a processing chamber for performing an etching process on a substrate is provided. The silicon component contains recycled silicon obtained by a silicon component recycling method including: collecting silicon wastes from any one of a silicon component for a plasma etching apparatus and a silicon ingot for a semiconductor wafer; obtaining a content of impurity based on an electric characteristic of the collected silicon wastes; determining an input amount of the silicon wastes, an input amount of a silicon source material, and an input amount of impurity based on the content of impurity obtained in the measurement process and a target value of an electric characteristic of a final product; manufacturing a silicon ingot by inputting the silicon wastes, the silicon source material, and the impurity into a crucible; and manufacturing the final product using the silicon ingot.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: March 22, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Kosuke Imafuku
  • Patent number: 9136108
    Abstract: A method for restoring a porous surface of a dielectric layer formed on a substrate, includes: (i) providing in a reaction space a substrate on which a dielectric layer having a porous surface with terminal hydroxyl groups is formed as an outer layer; (ii) supplying gas of a Si—N compound containing a Si—N bond to the reaction space to chemisorb the Si—N compound onto the surface with the terminal hydroxyl groups; (iii) irradiating the Si—N compound-chemisorbed surface with a pulse of UV light in an oxidizing atmosphere to oxidize the surface and provide terminal hydroxyl groups to the surface; and (iv) repeating steps (ii) through (iii) to form a film on the porous surface of the dielectric layer for restoration.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: September 15, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Kiyohiro Matsushita, Hirofumi Arai
  • Patent number: 9050623
    Abstract: Porous ULK film is cured with UV radiation at progressively shorter wavelengths to obtain ULK films quickly at a desired dielectric constant with improved mechanical properties. At longer wavelengths above about 220 nm or about 240 nm, porogen is removed while minimizing silicon-carbon bond formation. At shorter wavelengths, mechanical properties are improved while dielectric constant increases.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: June 9, 2015
    Assignee: Novellus Systems, Inc.
    Inventor: Bhadri N. Varadarajan
  • Publication number: 20150146122
    Abstract: A trace structure is proposed. The trace structure includes a substrate, a shorting bar on the substrate and a plurality of data lines or scan lines, whose one end is connected to the shorting bar, on the substrate. The trace structure also includes an excessive shorting bar on the substrate. A break on a data line or a scan line is repaired by connecting the broken data line or scan line with one of the excessive shorting bar or the rest of the shorting bars. The present invention also proposes a repair method and a LCD panel using the trace structure. The simple trace structure and easy break repair operation not only raises repair efficiency but also lessens repair time and saves cost.
    Type: Application
    Filed: December 13, 2013
    Publication date: May 28, 2015
    Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd.
    Inventor: Xiangyang Xu
  • Publication number: 20150144904
    Abstract: An organic electroluminescent device includes a substrate including a plurality of pixel regions each having a light emission region and an element region; a plurality of thin film transistors (TFTs) including at least one switching TFT and at least one driving TFT in each element region; a planarization layer on the plurality of TFTs; a first electrode on the planarization layer and including first to third portions connected to one another, wherein the first and second portions are at each pixel region, and the third portion is at a neighboring pixel region; an organic light emitting layer on the first electrode; and a second electrode on the organic light emitting layer, wherein an end of the third portion overlaps the driving TFT of the neighboring pixel region.
    Type: Application
    Filed: August 19, 2014
    Publication date: May 28, 2015
    Inventors: Jae-Hun JEONG, Ki-Sul CHO
  • Publication number: 20150137128
    Abstract: The present disclosure disclosed a thin-film transistor array substrate and a method for repairing the same. The array substrate comprises: a substrate; a plurality of common lines, configured on the substrate; a plurality of scan lines and data lines, arranged on the substrate with each scan line and data line perpendicular to each other, to form a plurality of pixel areas; a plurality of pixel elements including a main pixel electrode, a sub pixel electrode, and a charge sharing unit including a charge capacitor which provides a voltage difference between the main pixel electrode and the sub pixel electrode. When the charge capacitor is defective, an upper electrode or a lower electrode of the defective capacitor is disconnected from a circuit connected thereto. The method enables the repairing process faster and simpler, which is different from the traditional repairing means. The pixel element repaired can still work normally.
    Type: Application
    Filed: January 17, 2014
    Publication date: May 21, 2015
    Inventors: Zhiguang Yi, Tsung Lung Chang
  • Publication number: 20150137129
    Abstract: A thin film transistor (TFT) substrate includes; a substrate; a plurality of scan lines, disposed on the substrate; a plurality of data lines, disposed across the scan lines; a scan line insulting layer disposed between the scan lines and the data lines; a plurality of thin film transistors, each of thin film transistors disposed on an intersection of each scan line and each data, line; a data line insulting layer, disposed on a top surface of the scan line insulting layer and used to cover the data lines; and a common electrode, disposed on the data line insulting a layer, and comprising a plurality of positioning through holes, wherein the positioning through holes expose the data line insulting layer, and are located right above the data lines.
    Type: Application
    Filed: December 27, 2013
    Publication date: May 21, 2015
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventor: Han-Tung HSU
  • Patent number: 9034663
    Abstract: The invention relates to a sealed thin-film device (10, 12, 14), to a method of repairing a sealing layer (20) applied to a thin-film device (30) to produce the sealed thin-film device, to a system (200) for repairing the sealing layer applied to the thin-film device to generate the sealed thin-film device and to a computer program product. The sealed thin-film device comprises a thin-film device and a sealing layer applied on the thin-film device for protecting the thin-film device from environmental influence. The sealed thin-film device further comprises locally applied mending material (40; 42, 44) for sealing a local breach (50) in the sealing layer. An effect of this sealed thin-film device is that the operational life-time of the sealed thin-film device is improved. Furthermore, the production yield of the production of sealed thin-film devices is improved.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: May 19, 2015
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Coen A. Verschuren, Herbert Lifka, Rifat A. M. Hikmet
  • Patent number: 9034664
    Abstract: A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Griselda Bonilla, Junjing Bao, Samuel S. Choi, Ronald G. Filippi, Naftali E. Lustig, Andrew H. Simon
  • Publication number: 20150132862
    Abstract: Methods and structures for restoring an electrical parameter of a field-effect transistor in an integrated circuit deployed in an end product. A source, a drain, and a gate electrode of a field-effect transistor are coupled with ground. A restoration voltage is applied to a well beneath the field-effect transistor while the source, the drain, and the gate electrode of the field-effect transistor are coupled with ground. The well may be coupled with either a positive supply voltage or ground when a switch is in a first position during normal operation of the integrated circuit and with the restoration voltage when the switch is in a second position during a relaxation operation.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Applicant: International Business Machines Corporation
    Inventors: Terence B. Hook, Melanie J. Sherony, Christopher M. Schnabel
  • Patent number: 9029238
    Abstract: A method for processing a semiconductor wafer includes applying a release layer to a transparent handler. An adhesive layer, that is distinct from the release layer, is applied between a semiconductor wafer and the transparent handler having the release layer applied thereon. The semiconductor wafer is bonded to the transparent handler using the adhesive layer. The semiconductor wafer is processed while it is bonded to the transparent handler. The release layer is ablated by irradiating the release layer through the transparent handler with a laser. The semiconductor wafer is removed from the transparent handler.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: May 12, 2015
    Assignee: International Business Machines Corporation
    Inventors: Paul S. Andry, Russell A. Budd, John U. Knickerbocker, Robert E. Trzcinski, Douglas C. La Tulipe, Jr.
  • Patent number: 9029171
    Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee, Tien-I Bao
  • Patent number: 9023663
    Abstract: The object of the present invention is to provide a method for preparing a nano-sheet array structure of a Group V-VI semiconductor, comprising: (A) providing an electrolyte containing a hydrogen ion and disposing an auxiliary electrode and a working electrode in the electrolyte, wherein the working electrode comprises a Group V-VI semiconductor bulk; and (B) applying a redox reaction bias to the auxiliary electrode and the working electrode to form a nano-sheet array structure on the bulk.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: May 5, 2015
    Assignee: National Tsing Hua University
    Inventors: Yu-Lun Chueh, Hung-Wei Tsai, Tsung-Cheng Chan
  • Publication number: 20150115329
    Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes a first plurality of circuit elements where a first portion of the first plurality of circuit elements has defects. The second layer includes a second plurality of circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second plurality of circuit elements for mitigating the defects.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Lin, Jung-Rung Jiang, Chin-Her Chien, Ji-Jan Chen, Wei-Pin Changchien
  • Patent number: 9018020
    Abstract: Provided are methods and systems for treating shunts on solar cell substrates. Also provided are solar cells including such substrates. A shunt detected on a substrate proximate to a metallized grid pattern is electrically disconnected from at least the bus portion of the grid, which reduces shunt's impact on performance on the solar cell. An antireflective layer may be disposed between the shunt and a portion of the grid extending over the shunt. The exposure pattern of a photoresist used to form the antireflective layer may be adjusted accordingly to achieve this result. In some embodiments, the metallized grid may be modified by adjusting the exposure pattern of a photoresist used to form this grid. The grid may be modified to avoid any contact between the grid and the shunt or to disconnect a portion of the grid contacting the shunt from the bus portion area of the grid.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: April 28, 2015
    Assignee: The Boeing Company
    Inventors: Philip Chiu, Shoghig Mesropian, Dimitri D. Krut
  • Patent number: 9018632
    Abstract: A TFT substrate is provided in which a wire defect can be easily solved. A method of solving a wire defect in the TFT substrate is also provided. In an embodiment, the TFT substrate is configured so that (i) a plurality of gate lines and a plurality of source lines are arranged in a matrix manner, (ii) a TFT is provided in at least one of intersection regions where the plurality of gate lines and the plurality of source lines intersect with each other, and (iii) the at least one of intersection regions is divided by a slit, which is formed in a corresponding one of the plurality of gate lines, so that the at least intersection region is divided into parts arranged along a longitudinal direction of the plurality of source lines.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: April 28, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Makoto Shiomi
  • Publication number: 20150108480
    Abstract: An array substrate, a repairing method thereof and a display device, wherein the array substrate includes: a plurality of gate lines and a plurality of data lines provided in a display region, gate lead lines provided in a non-display region and respectively connected to the gate lines and a gate driver IC, and data lead lines provided in the non-display region and respectively connected to the data lines and a data driver IC. The array substrate further includes: at least one first repairing line provided in a same layer as the gate lead lines, and at a position corresponding to a data lead line; and/or, at least one second repairing line provided in a same layer as the data lead lines, and at a position corresponding to a gate lead line.
    Type: Application
    Filed: October 9, 2013
    Publication date: April 23, 2015
    Inventors: Xiangyang Xu, Hui Wang
  • Publication number: 20150108482
    Abstract: Disclosed are a thin film transistor substrate and a method of repairing a signal line of the thin film transistor substrate. The thin-film transistor substrate includes: a scan line for transferring a scan signal; a light-emission control line for transferring a light-emission control signal; and a capacitor including a first electrode and a second electrode, wherein the second electrode may be provided with a plurality of divided regions, al plurality of bridges coupling the plurality of divided regions to each other, and a plurality of protrusions which overlap at least one of the scan line and the light-emission control line.
    Type: Application
    Filed: March 6, 2014
    Publication date: April 23, 2015
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hyun-Tae Kim
  • Publication number: 20150102302
    Abstract: An organic light emitting diode display includes a substrate having a display unit and a peripheral portion, scan lines in a first direction, data lines in a second direction, pixels in the display unit and having pixel circuit portions and organic light emitting diodes, first dummy lines in the display unit and extending in the first direction, at least one second dummy line in the peripheral portion and extending in the second direction, dummy circuit portions connected to a first dummy line and the at least one second dummy line, driving pads connected to end portions of the data lines, at least one dummy driving pad connected to an end portion of the at least one second dummy line, and a driving circuit configured to transmit a data signal to the driving pads and to the at least one dummy driving pad.
    Type: Application
    Filed: June 24, 2014
    Publication date: April 16, 2015
    Inventors: Tae Gon KIM, Se-Ho KIM, Jae-Sic LEE
  • Patent number: 9006002
    Abstract: The length of the polycrystalline silicon rod (100) is measured with a tape measure, then the polycrystalline silicon rod (100) is hit with a hammer (120), and this hammering sound is recorded in a recorder (140) through a microphone (130). Then, an acoustic signal of the hammering sound is subjected to a fast Fourier transform and a frequency distribution is displayed. Furthermore, a peak frequency f is detected which shows the largest sound volume in the frequency distribution obtained after the fast Fourier transform. The relationship between the length (L) of the polycrystalline silicon rod and the peak frequency f is obtained, and the firmness of the polycrystalline silicon rod is determined on the basis of whether or not the peak frequency f is in a range of f?1,471/L (region A).
    Type: Grant
    Filed: July 4, 2011
    Date of Patent: April 14, 2015
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shigeyoshi Netsu, Fumitaka Kume, Junichi Okada
  • Patent number: 8999734
    Abstract: Disclosed herein are mono-functional silylating compounds that may exhibit enhanced silylating capabilities. Also disclosed are method of synthesizing and using these compounds. Finally methods to determine effective silylation are also disclosed.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: April 7, 2015
    Assignee: American Air Liquide, Inc.
    Inventors: James J. F. McAndrew, Curtis Anderson, Christian Dussarrat
  • Publication number: 20150084014
    Abstract: An organic light emitting display device includes a substrate including a display area and a non-display area, a plurality of scan lines extended in a first direction on the substrate, a plurality of data lines extended in a second direction intersecting the first direction, a plurality of first switching elements in the display area, the plurality of first switching elements being connected to the scan lines and data lines, organic emission layers connected to the first switching elements, first dummy lines between corresponding adjacent ones of the plurality of scan lines, the first dummy lines extending in the first direction, second switching elements disposed in the non-display area, the second switching elements being adjacent to first ends of the first dummy lines, and second dummy lines extended in the second direction, the second dummy lines being adjacent to the second switching elements.
    Type: Application
    Filed: June 18, 2014
    Publication date: March 26, 2015
    Inventors: Tae Gon KIM, Sung Ho CHO, Yong Chul KIM, Ji Yong PARK, Dong-Yoon SO, Mi Jin YOON
  • Publication number: 20150087081
    Abstract: A repairing method of an organic light emitting display device includes insulating a first switching element and an organic light emitting layer of a defective pixel from each other, short-circuiting a first dummy line and the organic emission layer at a first location, the first dummy line being adjacent to the defective pixel among a plurality of dummy lines extending in a first direction, short-circuiting the first dummy line and a second switching element at a second location, the second switching element being a dummy element prior to the short-circuiting, and insulating an inner side of the first dummy line and an outer side of the first dummy line from each other.
    Type: Application
    Filed: June 18, 2014
    Publication date: March 26, 2015
    Inventors: Tae Gon KIM, Jin-Yup KIM
  • Patent number: 8987040
    Abstract: A production device (2) and a method for forming multilayered (3, 4, 5, 6, 7) modules, in particular solar modules (1), which have at least one translucent sheet-like layer (3, 6) and at least one solar- or light-active element is provided. The production device (2) forms the layer structure and has an applicator (33) for a connecting layer (5, 7) for the aforementioned layers (3, 4, 6). Furthermore, the device has a controllable curve(arch)-forming device (17) for bending and rolling a sheet-like layer (3, 6) while the layers are being applied.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: March 24, 2015
    Assignees: Kuka Systems GmbH, Dirk Albrecht
    Inventors: Dirk Albrecht, Jürgen Liepert, Michael Büchler, Rudolf Huber, Thomas Kugler, Peter Kiemstedt
  • Publication number: 20150064807
    Abstract: A method of repairing an organic light-emitting display apparatus, the organic light-emitting display apparatus including a substrate, an organic light-emitting device formed on the substrate, a thin film transistor (TFT) formed on the substrate, an organic insulating layer formed on the TFT, and a conductive pattern formed on the organic insulating layer, the conductive pattern including a shorted part between two conductive elements in the conductive pattern, the method including: removing the short by using a focused ion beam (FIB).
    Type: Application
    Filed: April 1, 2014
    Publication date: March 5, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventors: Zail LHEE, Huiyeon CHOE, Hyori JEON, Younggil PARK
  • Patent number: 8956884
    Abstract: A non-abrading method to facilitate bonding of semiconductor components, such as silicon wafers, that have micro structural defects in a bonding interface surface. In a preferred method, micro structural defects are removed by forming an oxide layer on the bonding interface surface to a depth below the level of the defect, and then removing the oxide layer to expose a satisfactory surface for bonding, thereby increasing line yield and reducing scrap triggers in fabrication facilities.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: February 17, 2015
    Assignee: DunAn Microstaq, Inc.
    Inventor: Parthiban Arunasalam