Abstract: The invention relates to a sealed thin-film device (10, 12, 14), to a method of repairing a sealing layer (20) applied to a thin-film device (30) to produce the sealed thin-film device, to a system (200) for repairing the sealing layer applied to the thin-film device to generate the sealed thin-film device and to a computer program product. The sealed thin-film device comprises a thin-film device and a sealing layer applied on the thin-film device for protecting the thin-film device from environmental influence. The sealed thin-film device further comprises locally applied mending material (40; 42, 44) for sealing a local breach (50) in the sealing layer. An effect of this sealed thin-film device is that the operational life-time of the sealed thin-film device is improved. Furthermore, the production yield of the production of sealed thin-film devices is improved.

Abstract: A method of repairing hollow metal void defects in interconnects and resulting structures. After polishing interconnects, hollow metal void defects become visible. The locations of the defects are largely predictable. A repair method patterns a mask material to have openings over the interconnects (and, sometimes, the adjacent dielectric layer) where defects are likely to appear. A local metal cap is formed in the mask openings to repair the defect. A dielectric cap covers the local metal cap and any recesses formed in the adjacent dielectric layer.

Abstract: Methods and structures for restoring an electrical parameter of a field-effect transistor in an integrated circuit deployed in an end product. A source, a drain, and a gate electrode of a field-effect transistor are coupled with ground. A restoration voltage is applied to a well beneath the field-effect transistor while the source, the drain, and the gate electrode of the field-effect transistor are coupled with ground. The well may be coupled with either a positive supply voltage or ground when a switch is in a first position during normal operation of the integrated circuit and with the restoration voltage when the switch is in a second position during a relaxation operation.

Abstract: The present disclosure relates to a structure and method to create a self-repairing dielectric material for semiconductor device applications. A porous dielectric material is deposited on a substrate, and exposed with treating agent particles such that the treating agent particles diffuse into the dielectric material. A dense non-porous cap is formed above the dielectric material which encapsulates the treating agent particles within the dielectric material. The dielectric material is then subjected to a process which creates damage to the dielectric material. A chemical reaction is initiated between the treating agent particles and the damage, repairing the damage. A gradient concentration resulting from the consumption of treating agent particles by the chemical reaction promotes continuous diffusion the treating agent particles towards the damaged region of the dielectric material, continuously repairing the damage.

Abstract: A method for processing a semiconductor wafer includes applying a release layer to a transparent handler. An adhesive layer, that is distinct from the release layer, is applied between a semiconductor wafer and the transparent handler having the release layer applied thereon. The semiconductor wafer is bonded to the transparent handler using the adhesive layer. The semiconductor wafer is processed while it is bonded to the transparent handler. The release layer is ablated by irradiating the release layer through the transparent handler with a laser. The semiconductor wafer is removed from the transparent handler.

Abstract: The object of the present invention is to provide a method for preparing a nano-sheet array structure of a Group V-VI semiconductor, comprising: (A) providing an electrolyte containing a hydrogen ion and disposing an auxiliary electrode and a working electrode in the electrolyte, wherein the working electrode comprises a Group V-VI semiconductor bulk; and (B) applying a redox reaction bias to the auxiliary electrode and the working electrode to form a nano-sheet array structure on the bulk.

Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes a first plurality of circuit elements where a first portion of the first plurality of circuit elements has defects. The second layer includes a second plurality of circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second plurality of circuit elements for mitigating the defects.

Abstract: Provided are methods and systems for treating shunts on solar cell substrates. Also provided are solar cells including such substrates. A shunt detected on a substrate proximate to a metallized grid pattern is electrically disconnected from at least the bus portion of the grid, which reduces shunt's impact on performance on the solar cell. An antireflective layer may be disposed between the shunt and a portion of the grid extending over the shunt. The exposure pattern of a photoresist used to form the antireflective layer may be adjusted accordingly to achieve this result. In some embodiments, the metallized grid may be modified by adjusting the exposure pattern of a photoresist used to form this grid. The grid may be modified to avoid any contact between the grid and the shunt or to disconnect a portion of the grid contacting the shunt from the bus portion area of the grid.

Abstract: A TFT substrate is provided in which a wire defect can be easily solved. A method of solving a wire defect in the TFT substrate is also provided. In an embodiment, the TFT substrate is configured so that (i) a plurality of gate lines and a plurality of source lines are arranged in a matrix manner, (ii) a TFT is provided in at least one of intersection regions where the plurality of gate lines and the plurality of source lines intersect with each other, and (iii) the at least one of intersection regions is divided by a slit, which is formed in a corresponding one of the plurality of gate lines, so that the at least intersection region is divided into parts arranged along a longitudinal direction of the plurality of source lines.

Abstract: An array substrate, a repairing method thereof and a display device, wherein the array substrate includes: a plurality of gate lines and a plurality of data lines provided in a display region, gate lead lines provided in a non-display region and respectively connected to the gate lines and a gate driver IC, and data lead lines provided in the non-display region and respectively connected to the data lines and a data driver IC. The array substrate further includes: at least one first repairing line provided in a same layer as the gate lead lines, and at a position corresponding to a data lead line; and/or, at least one second repairing line provided in a same layer as the data lead lines, and at a position corresponding to a gate lead line.

Abstract: Disclosed are a thin film transistor substrate and a method of repairing a signal line of the thin film transistor substrate. The thin-film transistor substrate includes: a scan line for transferring a scan signal; a light-emission control line for transferring a light-emission control signal; and a capacitor including a first electrode and a second electrode, wherein the second electrode may be provided with a plurality of divided regions, al plurality of bridges coupling the plurality of divided regions to each other, and a plurality of protrusions which overlap at least one of the scan line and the light-emission control line.

Abstract: An organic light emitting diode display includes a substrate having a display unit and a peripheral portion, scan lines in a first direction, data lines in a second direction, pixels in the display unit and having pixel circuit portions and organic light emitting diodes, first dummy lines in the display unit and extending in the first direction, at least one second dummy line in the peripheral portion and extending in the second direction, dummy circuit portions connected to a first dummy line and the at least one second dummy line, driving pads connected to end portions of the data lines, at least one dummy driving pad connected to an end portion of the at least one second dummy line, and a driving circuit configured to transmit a data signal to the driving pads and to the at least one dummy driving pad.

Abstract: The length of the polycrystalline silicon rod (100) is measured with a tape measure, then the polycrystalline silicon rod (100) is hit with a hammer (120), and this hammering sound is recorded in a recorder (140) through a microphone (130). Then, an acoustic signal of the hammering sound is subjected to a fast Fourier transform and a frequency distribution is displayed. Furthermore, a peak frequency f is detected which shows the largest sound volume in the frequency distribution obtained after the fast Fourier transform. The relationship between the length (L) of the polycrystalline silicon rod and the peak frequency f is obtained, and the firmness of the polycrystalline silicon rod is determined on the basis of whether or not the peak frequency f is in a range of f?1,471/L (region A).

Abstract: Disclosed herein are mono-functional silylating compounds that may exhibit enhanced silylating capabilities. Also disclosed are method of synthesizing and using these compounds. Finally methods to determine effective silylation are also disclosed.

Abstract: An organic light emitting display device includes a substrate including a display area and a non-display area, a plurality of scan lines extended in a first direction on the substrate, a plurality of data lines extended in a second direction intersecting the first direction, a plurality of first switching elements in the display area, the plurality of first switching elements being connected to the scan lines and data lines, organic emission layers connected to the first switching elements, first dummy lines between corresponding adjacent ones of the plurality of scan lines, the first dummy lines extending in the first direction, second switching elements disposed in the non-display area, the second switching elements being adjacent to first ends of the first dummy lines, and second dummy lines extended in the second direction, the second dummy lines being adjacent to the second switching elements.

Abstract: A repairing method of an organic light emitting display device includes insulating a first switching element and an organic light emitting layer of a defective pixel from each other, short-circuiting a first dummy line and the organic emission layer at a first location, the first dummy line being adjacent to the defective pixel among a plurality of dummy lines extending in a first direction, short-circuiting the first dummy line and a second switching element at a second location, the second switching element being a dummy element prior to the short-circuiting, and insulating an inner side of the first dummy line and an outer side of the first dummy line from each other.

Abstract: A production device (2) and a method for forming multilayered (3, 4, 5, 6, 7) modules, in particular solar modules (1), which have at least one translucent sheet-like layer (3, 6) and at least one solar- or light-active element is provided. The production device (2) forms the layer structure and has an applicator (33) for a connecting layer (5, 7) for the aforementioned layers (3, 4, 6). Furthermore, the device has a controllable curve(arch)-forming device (17) for bending and rolling a sheet-like layer (3, 6) while the layers are being applied.

Abstract: A method of repairing an organic light-emitting display apparatus, the organic light-emitting display apparatus including a substrate, an organic light-emitting device formed on the substrate, a thin film transistor (TFT) formed on the substrate, an organic insulating layer formed on the TFT, and a conductive pattern formed on the organic insulating layer, the conductive pattern including a shorted part between two conductive elements in the conductive pattern, the method including: removing the short by using a focused ion beam (FIB).

Abstract: A non-abrading method to facilitate bonding of semiconductor components, such as silicon wafers, that have micro structural defects in a bonding interface surface. In a preferred method, micro structural defects are removed by forming an oxide layer on the bonding interface surface to a depth below the level of the defect, and then removing the oxide layer to expose a satisfactory surface for bonding, thereby increasing line yield and reducing scrap triggers in fabrication facilities.

Abstract: A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.

Abstract: A method is provided for fabricating an MOS transistor. The method includes providing a semiconductor substrate; and forming a ploy silicon dummy gate structure having a high-K gate dielectric layer, a high-K gate dielectric protection layer containing nitrogen and a poly silicon dummy gate on the semiconductor substrate. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the poly silicon dummy gate structure. Further, the method includes removing the poly silicon dummy gate to form a trench exposing the high-K gate dielectric protection layer containing nitrogen and performing a nitrogen treatment process to repair defects in the high-K gate dielectric protection layer containing nitrogen caused by removing the poly silicon dummy gate. Further, the method also includes forming a metal gate structure in the trench.

Abstract: A method of removing particles from a display panel is disclosed. In one aspect, the method includes charging the particles and applying an electric field to the charged particles to capture the charged particles. Organic particles and inorganic particles may be forcibly charged to capture the organic and inorganic particles using a metal bar so that the organic and inorganic particles may be substantially removed.

Abstract: A flat display panel and a related repairing method are provided. The flat display panel includes multiple horizontal repair lines parallel to scan lines and multiple vertical repair lines parallel to data lines. The vertical repair lines are disposed on one side of the data lines one to one, and the horizontal repair lines are disposed on one side of the scan lines one to one. When one of the data lines or one of the scan lines is broken, an electrical route formed by a use of the vertical repair lines or the horizontal repair lines detours the broken scan line or data line, so as to deliver signal to pixel electrode normally.

Abstract: A process for recycling a support substrate of a material substantially transparent to at least a wavelength of electromagnetic radiation. The process includes providing an initial substrate; forming an intermediate layer on a bonding face of the support substrate having an initial roughness, with the intermediate layer being of a material substantially transparent to at least a wavelength of electromagnetic radiation; forming an electromagnetic radiation absorbing layer either on the bonding face of the initial substrate or on the intermediate layer; bonding the initial substrate to the support substrate via the electromagnetic radiation absorbing layer; and irradiating the electromagnetic radiation absorbing layer through the support substrate and the intermediate layer to induce separation of the support substrate from the initial substrate.

Abstract: Anodes of a plurality of organic EL elements are connected together. A forward bias voltage relative to the potential of anodes and a reverse bias voltage are alternately applied to cathodes of the plurality of organic EL elements at a predetermined period. The ratio of the time for which the reverse bias voltage is applied and the time for which the forward bias voltage is applied is increased.

Abstract: The invention relates to a sealed thin-film device, to a method of repairing a sealing layer applied to a thin-film device to produce the sealed thin-film device, to a system for repairing the sealing layer applied to the thin-film device to generate the sealed thin-film device and to a computer program product. The sealed thin-film device comprises a thin-film device and a sealing layer applied on the thin-film device for protecting the thin-film device from environmental influence. The sealing layer comprises at least a first and a second barrier layer and a getter layer arranged between the first and the second barrier layer. The sealed thin-film device further comprises locally applied mending material for sealing a local breach in an outer one of said barrier layers.

Abstract: Provided is an organic light-emitting display apparatus and a method of repairing the same. The organic light-emitting display apparatus includes: an emission device comprising a plurality of sub-emission devices; an emission pixel circuit configured to supply a driving current to the emission device; a dummy pixel circuit configured to supply the driving current to the emission device; and a repair line coupling the emission device to the dummy pixel circuit, wherein the emission device is configured to receive the driving current from the emission pixel circuit or the dummy pixel circuit.

Abstract: A control method of a multi-chip package memory device includes the steps of applying stack signals to stack pads of memory dies, applying a repair signal to repair pads of the respective memory dies, setting one or more repaired memory dies for replacing a failed memory die among the memory dies, based on the repair signal applied to the respective memory dies, and setting stack states indicating a logical access order of the other memory dies excluding the repaired memory die, based on the stack signals applied to the other memory dies.

Abstract: The object of the present invention is to provide a method for preparing a nano-sheet array structure of a Group V-VI semiconductor, comprising: (A) providing an electrolyte containing a hydrogen ion and disposing an auxiliary electrode and a working electrode in the electrolyte, wherein the working electrode comprises a Group V-VI semiconductor bulk; and (B) applying a redox reaction bias to the auxiliary electrode and the working electrode to form a nano-sheet array structure on the bulk.

Abstract: A method for making a packaged integrated circuit is provided. The method includes making a first panel of encapsulated die. In some embodiments, if a threshold number of die are not positioned in proper positions in the first panel, the die are separated from the first panel. The separated die are subsequently encapsulated in other panels of encapsulated die. Conductive interconnects can be formed over the other panels. The other panels are then separated into integrated circuit packages.

Abstract: Such a device is disclosed that includes: redundancy circuits for replacing defective memory cells included in a memory cell array; an electrical fuse circuit that stores addresses of the defective memory cells; a data determination circuit that generates a determination signal by determining whether test data read from the memory cell array is correct or incorrect; and an analysis circuit that supplies, in a first operation mode, the electrical fuse circuit with an address signal supplied when the determination signal is activated, and supplies, in a second operation mode, the electrical fuse circuit with an address signal supplied when a data mask signal supplied from outside is activated irrespective of the determination signal.

Abstract: A TFT substrate is provided in which a wire defect can be easily solved. A method of solving a wire defect in the TFT substrate is also provided. In an embodiment, the TFT substrate is configured so that (i) a plurality of gate lines and a plurality of source lines are arranged in a matrix manner, (ii) a TFT is provided in at least one of intersection regions where the plurality of gate lines and the plurality of source lines intersect with each other, and (iii) the at least one of intersection regions is divided by a slit, which is formed in a corresponding one of the plurality of gate lines, so that the at least intersection region is divided into parts arranged along a longitudinal direction of the plurality of source lines.

Abstract: To provide a light-emitting element or a light-emitting device in which power is not consumed wastefully even if a short-circuit failure occurs. The present invention focuses on heat generated due to a short-circuit failure which occurs in a light-emitting element. A fusible alloy which is melted at temperature T2 by heat generated due to the short-circuit failure when the short-circuit failure occurs is used for at least one of a pair of electrodes in a light-emitting element, and a layer containing an organic composition which is melted at temperature T1 is formed on a surface of the electrode opposite to a surface facing the other electrode. The present inventors have reached a structure in which the temperature T2 is lower than temperature T3 at which the light-emitting element is damaged and the temperature T1 is lower than the temperature T2, and this structure can achieve the objects.

Abstract: A spin-current switched magnetic memory element includes a plurality of magnetic layers, at least one of the plurality of magnetic layers having a perpendicular magnetic anisotropy component and including a current-switchable magnetic moment, and at least one barrier layer formed adjacent to the plurality of magnetic layers. The plurality of magnetic layers includes at least one composite layer.

Abstract: An inertial angular sensor of MEMS type has a support of at least two masses which are mounted movably with respect to the support, at least one electrostatic actuator and at least one electrostatic detector. The masses are suspended in a frame itself connected by suspension means to the support. The actuator and the detector are designed to respectively produce and detect a vibration of the masses, and a method for balancing such a sensor provided with at least one load detector mounted between the frame and the support and with at least one electrostatic spring placed between the frame and one of the masses and slaved so as to ensure dynamic balancing of the sensor as a function of a measurement signal of the load sensor.

Abstract: A semiconductor memory device includes at least one first semiconductor chip including a plurality of memory cells and a second semiconductor chip including a fuse circuit configured to repair defective cells among the memory cells of the at least one first semiconductor chip.

Abstract: A warp correction apparatus includes an injection mechanism including a nozzle that performs injection treatment, an adsorption table that holds the substrate by adsorption at a principal surface side or a film surface side, a moving mechanism that moves the adsorption table so that the substrate relatively moves with respect to an injection area of an injection particle by the nozzle, an injection treatment chamber that houses the substrate held on the adsorption table and in the interior of which injection treatment is performed, a measurement mechanism that measures a warp of the substrate, and a control device that, based on a difference between a target warp amount and a warp amount measured by the measurement mechanism, performs at least either one of a setting processing of an injection treatment condition of the injection mechanism and an accept/reject determination of the substrate for which injection treatment has been performed.

Abstract: A method of detaching a sealing member of a light emitting device which has a substrate, a light emitting element mounted on the substrate and a sealing member that seals the light emitting element, wherein a release layer and/or an air layer is/are provided between the substrate and the sealing member; and the sealing member is detached from the substrate at the release layer and/or the air layer.

Abstract: One illustrative method disclosed herein includes providing a layer of a carbon-containing insulating material having a nominal carbon concentration, performing at least one process operation on the carbon-containing insulating material that results in the formation of a reduced-carbon-concentration region in the layer of carbon-containing insulating material, wherein the reduced-carbon-concentration region has a carbon concentration that is less than the nominal carbon concentration, performing a carbon-introduction process operation to introduce carbon atoms into at least the reduced-carbon-concentration region and thereby define a carbon-enhanced region having a carbon concentration that is greater than the carbon concentration of the reduced-carbon-concentration region and, after introducing the carbon atoms, performing a heating process on at least the carbon-enhanced region.

Abstract: A method for etching trenches in an etch layer disposed below a patterned organic mask is provided. The patterned organic mask is treated, comprising flowing a treatment gas comprising H2 and N2, forming a plasma from the treatment gas, making patterned organic mask more resistant to wiggling, and stopping the flow of the treatment gas. Trenches are etched in the etch layer through the patterned organic mask.

Abstract: A thin film transistor substrate includes a substrate including a display area including: pixels and a periphery area where a driver for driving the pixels is disposed; first signal lines connected with the pixels and extended to the periphery area, and including first short-circuit portions provided in the periphery area; second signal lines connected with the pixels and extended to the periphery area by crossing the first signal lines in an insulated manner; first connection members overlapping lateral ends of the first signal lines, disposed in lateral sides with respect to the first short-circuited portions, and formed of a doped semiconductor; and first repairing conductors overlapping the lateral ends of the first signal lines, and disposed in the lateral sides with respect to the first short-circuited portions. Lateral ends of the first connection members are connected with the lateral ends of the first signal lines through contact holes.

Abstract: A substrate warp correcting device includes, a lower member including a concave portion, and the lower member on which a substrate is to be arranged, an upper member arranged above the lower member, and the upper member including a gas supplying hole, wherein the substrate is arranged between the lower member and the upper member and above the concave portion, and a sealing member arranged between a periphery part of the substrate and the upper member, and the sealing member sealing a space between the substrate and the upper member.

Abstract: Such a device is disclosed that includes: redundancy circuits for replacing defective memory cells included in a memory cell array; an electrical fuse circuit that stores addresses of the defective memory cells; a data determination circuit that generates a determination signal by determining whether test data read from the memory cell array is correct or incorrect; and an analysis circuit that supplies, in a first operation mode, the electrical fuse circuit with an address signal supplied when the determination signal is activated, and supplies, in a second operation mode, the electrical fuse circuit with an address signal supplied when a data mask signal supplied from outside is activated irrespective of the determination signal.

Abstract: The invention concerns a silicon devices/heatsinks stack assembly and a method to pull apart a faulty silicon device in said stack assembly. Said silicon devices/heatsinks stack assembly comprises an arrangement of many silicon devices disks, two adjacent silicon devices disks being separated by a flat heatsink device, each silicon device disk and each heatsink comprising a centering hole on its both faces, a centering pin placed between the adjacent centering holes of a silicon device disk and an adjacent heatsink device. Each heatsink device is pierced with two guide holes, at two opposite ends of this one.

Abstract: A method and apparatus for repairing transistors may include applying a first voltage to a source, a second voltage to the gate and a third voltage to the drain for a predetermined time. In this manner the transistor structure may be repaired or returned to operate at or near the original operating characteristics.

Abstract: A method for manufacturing a flexible display device includes: manufacturing a flexible substrate on a substrate by: forming a first organic layer on the substrate, removing foreign particles formed on the first organic layer and forming a recessed first repair groove in the first organic layer, forming a first inorganic layer on the first organic layer, forming a second organic layer on the first inorganic layer and forming a second inorganic layer on the second organic layer, forming a display for displaying an image on the flexible substrate and removing the substrate from the first organic layer.

Abstract: In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional.

Abstract: The present invention provides an organic EL panel and a manufacturing method of the organic EL layer which can slow the reduction in the light emission lifetime of an organic layer and allow a short-circuit defect to be repaired. Organic EL elements include: an organic EL element including a short-circuit portion, and an altered portion formed to be highly resistive by irradiating a cathode with a laser beam; and an organic EL element which does not include the short-circuit portion. In the organic EL element, an organic EL layer emits light when a voltage higher than or equal to a first voltage is applied. In the organic EL element, the organic EL layer emits light when a voltage higher than equal to a second voltage that is higher than the first voltage is applied.

Abstract: A method for repairing process-related damage of a dielectric film includes: (i) adsorbing a first gas containing silicon on a surface of the damaged dielectric film without depositing a film in the absence of reactive species, (ii) adsorbing a second gas containing silicon on a surface of the dielectric film, followed by applying reactive species to the surface of the dielectric film, to form a monolayer film thereon, and (iii) repeating step (ii). The duration of exposing the surface to the first gas in step (i) is longer than the duration of exposing the surface to the second gas in step (ii).

Abstract: A method of recycling a silicon component for a plasma etching apparatus includes a collecting process of collecting silicon wastes from any one of a silicon component for a plasma etching apparatus and a silicon ingot for a semiconductor wafer; a measurement process of obtaining a content of impurity based on an electric characteristic of the collected silicon wastes; an input amount determination process of determining an input amount of the silicon wastes, an input amount of a silicon source material, and an input amount of impurity based on the content of impurity obtained in the measurement process and a target value of an electric characteristic of a final product; and a silicon ingot manufacturing process of manufacturing a silicon ingot by inputting the silicon wastes, the silicon source material, and the impurity based on the input amounts determined in the input amount determination process into a crucible.