Abstract: The present invention provides a method for preparing a nanoporous ultra-low dielectric thin film including a high-temperature ozone treatment and nanoporous ultra-low dielectric thin film prepared by the same method. The method includes preparing a mixture of an organic silicate matrix-containing solution and a reactive porogen-containing solution; coating the mixture on a substrate to form a thin film; and heating the thin film with an ozone treatment. The prepared nanoporous ultra-low dielectric thin film could have a dielectric constant of about 2.3 or less and a mechanical strength of about 10 GPa or more by improving a pore size and a distribution of pores in the thin film by performing an ozone treatment with high temperature and optimization of the ozone treatment temperature.

Abstract: Embodiments relate to a method for forming reliable interconnects by preparing a substrate with a dielectric layer, processing the dielectric layer to serve as an IMD layer, wherein the IMD layer comprises a hybrid IMD layer comprising a plurality of dielectric materials with different k values.

Abstract: To provide a substrate for optics provided with a fine-structure product which improves luminous efficiency of an LED while improving internal quantum efficiency IQE by decreasing the number of dislocation defects in a semiconductor layer, a substrate for optics (1) is provided with a fine-structure layer (12) including dots comprised of a plurality of convex portions (13) extending in the direction of from the main surface of a substrate (11) to outside the surface, where the fine-structure layer (12) has a plurality of dot lines (13-1 to 13-N) in which a plurality of dots is arranged with a pitch Py in the first direction in the main surface of the substrate (11), while having the plurality of dot lines in which a plurality of dots is arranged with a pitch Px in the second direction orthogonal to the first direction in the main surface of the substrate (11), one of the pitch Py and the pitch Px is a constant interval of nano-order, while the other one is an inconstant interval of nano-order, or both are inc

Abstract: A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.

Abstract: A method of fabricating an electromechanical device includes the following steps. A first and a second back gate are formed over a substrate. An etch stop layer is formed covering the first and second back gates. Electrodes are formed over the first and second back gates, wherein the electrodes include one or more gate, source, and drain electrodes, wherein gaps are present between the source and drain electrodes. One or more Janus components are placed the gaps, each of which includes a first portion having an electrically conductive material and a second portion having an electrically insulating material, and wherein i) the first or second portion of the Janus components placed in a first one of the gaps has a fixed positive surface charge and ii) the first or second portion of the Janus components placed in a second one of the gaps has a fixed negative surface charge.

Abstract: A bonded device having at least one porosified surface is disclosed. The porosification process introduces nanoporous holes into the microstructure of the bonding surfaces of the devices. The material property of a porosified material is softer as compared to a non-porosified material. For the same bonding conditions, the use of the porosified bonding surfaces enhances the bond strength of the bonded interface as compared to the non-porosified material.

Abstract: Provided is a method of producing a wafer for a solar cell that can produce the solar cell with high conversion efficiency. A method of producing a wafer for a solar cell according to the present invention comprises a first step of contacting lower alcohol to at least one surface of the semiconductor wafer and a second step, after the first step, of contacting hydrofluoric acid containing metal ion to the at least one surface of the semiconductor wafer, and a third step that is, after the second step, a step of contacting alkali solution to the at least one surface of the semiconductor wafer, a step of contacting acid solution containing hydrofluoric acid and nitric acid to the at least one surface of the semiconductor wafer, or a step of carrying out an oxidation treatment to the at least one surface of the semiconductor wafer.

Abstract: A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer arranged between the semiconductor portion and the non-porous semiconductor layer, forming a porous oxide layer by oxidizing the porous semiconductor layer, forming a bonded substrate by bonding a supporting substrate to a surface, on a side of the non-porous semiconductor layer, of the substrate on which the porous oxide layer is formed, and separating the semiconductor portion from the bonded substrate by utilizing the porous oxide layer.

Abstract: In accordance with the invention, there are methods of controlling the sidewall angle of a polysilicon gate from batch to batch while maintaining current bottom critical dimension control performance. The method can include generating a correlation between a sidewall angle of a gate and RF bias power and etch time of one or more etch steps during the formation of the gate, developing a statistical model for the sidewall angle as a function of one or more of polysilicon density, polythickness, and etcher, and predicting a sidewall angle using the statistical model for a given polydensity, a given polythickness, and a given etcher. The method can also include comparing the predicted sidewall angle with a target sidewall angle and determining an optimized RF bias power and optimized etch time of one or more etch steps during the formation of the gate using the correlation to match the target sidewall angle.

Abstract: A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the high adhesion phase change material. The high adhesion phase change material includes a greater amount of at least one of nitrogen and oxygen than the low adhesion phase change material. The phase change material is produced by forming a first chalcogenide compound material including an amount of at least one of nitrogen and oxygen on the dielectric material and forming a second chalcogenide compound including a lower percentage of at least one of nitrogen and oxygen on the first chalcogenide compound material. A phase change random access memory device, and a semiconductor structure are also disclosed.

Abstract: Provided is an organic EL apparatus including: an organic EL panel including organic EL devices; a heat releasing member; and a pair of film sheets of which at least one is transparent, wherein the organic EL panel and the heat releasing member overlap and are interposed and encapsulated by the pair of film sheets in a state where a portion of the heat releasing member is exposed outside the pair of film sheets.

Abstract: A porous lift off layer facilitates removal of films from surfaces, such as semiconductors. A layer, with porosities typically larger than the film thickness is provided where no film is desired. The film is applied over the porous layer and also where it is desired. The porous material and the film are then removed from areas where film is not intended. The porous layer can be provided as a slurry, dried to open porosities, or fugitive particles within a field, which disassociate upon the application of heat or solvent. The film can be removed by etchant that enters through porosities that have arisen due to the film not bridging the spaces between solid portions. Etchant attacks both film surfaces. Particles may have diameters of four to ten times the film thickness. Particles may be silica, alumina and ceramics. Porous layers can be used in depressions or on flat surfaces.

Abstract: The present invention discloses a CMOS device of reducing charge sharing effect and a fabrication method thereof. The present invention has an additional isolation for trapping carriers disposed right below an isolation region. the material of the additional isolation region is porous silicon. Since porous silicon is a functional material of spongy structure by electrochemistry anodic oxidizing monocrystalline silicon wafer, there are a large number of microvoids and dangling bonds on the surface layer of the porous silicon. These defects may form defect states in a center of forbidden band of the porous silicon, the defect states may trap carriers so as to cause an increased resistance. And with an increase of density of corrosion current, porosity increases, and defects in the porous silicon increase.

Abstract: Electromechanical transistors that employ Janus micro/nano-components and techniques for the fabrication thereof are provided. In one aspect, a method of fabricating an electromechanical transistor includes the following steps. A wafer is provided. A source electrode and a drain electrode are formed opposite one another on a surface of the wafer, wherein a gap is present between the source electrode and the drain electrode. A first gate electrode and a second gate electrode are formed on the surface of the wafer on opposite sides of the gap between the source electrode and the drain electrode. At least one Janus component is placed in the gap between the source electrode and the drain electrode, wherein the Janus component includes a first portion having an electrically conductive material and a second portion having an electrically insulating material.

Abstract: A semiconductor device manufacturing method for manufacturing a semiconductor device having a transistor mounted in a wiring of a plural-layer structure includes in manufacturing the semiconductor device that is formed on a semiconductor element and includes a barrier insulating film, a porous interlayer insulating film, a wiring, a via plug formed by embedding a metal wiring material in a wiring trench, and a via hole formed in the porous interlayer insulating film, irradiating an electron beam or an ultraviolet ray onto at least a portion of the porous interlayer insulating film before forming an opening in the barrier insulating film.

Abstract: A method of making an integrated circuit includes providing a substrate with a high-k dielectric and providing a polysilicon gate structure over the high-k dielectric. A doping process is performed on the substrate adjacent to the polysilicon gate structure, after which the polysilicon gate structure is removed and replaced with a metal gate structure. An interlayer dielectric (ILD) is deposited over the metal gate structure and the doped substrate, and a dry etch process forms a trench in the ILD to a top surface of the metal gate structure. After the dry etch process, a wet etch process forms an undercut near the top surface of the metal gate structure. The trench and undercut are then filled with a conductive material.

Abstract: A method for transferring a micro-technological layer includes preparing a substrate having a porous layer buried beneath a useful surface, forming an embrittled zone between it and the surface, bonding the substrate to a supporting substrate, causing detachment at the porous layer by mechanical stress to obtain a first substrate remnant, and a bare surfaced detached layer joined to the supporting substrate, performing technological steps on the bared surface of the detached layer, bonding the detached layer, by the surface to which the technological steps had been applied, to a second supporting substrate, causing detachment, at the embrittled zone, by heat treatment to obtain a detached layer remnant joined to the second supporting substrate, and the detached layer remnant joined to the first supporting substrate.

Abstract: Defects in a semiconductor substrate are reduced. A semiconductor substrate with fewer defects is manufactured with high yield. Further, a semiconductor device is manufactured with high yield. A semiconductor layer is formed over a supporting substrate with an oxide insulating layer interposed therebetween, adhesiveness between the supporting substrate and the oxide insulating layer in an edge portion of the semiconductor layer is increased, an insulating layer over a surface of the semiconductor layer is removed, and the semiconductor layer is irradiated with laser light, so that a planarized semiconductor layer is obtained. For increasing the adhesiveness between the supporting substrate and the oxide insulating layer in the edge portion of the semiconductor layer, laser light irradiation is performed from the surface of the semiconductor layer.

Abstract: Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate.

Abstract: Methods of fabricating semiconductor structures and devices include bonding a seed structure to a substrate using a glass. The seed structure may comprise a crystal of semiconductor material. Thermal treatment of the seed structure bonded to the substrate using the glass may be utilized to control a strain state within the seed structure. The seed structure may be placed in a state of compressive strain at room temperature. The seed structure bonded to the substrate using the glass may be used for growth of semiconductor material, or, in additional methods, a seed structure may be bonded to a first substrate using a glass, thermally treated to control a strain state within the seed structure and a second substrate may be bonded to an opposite side of the seed structure using a non-glassy material.

Abstract: A transmission electron microscope (TEM) micro-grid includes a grid and a heater including at least one carbon nanotube film structure located on the grid. The micro-grid with the at least one carbon nanotube film structure prevents a floating of the sample located on the micro-grid to increase the quality of TEM images.

Abstract: Silicon-based explosive devices and methods of manufacture are provided. In this regard, a representative method involves: providing a doped silicon substrate; depositing undoped silicon on a first side of the substrate; and infusing an oxidizer into an area bounded at least in part by the undoped silicon; wherein the undoped silicon limits an exothermic reaction of the doped silicon to the bounded area. Another representative method involves: providing a doped silicon substrate; depositing a masking layer of low-pressure chemical vapor deposited (LPCVD) Silicon nitride to the first side of the substrate; patterning the nitride mask and etching the porous silicon, and infusing oxidizer into an area bounded by the LPCVD nitride; wherein the silicon nitride limits an exothermic reaction of the doped silicon to the bounded area.

Abstract: In a preferred method of formation embodiment, a metal foil or film is obtained or formed with micro-holes. The foil is anodized to form metal oxide. One or more self-patterned metal electrodes are automatically formed and buried in the metal oxide created by the anodization process. The electrodes form in a closed circumference around each microcavity in a plane(s) transverse to the microcavity axis, and can be electrically isolated or connected. Preferred embodiments provide inexpensive microplasma device electrode structures and a fabrication method for realizing microplasma arrays that are lightweight and scalable to large areas. Electrodes buried in metal oxide and complex patterns of electrodes can also be formed without reference to microplasma devices—that is, for general electrical circuitry.

Abstract: Methods are provided for forming a structure that includes an air gap. In one embodiment, a method is provided for forming a damascene structure including depositing a porous low dielectric constant layer by a method including reacting an organosilicon compound and a porogen-providing precursor, depositing a porogen-containing material, and removing at least a portion of the porogen-containing material, depositing an organic layer on the porous low dielectric constant layer by reacting the porogen-providing precursor, forming a feature definition in the organic layer and the porous low dielectric constant layer, filing the feature definition with a conductive material therein, depositing a mask layer on the organic layer and the conductive material disposed in the feature definition, forming apertures in the mask layer to expose the organic layer, removing a portion or all of the organic layer through the apertures, and forming an air gap adjacent the conductive material.

Abstract: A structure of a porous low-k layer is described, comprising a bottom portion and a body portion of the same atomic composition, wherein the body portion is located on the bottom portion, and the bottom portion has a density higher than the density of the body portion. An interconnect structure is also described, including the above porous low-k layer, and a conductive layer filling up a damascene opening in the porous low-k layer.

Abstract: To provide a structure and a manufacturing method for efficiently forming a transistor to which tensile strain is preferably applied and a transistor to which compressive strain is preferably applied over the same substrate when stress is applied to a semiconductor layer in order to improve mobility of the transistors in a semiconductor device. Plural kinds of transistors which are separated from a single-crystal semiconductor substrate and include single-crystal semiconductor layers bonded to a substrate having an insulating surface with a bonding layer interposed therebetween are provided over the same substrate. One of the transistors uses a single-crystal semiconductor layer as an active layer, to which tensile strain is applied. The other transistors use single-crystal semiconductor layers as active layers, to which compressive strain using part of heat shrink generated by heat treatment of the base substrate after bonding is applied.

Abstract: A method for producing an electro-mechanical microsystem including movable mechanical parts, said method including a phase of releasing at least one movable mechanical part, wherein the releasing phase includes the following steps: formation of at least one porous zone in a first wafer of a semiconductor material; formation of at least a pattern of a material that makes at least one movable mechanical part on a front face of the first wafer and at least a partial encapsulation of the pattern in a sacrificial layer; release of the movable mechanical part through a rear face of the first wafer throughout the porous zone, using a solvent of the sacrificial layer.

Abstract: A transmission electron microscope (TEM) micro-grid includes a grid, a carbon nanotube film structure and two electrodes electrically connected to the carbon nanotube film structure.

Abstract: A transmission electron microscope (TEM) micro-grid includes a metallic grid and a carbon nanotube film structure covered thereon. A method for making a TEM micro-grid includes the steps of: (a) providing an array of carbon nanotubes, quite suitably, providing a super-aligned array of carbon nanotubes; (b) drawing a carbon nanotube film from the array of carbon nanotubes; (c) covering the carbon nanotube film on a metallic grid, and treating the carbon nanotube film and the metallic grid with an organic solvent.

Abstract: A phase change memory device having a bottleneck constriction and method of making same are presented. The phase change memory device includes a semiconductor substrate, a lower electrode, an interlayer film, an insulator, a phase change layer and an upper electrode. The interlayer film is formed on the semiconductor substrate having the lower electrode. The interlayer film includes a laminate of a first insulating film, a silicon film and a second insulating film with a hole formed therethrough. The insulator is disposed along the exposed surface of the silicon film around the inner circumference of the hole. The phase change layer is embedded within the hole having the insulator which constricts the shape of the phase change layer to a bottleneck constriction. A method of manufacturing the phase change memory device is also provided.

Abstract: A transmission electron microscope (TEM) micro-grid includes a pure carbon grid having a plurality of holes defined therein and at least one carbon nanotube film covering the holes. A method for manufacturing a TEM micro-grid includes following steps. A pure carbon grid precursor and at least one carbon nanotube film are first provided. The at least one carbon nanotube film is disposed on a surface of the pure carbon grid precursor. The pure carbon grid precursor and the at least one carbon nanotube film are then cut to form the TEM micro-grid in desired shape.

Abstract: A method of fabricating an electrically conductive mechanical interconnection element (12) comprises: a first stage of electrochemically depositing a structure comprising a plurality of metal wires (2a) of sub-micrometric diameter projecting from the likewise metallic surface of a substrate (2); and a second stage of controlled partial dissolution of said wires to reduce their diameter. A method of making a mechanical and/or electrical interconnection, the method comprising the steps consisting in: fabricating two interconnection elements by a method as described above; and placing said interconnection elements face to face and pressing one against the other so as to cause the nanometric wires projecting from the surfaces of said elements to interpenetrate and tangle together. A three-dimensional electronic device comprising a stack of microelectronic chips mechanically and electrically connected to one another by such interconnection elements.

Abstract: A method for manufacturing a semiconductor structure is provided which includes the following operations: supplying a crystalline semiconductor substrate, providing a porous region adjacent to a surface of the semiconductor substrate, introducing a dopant into the porous region from the surface, and thermally recrystallizing the porous region into a crystalline doping region of the semiconductor substrate whose doping type and/or doping concentration and/or doping distribution are/is different from those or that of the semiconductor substrate. A corresponding semiconductor structure is likewise provided.

Abstract: In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric.

Abstract: A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the high adhesion phase change material. The high adhesion phase change material includes a greater amount of at least one of nitrogen and oxygen than the low adhesion phase change material. The phase change material is produced by forming a first chalcogenide compound material including an amount of at least one of nitrogen and oxygen on the dielectric material and forming a second chalcogenide compound including a lower percentage of at least one of nitrogen and oxygen on the first chalcogenide compound material. A phase change random access memory device, and a semiconductor structure are also disclosed.

Abstract: A method of manufacturing a solar cell having a texture on a surface of a silicon substrate includes first forming a porous layer on the surface of the silicon substrate by dipping the silicon substrate into a mixed aqueous solution of oxidizing reagent containing metal ions and hydrofluoric acid. Second, a texture is formed by etching the surface of the silicon substrate after the porous layer is formed, by dipping the silicon substrate into a mixed acid mainly containing hydrofluoric acid and nitric acid.

Abstract: If the size of a single crystal silicon layer attached is not appropriate, even when a large glass substrate is used, the number of panels to be obtained cannot be maximized. Therefore, in the present invention, a substantially quadrangular single crystal semiconductor substrate is formed from a substantially circular single crystal semiconductor wafer, and a damaged layer is formed by irradiation with an ion beam into the single crystal semiconductor substrate. A plurality of the single crystal semiconductor substrates are arranged so as to be separated from each other over one surface of a supporting substrate. By thermal treatment, a crack is generated in the damaged layer and the single crystal semiconductor substrate is separated while a single semiconductor layer is left over the supporting substrate. After that, one or a plurality of display panels is manufactured from the single crystal semiconductor layer bonded to the supporting substrate.

Abstract: The present invention provides a porous semiconductive structure, characterized in that the structure has an electrical conductivity of 5·10?8 S·cm?1 to 10 S·cm?1, and an activation energy of the electrical conductivity of 0.1 to 700 meV, and a solid fraction of 30 to 60% by volume, and a pore size of 1 nm to 500 nm, the solid fraction having at least partly crystalline doped constituents which are bonded to one another via sinter necks and have sizes of 5 nm to 500 nm and a spherical and/or ellipsoidal shape, which comprise the elements silicon, germanium or an alloy of these elements, and also a process for producing a porous semiconductive structure, characterized in that A. doped semimetal particles are obtained, and then B. a dispersion is obtained from the semimetal particles obtained after step A, and then C. a substrate is coated with the dispersion obtained after step B, and then D. the layer obtained after step C is treated by means of a solution of hydrogen fluoride in water, and then E.

Abstract: The present invention provides a method for forming a silicon oxide film, which has excellent insulating properties and higher quality that can enhance a yield in manufacture of semiconductor devices, while keeping advantageous points in a plasma oxidation process. In this method, plasma is generated under a first process condition that a ratio of oxygen in a processing gas is 1% or less and pressure is within a range of 0.133 to 133 Pa, so as to form the silicon oxide film, by oxidizing silicon on a surface of an object to be processed including silicon as a main component, by using the plasma (first oxidation step). Following the first oxidation step, the plasma is generated under a second process condition that the ratio of oxygen in the processing gas is 20% or more and the pressure is within a range of 400 to 1333 Pa, so as to form an additional silicon oxide film, by further oxidizing the surface of the object to be processed, by using the plasma (second oxidation step).

Abstract: Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided.

Abstract: A method of forming a porous low-k layer is described. A CVD process is conducted to a substrate, wherein a framework precursor and a porogen precursor are supplied. In an end period of the supply of the framework precursor, the value of at least one deposition parameter negatively correlated with the density of the product of the CVD process is decreased.

Abstract: A semiconductor structure and a method of manufacturing a silicon on insulator (SOI) structure having a silicon germanium (SiGe) layer interposed between the silicon and the insulator. According to one manufacturing method, a first SiGe layer, a silicon layer, and a second SiGe layer are epitaxially grown in sequence over a first substrate, and then an insulating layer is formed on the second SiGe layer. Then, impurity ions are implanted into a predetermined location of the first substrate underlying the first SiGe layer to form an impurity implantation region. A second substrate is bonded to the insulating layer on the first substrate. After the first substrate is separated along the impurity implantation region and removed, the first SiGe layer remaining on the surface of the separated region is removed so that the surface of the silicon layer may be exposed.

Abstract: A phase-change memory device in which a phase-change material layer has a multilayered structure with different compositions and a method of fabricating the same are provided. The phase-change memory device includes a first electrode layer formed on a substrate, a heater electrode layer formed on the first electrode layer, an insulating layer formed on the heater electrode layer and having a pore partially exposing the heater electrode layer, a phase-change material layer formed to fill the pore and partially contacting the heater electrode layer, and a second electrode layer formed on the phase-change material layer.

Abstract: A ring shaped heater surrounds a chalcogenide region along the length of a cylindrical solid phase portion thereof defining a change phase memory element. The chalcogenide region is formed in a sub-lithographic pore, so that a relatively compact structure is achieved. Furthermore, the ring contact between the heater and the cylindrical solid phase portion results in a more gradual transition of resistance versus programming current, enabling multilevel memories to be formed.

Abstract: A method for fabricating a semiconductor device, includes forming a porous dielectric film above a substrate using a porous insulating material, forming an opening in the porous dielectric film, repairing film quality of the porous dielectric film on a surface of the opening by feeding a predetermined gas replacing a Si—OH group to the opening, and performing pore sealing of the surface of the opening using the same predetermined gas as that used for film quality repairs after repairing the film quality.

Abstract: A semiconducting material that has all the advantages of prior art SOI substrates including, for example, low parasitic capacitance and leakage, without having floating body effects is provided. More specifically, the present invention provides a Semiconductor-on-Pores (SOP) material that includes a top semiconductor layer and a bottom semiconductor layer, wherein the semiconductor layers are separated in at least one region by a porous semiconductor material. Semiconductor structures including the SOP material as a substrate as well as a method of fabricating the SOP material are also provided. The method includes forming a p-type region with a first semiconductor layer, converting the p-type region to a porous semiconductor material, sealing the upper surface of the porous semiconductor material by annealing, and forming a second semiconductor layer atop the porous semiconductor material.

Abstract: A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.

Abstract: A phase change material including a high adhesion phase change material formed on a dielectric material and a low adhesion phase change material formed on the high adhesion phase change material. The high adhesion phase change material includes a greater amount of at least one of nitrogen and oxygen than the low adhesion phase change material. The phase change material is produced by forming a first chalcogenide compound material including an amount of at least one of nitrogen and oxygen on the dielectric material and forming a second chalcogenide compound including a lower percentage of at least one of nitrogen and oxygen on the first chalcogenide compound material. A phase change random access memory device, and a semiconductor structure are also disclosed.

Abstract: Reactors and methods for miniaturized reactions having enhanced reaction kinetics. In particular the subject matter is directed to chemical and biological reactions conducted in a nanoporous membrane environment. The subject matter contemplates methods for modifying the kinetics of reactions and devices for conducting reactions having modified kinetics. The subject matter also provides systems for rapid miniaturized reactions. Further the subject matter includes methods and kits for conducting a reaction with enhanced throughput and methods of conducting miniaturized, high throughput analyses of reaction products, and the like. Reactions performed on or within a nanoporous membrane exhibits improved kinetic characteristics.

Abstract: In one embodiment, the invention is a method for fabricating an ultra thin silicon on insulator. One embodiment of a method for fabricating an ultra thin silicon on insulator includes providing a silicon layer, saturating the silicon layer with at least one reactant gas at a first temperature, the first temperature being low enough to substantially prevent the occurrence of any reactions involving the reactant gas, and raising the first temperature to a second temperature, the second temperature being approximately a dissociation temperature of the reactant gas.