Total Dielectric Isolation Patents (Class 438/404)
  • Patent number: 10553675
    Abstract: In accordance with an embodiment of an integrated circuit, a cavity is buried in a semiconductor body below a first surface of the semiconductor body. An active area portion of the semiconductor body is arranged between the first surface and the cavity. The integrated circuit further includes a trench isolation structure configured to provide a lateral electric isolation of the active area portion.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: February 4, 2020
    Assignee: Infineon Technologies AG
    Inventors: Sebastian Schmidt, Donald Dibra, Oliver Hellmund, Peter Irsigler, Andreas Meiser, Hans-Joachim Schulze, Martina Seider-Schmidt, Robert Wiesner
  • Patent number: 10446643
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a planar surface and methods of manufacture. The structure includes a cavity formed in a substrate material and which has a curvature at its upper end. The cavity is covered with epitaxial material that has an upper planar surface.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Siva P. Adusumilli, Anthony K. Stamper, Laura J. Schutz, Cameron E. Luce
  • Patent number: 10224449
    Abstract: A photoresistor comprises a silicon-on-insulator substrate (101) comprising a device layer (4). In an example embodiment and mode at least two non-contiguous first highly conductive regions (2, 3) of semiconductor material are formed on a surface of the device layer, and at least one active region (1) of a high resistivity semiconductor material of a same conductivity type as the first highly conductive regions are formed to propagate through a whole thickness of the device layer and to electrically contact the at least two non-contiguous first highly conductive regions.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: March 5, 2019
    Assignee: OSI Optoelectronics, Inc.
    Inventor: Alexander O. Goushcha
  • Patent number: 9985111
    Abstract: A method of forming a semiconductor structure includes forming a shallow trench isolation (STI) feature in a semiconductor substrate. An active region is defined on the semiconductor substrate, wherein the STI feature and the active region have a coplanar surface. A dummy gate is formed on the active region and the STI feature, and an interlayer dielectric layer (ILD) is formed on the semiconductor substrate. The dummy gate is then removed, thereby forming a gate trench in the ILD. The STI feature is selectively etched within the gate trench. A metal gate is formed within the gate trench.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: May 29, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9865462
    Abstract: A strain relaxed buffer layer of a second semiconductor material and of a second lattice constant and containing misfit dislocation defects and threading dislocation defects is formed atop a surface of a first semiconductor material of a first lattice constant that differs from the second lattice constant. The surface of the first semiconductor material includes at least one recessed region and adjoining non-recessed regions. An anneal is then performed on the strain relaxed buffer layer to propagate and amass the misfit dislocation defects and threading dislocation defects at a sidewall of each of the non-recessed regions of the first semiconductor material.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9537011
    Abstract: One embodiment provides a method comprising etching a fin of a fin-shaped field effect transistor (FinFET) to form a reduced fin, and laterally etching the reduced fin to form a fin channel including a first fin channel sidewall and a second fin channel sidewall opposing the first fin channel sidewall. The method further comprises forming a first thin dielectric tunnel and a second thin dielectric tunnel on the first fin channel sidewall and the second fin channel sidewall, respectively. Each thin dielectric tunnel prevents lateral epitaxial crystal growth on the fin channel. The method further comprises etching an insulator layer disposed between the fin channel and a substrate of the FinFET to expose portions of a substrate surface of the substrate. A source epitaxy and a drain epitaxy are formed from vertical epitaxial crystal growth on the exposed portions of the substrate surface after epitaxial deposition.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Johnathan E. Faltermeier, Edward J. Nowak, Kern Rim
  • Patent number: 9401276
    Abstract: An apparatus for forming porous silicon layers on at least two surfaces of a plurality of silicon templates in a batch electrochemical anodic etch process is provided. The apparatus comprises a plurality of edge-sealing template mounts operable to prevent formation of porous silicon at the edges of a plurality of templates. An electrolyte is disposed among the plurality of templates. The apparatus further comprises a power supply operable to switch polarity, change current intensity, and control etching time to produce the porous silicon layers.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: July 26, 2016
    Assignee: Solexel, Inc.
    Inventors: Mehrdad M. Moslehi, Karl-Josef Kramer, David Xuan-Qi Wang, Pawan Kapur, Somnath Nag, George D. Kamian, Jay Ashjaee, Takao Yonehara
  • Patent number: 9312217
    Abstract: The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: April 12, 2016
    Assignee: Silex Microsystems AB
    Inventors: Edvard Kälvesten, Tomas Bauer, Thorbjörn Ebefors
  • Patent number: 9170228
    Abstract: A solid-state field-effect transistor sensor for detecting chemical and biological species and for detecting changes in radiation is disclosed. The device includes a porous or structured channel section to improve device sensitivity. The device is operated in a fully depleted mode such that a sensed biological, chemical or radiation change causes an exponential change in channel conductance.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: October 27, 2015
    Inventor: Bharath R. Takulapalli
  • Publication number: 20150132918
    Abstract: An embodiment radio frequency area of an integrated circuit is disclosed. The radio frequency area includes a substrate having an implant region. The substrate has a first resistance. A buried oxide layer is disposed over the substrate and an interface layer is disposed between the substrate and the buried oxide layer. The interface layer has a second resistance lower than the first resistance. A silicon layer is disposed over the buried oxide layer and an interlevel dielectric is disposed in a deep trench. The deep trench extends through the silicon layer, the buried oxide layer, and the interface layer over the implant region. The deep trench may also extend through a polysilicon layer disposed over the silicon layer.
    Type: Application
    Filed: January 23, 2015
    Publication date: May 14, 2015
    Inventors: Kuo-Yu Cheng, Wei-Kung Tsai, Kuan-Chi Tsai, Tsung-Yu Yang, Chung-Long Chang, Chun-Hong Chen, Chih-Ping Chao, Chen-Yao Tang, Yu Hung Chen
  • Publication number: 20150123231
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 7, 2015
    Inventors: Wei-Ming CHIEN, Po-Han LEE, Tsang-Yu LIU, Yen-Shih HO
  • Patent number: 9023707
    Abstract: Methods of ONO integration into MOS flow are provided. In one embodiment, the method comprises: (i) forming a pad dielectric layer above a MOS device region of a substrate; and (ii) forming a patterned dielectric stack above a non-volatile device region of the substrate, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer, the charge-trapping layer comprising multiple layers including a first nitride layer formed on the tunnel layer and a second nitride layer, wherein the first nitride layer is oxygen rich relative to the second nitride layer. Other embodiments are also described.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 5, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Bo Jin, Fredrick B. Jenne
  • Publication number: 20150102409
    Abstract: A method of isolating a semiconductor fin from an underlying substrate including forming a masking layer around a base portion of the fin, forming spacers on a top portion of the fin above the masking layer, removing the masking layer to expose the base portion of the fin, and converting the base portion of the fin to an isolation region that electrically isolates the fin from the substrate. The base portion of the fin may be converted to an isolation region by oxidizing the base portion of the fin, using for example a thermal oxidation process. While converting the base portion of the fin to an isolation region, the spacers prevent the top portion of the fin from also being converted.
    Type: Application
    Filed: October 10, 2013
    Publication date: April 16, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Shom S. Ponoth, Balasubramanian Pranatharthiharan, Theodorus E. Standaert, Tenko Yamashita
  • Patent number: 9000481
    Abstract: A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: April 7, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Jun Hu, Wayne F. Eng
  • Publication number: 20150091129
    Abstract: An isolation structure can include a structure material with thermal conductivity greater than silicon dioxide, yet electrical conductivity such that the structure material can replace silicon dioxide as an insulator. At least one column can extend to a target layer from a top surface of a semiconductor device near an active area of the device. At least one lateral portion can extend from the column(s) substantially parallel to the target layer and can extend between multiple columns in the target layer, such as in a cavity formed by lateral etching. The structure material can include, for example, aluminum nitride (AlN).
    Type: Application
    Filed: September 30, 2013
    Publication date: April 2, 2015
    Applicant: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Qizhi Liu, Zhenzhen Ye, Yan Zhang
  • Patent number: 8987859
    Abstract: Techniques are disclosed for enhancing the dielectric breakdown performance of integrated circuit (IC) interconnects. The disclosed techniques can be used to selectively etch the dielectric layer of an IC to form a recess, for example, between a given pair of adjacent/neighboring interconnects (e.g., metal lines). Thereafter, a layer of dielectric material of higher dielectric breakdown field (Ec) than the surrounding/underlying dielectric material (or other suitable insulator, as will be apparent in light of this disclosure) may be deposited/grown so as to substantially conform to the topology provided by the adjacent/neighboring interconnects and etched recess. In some cases, this dielectric layer may help to prevent or otherwise reduce: (1) dielectric breakdown between the adjacent/neighboring interconnects by locally increasing the dielectric breakdown voltage (VBD); and/or (2) diffusion of the interconnect fill metal into the surrounding/underlying dielectric material.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: March 24, 2015
    Assignee: Intel Corporation
    Inventors: Pavel S. Plekhanov, Kevin J. Fischer, Qiang Fu, Hiroki Hiramatsu
  • Patent number: 8987108
    Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: March 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, David H. Wells, Tuman E. Allen
  • Publication number: 20150076654
    Abstract: Approaches for providing enlarged fin tips for a set of fins of a fin field effect transistor device (FinFET) are disclosed. Specifically, approaches are provided for patterning a hardmask formed over a substrate; forming a set of fin tips from the substrate using a first etch; and forming a set of fins from the substrate using a second etch, wherein each of the set of fin tips has a width greater than a most narrow section of each of the set of fins. Each of the fin tips has a tapered profile that enlarges towards a top end thereof to compensate for erosion losses during processing.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 19, 2015
    Applicant: GLOBAL FOUNDRIES Inc.
    Inventors: Michael Ganz, Eric S. Kozarsky
  • Publication number: 20150069495
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a first stacked body having a gate insulating film, a first charge storage layer, a first insulating film, a second charge storage layer, and a second insulating film, a second element isolation region, a bottom and at least part of a side portion of the second element isolation region being in contact with the semiconductor substrate in the peripheral portion; and a second stacked body, a third insulating film, a first layer, a fourth insulating film, a second layer, and the second insulating film are stacked in this order from the semiconductor substrate side between the semiconductor substrate and the control gate electrode in the second stacked body in the peripheral portion, a side portion of the second stacked body being covered with the second insulating film.
    Type: Application
    Filed: January 24, 2014
    Publication date: March 12, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenji AOYAMA, Tatsuya OKAMOTO, Hiroki YAMASHITA, Masanari HATTORI
  • Publication number: 20150061014
    Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil JACOB, Murat Kerem AKARVARDAR, Steven John BENTLEY, Bartlomiej Jan PAWLAK
  • Patent number: 8962411
    Abstract: A method of manufacturing a circuit pattern with high aspect ratio is disclosed. A plurality of parallel lines and supporting lines intersecting the parallel lines are formed. Supporting isolation structures are then formed in the space between the parallel lines and the supporting line for supporting the parallel lines in a later etching process. The parallel lines and the supporting line are then disconnected after the etching process.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: February 24, 2015
    Assignee: Nanya Technology Corp.
    Inventors: Chien-An Yu, Yi-Fong Lin
  • Patent number: 8962441
    Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: February 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jerome Ciavatti, Johannes M. van Meer
  • Patent number: 8952421
    Abstract: A compound semiconductor device includes a plurality of high-resistance crystalline silicon epitaxial layers and a plurality of activated dopant regions disposed in a same region of at least some of the epitaxial layers so that the activated dopant regions are aligned in a vertical direction perpendicular to a main surface of the epitaxial layers. The compound semiconductor device further includes an III-nitride compound semiconductor device structure disposed on the main surface of the epitaxial layers. The III-nitride compound semiconductor device structure has a source, a drain and a gate. An electrically conductive structure is formed from the activated dopant regions. The electrically conductive structure extends in the vertical direction through the epitaxial layers with the activated dopant regions toward the III-nitride compound semiconductor device structure, and is electrically connected to the source.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Gianmauro Pozzovivo, Simone Lavanga
  • Publication number: 20150031187
    Abstract: Embodiments of the present invention provide methods to etching a recess channel in a semiconductor substrate, for example, a silicon containing material. In one embodiment, a method of forming a recess structure in a semiconductor substrate includes transferring a silicon substrate into a processing chamber having a patterned photoresist layer disposed thereon exposing a portion of the substrate, providing an etching gas mixture including a halogen containing gas and a Cl2 gas into the processing chamber, supplying a RF source power to form a plasma from the etching gas mixture, supplying a pulsed RF bias power in the etching gas mixture, and etching the portion of the silicon substrate exposed through the patterned photoresist layer in the presence of the plasma.
    Type: Application
    Filed: July 23, 2013
    Publication date: January 29, 2015
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Joo Won Han, Kee Young CHO, Han Sao CHO, Sang Wook KIM, Anisul H. KHAN
  • Publication number: 20150024572
    Abstract: Semiconductor fabrication methods are provided which include facilitating fabricating semiconductor fin structures by: providing a wafer with at least one fin extending above a substrate, the at least one fin including a first layer disposed above a second layer; mechanically stabilizing the first layer; removing at least a portion of the second layer of the fin(s) to create a void below the first layer; filling the void, at least partially, below the first layer with an isolation material to create an isolation layer within the fin(s); and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the fin(s), and a fin device(s) of a second architectural type in a second fin region of the fin(s), where the first architectural type and the second architectural type are different fin device architectures.
    Type: Application
    Filed: July 18, 2013
    Publication date: January 22, 2015
    Inventors: Ajey P. JACOB, Kangguo CHENG, Bruce B. DORIS, Nicolas LOUBET, Prasanna KHARE, Ramachandra DIVAKARUNI
  • Patent number: 8916950
    Abstract: A semiconductor structure and method for forming a shallow trench isolation (STI) structure having one or more oxide layers and a nitride plug. Specifically, the structure and method involves forming one or more trenches in a substrate. The STI structure is formed having one or more oxide layers and a nitride plug, wherein the STI structure is formed on and adjacent to at least one of the one or more trenches. One or more gates are formed on the substrate and spaced at a distance from each other. A dielectric layer is formed on and adjacent to the substrate, the STI structure, and the one or more gates.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventors: Byeong Y. Kim, Shreesh Narasimha
  • Publication number: 20140363949
    Abstract: Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer.
    Type: Application
    Filed: August 21, 2014
    Publication date: December 11, 2014
    Inventors: Paul D. Hurwitz, Robert L. Zwingman
  • Patent number: 8906771
    Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Mikhalev, Jim Fulford, Yongjun Jeff Hu, Gordon A. Haller, Lequn Liu
  • Patent number: 8907423
    Abstract: A high withstand voltage transistor is formed in a high withstand voltage region, and a low withstand voltage transistor is formed in a low withstand voltage region in a method of manufacturing a semiconductor device. The method includes forming a thermal oxide film and a silicon nitride film over the surface of a silicon substrate; forming an opening to the thermal oxide film and the silicon nitride film in each of the high withstand voltage region and the low withstand voltage region; etching the silicon substrate to form trenches; burying a buried oxide film in each of the trenches; removing the thermal oxide film and the silicon nitride film; and forming a thick gate oxide film and a thin oxide film. The depth of a tapered portion of the trench in the low withstand voltage region is shallower than that in the high withstand voltage region.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Tadahiro Miwatashi
  • Patent number: 8877600
    Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: November 4, 2014
    Assignees: STMicroelectronics, Inc., STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS, Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Claire Fenouillet-Beranger, Stephane Denorme, Nicolas Loubet, Qing Liu, Emmanuel Richard, Pierre Perreau
  • Patent number: 8835277
    Abstract: A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: September 16, 2014
    Assignee: Spansion LLC
    Inventors: Tung-Sheng Chen, Shenqing Fang
  • Patent number: 8835278
    Abstract: Disclosed are methods for forming a localized buried dielectric layer under a fin for use in a semiconductor device. In some embodiments, the method may include providing a substrate comprising a bulk semiconductor material and forming at least two trenches in the substrate, thereby forming at least one fin. The method further includes filling the trenches with an insulating material and partially removing the insulating material to form an insulating region at the bottom of each of the trenches. The method further includes depositing a liner at least on the sidewalls of the trenches, removing a layer from a top of each of the insulating regions to thereby form a window opening at the bottom region of the fin, and transforming the bulk semiconductor material of the bottom region of the fin via the window opening, thereby forming a localized buried dielectric layer in the bottom region of the fin.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: September 16, 2014
    Assignee: IMEC
    Inventors: Gouri Sankar Kar, Antonino Cacciato, Min-Soo Kim
  • Patent number: 8822300
    Abstract: A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: September 2, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Jun Hu, Wayne F. Eng
  • Patent number: 8816470
    Abstract: A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: August 26, 2014
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Patent number: 8794501
    Abstract: A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. The micro LED structure may include a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer. A conformal dielectric barrier layer may span sidewalls of the micro p-n diode. The micro LED structure and micro LED array may be picked up and transferred to a receiving substrate.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: August 5, 2014
    Assignee: LuxVue Technology Corporation
    Inventors: Andreas Bibl, John A. Higginson, Hung-Fai Stephen Law, Hsin-Hua Hu
  • Patent number: 8785306
    Abstract: A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: July 22, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla, Yeeheng Lee, John Chen, Moses Ho
  • Patent number: 8759942
    Abstract: The present invention provides semiconductor devices and methods for fabricating the same, in which superior dielectric termination of drift regions is accomplished by a plurality of intersecting trenches with intermediate semiconductor islands. Thus, a deep trench arrangement can be achieved without being restricted by the overall width of the isolation structure.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: June 24, 2014
    Assignee: X-FAB Semiconductor Foundries AG
    Inventors: Alexander Hoelke, Deb Kumar Pal, Pei Shan Chua, Gopalakrishnan Kulathu Sankar, Kia Yaw Kee, Yang Hao, Uta Kuniss
  • Patent number: 8748204
    Abstract: Isolation of III-nitride devices may be performed with a dopant selective etch that provides a smooth profile with little crystal damage in comparison to previously used isolation techniques. The dopant selective etch may be an electro-chemical or photo-electro-chemical etch. The desired isolation area may be identified by changing the conductivity type of the semiconductor material to be etched. The etch process can remove a conductive layer to isolate a device atop the conductive layer. The etch process can be self stopping, where the process automatically terminates when the selectively doped semiconductor material is removed.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: June 10, 2014
    Assignee: International Rectifier Corporation
    Inventor: Paul Bridger
  • Patent number: 8741741
    Abstract: A method for manufacturing an SOI wafer that has an SOI layer formed on a buried insulator layer and is suitable for photolithography with an exposure light having a wavelength ? comprises: designing a thickness of the buried insulator layer of the SOI wafer on the basis of the wavelength ? of the exposure light utilized for the photolithography that is to be performed on the SOI wafer after manufacturing; and fabricating the SOI wafer that has the SOI layer formed on the buried insulator layer having the designed thickness. As a result, there is provided a method for designing an SOI wafer and a method for manufacturing an SOI wafer that enable the variation in the reflection rate of the exposure light due to the variation in the SOI layer thickness and hence variation in the exposure state of a resist to be inhibited in a photolithography operation.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: June 3, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Susumu Kuwabara
  • Patent number: 8741734
    Abstract: A semiconductor device includes a semiconductor substrate having a trench defining an active region. A wall oxide is formed on side walls of the active region extending in the longitudinal direction, and an element isolation layer is formed in the trenches. A method of manufacturing a semiconductor device includes forming line-shape first trenches on a semiconductor substrate so as to define an active region; forming a wall oxide on surfaces of the first trenches; forming a second trench which separates the active region into a plurality of active regions; and filling the trenches with an element isolation layer.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: June 3, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Bum Kim
  • Publication number: 20140141591
    Abstract: A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.
    Type: Application
    Filed: November 19, 2012
    Publication date: May 22, 2014
    Applicant: Spansion LLC
    Inventors: Tung-Sheng CHEN, Shenqing Fang
  • Patent number: 8709903
    Abstract: Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Botula, John J. Ellis-Monaghan, Alvin J. Joseph, Max G. Levy, Richard A. Phelps, James A. Slinkman, Randy L. Wolf
  • Patent number: 8703575
    Abstract: The instant disclosure relates to a method of forming an isolation area. The method includes the steps of: providing a substrate having a first type of ion dopants, where the substrate has a plurality of trenches formed on the cell areas and the isolation area between the cell areas of the substrate, with the side walls of the trenches having an oxidation layer formed thereon and the trenches are filled with a metallic structure; removing the metallic structure from the trenches of the isolation area; implanting a second type of ions into the substrate under the trenches of the isolation area; and filling all the trenches with an insulating structure, where the trenches of the isolation area are filled up fully by the insulating structure to form a non-metallic isolation area.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: April 22, 2014
    Assignee: Inotera Memories, Inc.
    Inventors: Tzung-Han Lee, Chung-Lin Huang, Ron Fu Chu
  • Patent number: 8692266
    Abstract: A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: April 8, 2014
    Assignee: Optromax Electronics Co., Ltd
    Inventor: Kuo-Tso Chen
  • Publication number: 20140091381
    Abstract: Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be provided to prevent the collapse of closely spaced device structures during fabrication. In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be set in place prior to performing a high aspect ratio word line etch for forming the NAND strings. The one or more mechanical support structures may comprise one or more fin supports that are arranged in a bit line direction. In another example, the one or more mechanical support structures may be developed during the word line etch for forming the NAND strings.
    Type: Application
    Filed: October 3, 2012
    Publication date: April 3, 2014
    Applicant: SANDISK 3D, LLC
    Inventor: Donovan Lee
  • Patent number: 8685830
    Abstract: A method of filling shallow trenches is disclosed. The method includes: successively forming a first oxide layer and a second oxide layer over the surface of a silicon substrate where shallow trenches are formed in; etching the second oxide layer to form inner sidewalls with an etchant which has a high etching selectivity ratio of the second oxide layer to the first oxide layer; growing a high-quality pad oxide layer by thermal oxidation after the inner sidewalls are removed; and filling the trenches with an isolation dielectric material. By using this method, the risk of occurrence of junction spiking and electrical leakage during a subsequent process of forming a metal silicide can be reduced.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: April 1, 2014
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Fan Chen, Xiongbin Chen, Kai Xue, Keran Zhou, Jia Pan, Hao Li, Yongcheng Wang
  • Patent number: 8673731
    Abstract: Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.
    Type: Grant
    Filed: August 20, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight
  • Publication number: 20140054698
    Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicant: STMicroelectronics, Inc.
    Inventors: Qing Liu, Nicolas Loubet, Prasanna Khare
  • Publication number: 20140054699
    Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.
    Type: Application
    Filed: August 21, 2012
    Publication date: February 27, 2014
    Applicants: STMicroelectronics, Inc., COMMISSARIATE A ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: QING LIU, PRASANNA KHARE, NICOLAS LOUBET, SHOM PONOTH, MAUD VINET, BRUCE DORIS
  • Publication number: 20140051225
    Abstract: Techniques for gate workfunction engineering using a workfunction setting material to reduce short channel effects in planar CMOS devices are provided. In one aspect, a method of fabricating a CMOS device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. A patterned dielectric is formed on the wafer having trenches therein present over active areas in which a gate stack will be formed. Into each of the trenches depositing: (i) a conformal gate dielectric (ii) a conformal gate metal layer and (iii) a conformal workfunction setting metal layer. A volume of the conformal gate metal layer and/or a volume of the conformal workfunction setting metal layer deposited into a given one of the trenches are/is proportional to a length of the gate stack being formed in the given trench. A CMOS device is also provided.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Isaac Lauer, Chung-Hsun Lin, Jeffrey W. Sleight