Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.

Abstract: A method of manufacturing a semiconductor light emitting device includes: forming an active layer of an aluminum gallium nitride (AlGaN)-based semiconductor material on an n-type clad layer of an n-type AlGaN-based semiconductor material; forming a p-type semiconductor layer on the active layer; removing portions of the p-type semiconductor layer, the active layer, and the n-type clad layer so as to expose a partial region of the n-type clad layer; and forming an n-side electrode on the partial region of the n-type clad layer exposed. The removing includes first dry-etching performed by using both a reactive gas and an inert gas and second dry-etching performed after the first dry-etching by using a reactive gas.

Abstract: Disclosed is a semiconductor device manufacturing method comprising: forming an element isolation region in one principal face of a semiconductor substrate of one conductivity type; forming a gate electrode extending from an element region to the element isolation region at both sides of the element region in a first direction, both end portions of the gate electrode in the first direction being on the element isolation region and respectively including a concave portion and protruding portions at both sides of the concave portion; carrying out ion implantation of impurities of the one conductivity type from a direction tilted from a direction perpendicular to the one principal face toward the first direction so that first and second impurity implantation regions of the one conductivity type are formed in the one principal face in two end regions of the element region in the first direction.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having first and second regions; a first transistor comprising a first gate insulating film and a first gate electrode thereon in the first region on the semiconductor substrate, the first gate insulating film comprising a first interface layer containing nitrogen atoms and a first high dielectric constant layer thereon; a second transistor comprising a second gate insulating film and a second gate electrode thereon in the second region on the semiconductor substrate, the second gate insulating film comprising a second interface layer and a second high dielectric constant layer thereon, the second interface layer containing nitrogen atoms at an average concentration lower than that of the first interface layer or not containing nitrogen atoms, and the second transistor having a threshold voltage different from that of the first transistor; and an element isolation region on the semiconductor substrate, the element isolation

Abstract: A focus ring is shaped by cutting off a silicon carbide body formed by a sintering method or a CVD method. The shaped focus ring is exposed to a plasma generated from at least one of a carbon tetra fluoride gas and an oxygen gas for producing impurities, and the impurities are introduced to void-like defects existing in the vicinity of a surface of the focus ring. Subsequently, positrons are injected in the vicinity of the surface of the focus ring into which the impurities are introduced, and the defect density in the vicinity of the surface of the focus ring is detected by the positron annihilation method.

Abstract: Conductive through vias are formed in electronic devices and electronic device carrier, such as, a silicon chip carrier. An annulus cavity is etched into the silicon carrier from the top side of the carrier and the cavity is filled with insulating material to form an isolation collar around a silicon core region. An insulating layer with at least one wiring level, having a portion in contact with the silicon core region, is formed on the top side of the carrier. Silicon is removed from the back side of the carrier sufficient to expose the distal portion of the isolation collar. The core region is etched out to expose the portion of the wiring level in contact with the silicon core region to form an empty via. The via is filled with conductive material in contact with the exposed portion of the wiring level to form a conductive through via to the wiring level. A solder bump formed, for example, from low melt C4 solder, is formed on the conductive via exposed on the carrier back side.

Abstract: A semiconductor device may include a semiconductor substrate having a surface, a shallow trench isolation (STI) region in the semiconductor substrate and extending above the surface thereof, and a superlattice layer adjacent the surface of the semiconductor substrate and comprising a plurality of stacked groups of layers. More particularly, each group of layers of the superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, at least some atoms from opposing base semiconductor portions may be chemically bound together with the chemical bonds traversing the at least one intervening non-semiconductor monolayer.

Abstract: A semiconductor device suitable for a source-follower circuit, provided with a gate electrode formed on a semiconductor substrate via a gate insulation film, a first conductivity type layer formed in the semiconductor substrate under a conductive portion of the gate electrode and containing a first conductivity type impurity, first source/drain regions of the first conductivity type impurity formed in the semiconductor substrate and extended from edge portions of the gate electrode, and second source/drain regions having a first conductivity type impurity concentration lower than that in the first source/drain regions and formed adjoining the gate insulation film and the first source/drain regions in the semiconductor substrate so as to overlap portions of the conductive portion of the gate electrode.

Abstract: A method of forming a silicon germanium conduction channel under a gate stack of a semiconductor device, the gate stack being formed on a silicon layer on an insulating layer, the method including growing a silicon germanium layer over said silicon layer and heating the device such that germanium condenses in the silicon layer such that a silicon germanium channel is formed between the gate stack and the insulating layer.

Abstract: A method for fabricating a semiconductor element on a semiconductor substrate having a support substrate and a semiconductor layer above the support substrate. The method includes preparing the semiconductor substrate having a transistor formation region and an element isolation region both defined thereon; forming a pad oxide film on the semiconductor layer of the semiconductor substrate; forming an oxidation-resistant mask layer on the pad oxide film; forming a resist mask to cover the transistor formation region on the oxidation-resistant mask layer; performing a first etching process for etching the oxidation-resistant mask layer using the resist mask as a mask to expose the pad oxide film of the element isolation region; and removing the resist mask and oxidizing the semiconductor layer below the exposed pad oxide film by LOCOS using the exposed oxidation-resistant mask layer as a mask to form an element isolation layer.

Abstract: Alloys of silver and an alloying element that diffuses to the surface of the high conductivity metal and is oxidizable to form an alloying element oxide such as beryllium are provided along with electronic structures employing the alloys and methods of fabrication.

Abstract: The present invention provides a method of forming a thin channel MOSFET having low external resistance. The method comprises forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.

Abstract: A method of fabricating a semiconductor device including gate dielectrics having different thicknesses may be provided. A method of fabricating a semiconductor device may include providing a substrate having a higher voltage device region and a lower voltage device region, forming an anti-oxidation layer on the substrate, and selectively removing portions of the anti-oxidation layer on the substrate. The method may also include performing a first thermal oxidization on the substrate to form a field oxide layer on the selectively removed portions of the anti-oxidation layer, removing the anti-oxidation layer disposed on the higher voltage device region, performing a second thermal oxidization on the substrate to form a central higher voltage gate oxide layer on the higher voltage device region, removing the anti-oxidation layer disposed on the lower voltage device region, and performing a third thermal oxidization on the substrate to form a lower voltage gate oxide layer on the lower voltage device region.

Abstract: Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.

Abstract: A method for manufacturing a semiconductor device includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a semiconductor substrate; forming a first groove penetrating the first semiconductor layer and the second semiconductor layer by partially etching the first semiconductor layer and the second semiconductor layer; forming a support covering the second semiconductor layer from inside of the first groove to a surface of the second semiconductor layer so as to support the second semiconductor layer; etching a sidewall formed in the first groove of the support so as to render the sidewall thin; forming a second groove exposing the first semiconductor layer by sequentially etching a part of the second semiconductor layer and a part of the first semiconductor layer; forming a cavity between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer through the second groove under an etching condition in which the first semicondu

Abstract: The invention provides soybean plants having a novel determinant, Rps8, for resistance to Phytophthora sojae. The invention also provides methods for identifying germplasms that are either heterozygous or homozygous for Rps8 using marker assisted selection. Genetic and enzymatic markers with known chromosomal loci that are associated with the Rps8 locus are used to confirm Rps8-derived Phytophthora sojae resistance in germplasms. Marker assisted selection also used when introgressing Rps8-derived soybean Phytophthora sojae resistance into non-resistant soybean germplasm or less resistant soybean germplasms.

Abstract: Methods for improving the mechanical properties of a CDO film are provided. The methods involve, for instance, providing either a dense CDO film or a porous CDO film in which the porogen has been removed followed by curing the CDO film at an elevated temperature using either a UV light treatment, an e-beam treatment, or a plasma treatment such that the curing improves the mechanical toughness of the CDO dielectric film.

Abstract: A method and apparatus for providing integrated active regions on silicon-on-insulator (SOI) devices by oxidizing a portion of the active layer. When the active layer of the SOI wafer is relatively thick, such as about 200 ? to 1000 ? or greater, the etching process partially removes the active layer. The remaining active layer is oxidized prior to a wet dip for removing the mask layer, preventing the wet dip process from undercutting the active region. When the active layer of the SOI wafer is relatively thin, such as about 25 ? to 400 ?, the partial etching step may be reduced or eliminated. In this case, the active layer is oxidized with little or no etching of the active layer. The exposed active layer is oxidized to prevent the wet dip process from undercutting the active region.

Abstract: A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A thermal oxidation completes the vertical isolation by use of a minifield oxidation process. The recess is filled to form a shallow trench isolation structure. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

Abstract: Methods for improving the mechanical properties of a CDO film are provided. The methods involve, for instance, providing either a dense CDO film or a porous CDO film in which the porogen has been removed followed by curing the CDO film at an elevated temperature using either a UV light treatment, an e-beam treatment, or a plasma treatment such that the curing improves the mechanical toughness of the CDO dielectric film.

Abstract: In a FinFET integrated circuit, the fins are formed with a reduced body thickness in the body area and then thickened in the S/D area outside the body to improve conductivity. The thickening is performed with epitaxial deposition while the lower portion of the gates are covered by a gate cover layer to prevent thickening of the gates at the fin level, which may short the gate to the S/D.

Abstract: A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually adjacent trenches, open on a first face of the wafer, which have a depth and a width and define walls); by thermal oxidation, completely oxidizing the walls and filling at least partially the first trenches, so as to form an insulating structure of dielectric material; and removing one portion of the substrate comprised between the insulating structure and a second face of the wafer, opposite to the first face of the wafer.

Abstract: An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.

Abstract: An object of the present invention is to provide a method for manufacturing a capacitor structure that makes it possible to control the accumulation of electric charges on a top electrode film as a factor that brings about electrostatic breakdown in the insulating film of an MIM capacitor structure, and to provide a method for manufacturing capacitor elements with a low percent defective. The first technique is characterized in that a top electrode film is formed on a substrate after a grounded conductive member is brought into contact with a bottom electrode film or insulating film, and the conductive member is then separated from the bottom electrode film or insulating film. The second technique is characterized in that a top electrode film is formed on a substrate in a state in which a member kept at a negative potential is disposed around the substrate.

Abstract: An electronic power device is integrated monolithically in a semiconductor substrate. The device has a first power region and a second region, each region including P/N junction formed of a first semiconductor region with a first type of conductivity, which first semiconductor region extends through the substrate from the top surface of the device and is diffused into a second semiconductor region with the opposite conductivity from the first. The device also includes an interface structure between the two regions, of substantial thickness and limited planar size, that includes a trench filled with dielectric material. A method of manufacturing the electronic power device includes forming a silicon oxide-filled trench. The method includes forming, in the substrate, a plurality of small trenches having predetermined widths and -being delimited by a corresponding plurality of semiconductor material walls having second predetermined widths.

Abstract: A method for filling narrow isolation trenches during a semiconductor fabrication process is disclosed. The semiconductor includes both high-aspect ratio narrow isolation trenches formed in a core area of a substrate, and wide isolation trenches formed in a circuit area of the substrate. After trench formation, a thick liner oxidation is performed in all of the isolation trenches in which a layer of thermal oxide is grown to a thickness sufficient to completely fill the high-aspect ratio narrow isolation trenches. Subsequent to the liner oxidation, the wide isolation trenches are filled with an isolation dielectric, whereby all of the trenches are uniformly filled with minimal voids.

Abstract: A Silicon On Insulator (SOI) structure and method of producing an SOI structure that can prevent a short circuit between a Local Inter-Connect (LIC) and a well in the SOI structure is disclosed. The SOI structure includes a BOX layer of insulation material formed on a silicon substrate; an SOI layer formed on the BOX layer; a well formed within a device isolation area of the SOI layer such that its lower surface is in contact with the BOX layer; a field oxide film formed on a surface side within the well; a gate line formed across an active area on the SOI layer and a portion on the field oxide film; an N+ type source/drain area formed within the active area along both sides of the gate line to contact its lower surface with the BOX layer; an insulation layer formed on such resultant structure; and an opening part that is formed within the insulation layer.

Abstract: The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while providing improved wafer to wafer device uniformity. Specifically, the method facilitates the formation of finFET devices from bulk semiconductor wafers with improved fin height control. Additionally, the method provides the ability to form finFETs from bulk semiconductor while providing isolation between fins and between the source and drain region of individual finFETs. Finally, the method can also provide for the optimization of fin width. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

Abstract: A method for estimating molecular nitrogen implantation dosage. The semiconductor wafers are first implanted with various concentration of molecular nitrogen. After implantation, the implanted wafers and a non-implanted wafer are subjected to thermal process to grow oxide layer. The thickness of oxide layer on the wafers with various implantation dosage is measured. Because implanted nitrogen on the wafers suppresses the growth of oxide layer, a suppression ratio is computed from the difference in thickness of the oxide layer between the implanted and non-implanted semiconductor wafers to stand for the thickness variation. Then, a relation between the suppression ratio and the dosages of molecular nitrogen is built. A molecular nitrogen dosage needed to grow a predetermined thickness of oxide layer on a process wafer is computed by inputting the predetermined thickness into the relation.

Abstract: A method for forming an isolation structure (22) on a SOI substrate (11) is provided. A three layer stack of an etchant barrier layer (16), a stress relief layer (17), and an oxide mask layer (18) is formed on the SOI substrate (11). The three layer stack is patterned and etched to expose portions of the etchant barrier layer (16). The silicon layer (13) below the exposed portions of the etchant barrier layer (16) is oxidized to form the isolation structure (22). The isolation structure (22) comprises a bird's head region (21) with a small encroachment which results in higher edge threshold voltage. The method requires minimum over-oxidation and provides for an isolation structure (22) that leaves the SOI substrate (11) planar. Minimal over-oxidation reduces the number of dislocations formed during the oxidation process and improves the source to drain leakage of the device.

Abstract: In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.

Abstract: A method of forming an isolated structure of sufficient size to permit the fabrication of an active device thereon is comprised of the steps of depositing a gate oxide layer on a substrate. Material, such as a polysilicon layer and a nitride layer, is deposited on the gate oxide layer to protect the gate oxide layer. An active area is defined, typically by patterning a layer of photoresist. The protective material, the layer of oxide, and finally the substrate are etched to form a trench around the active area. Spacers are formed on the sides of the active area. The substrate is etched to deepen the trench around the active area to a point below the spacers. The substrate is oxidized at the bottom of the trench and horizontally under the active area to at least partially isolate the active area from the substrate. Oxide spacers are formed on the sides of the active area to fill exposed curved oxide regions and the remainder of the trench may be filled with an oxide.

Abstract: The invention utilizes introductions of oxygen and hydroxyl to perform an in situ steam generated process to reoxidize a conventional sidewall oxide layer and density the oxide in a shallow trench isolation. The ISSG process renders the conventional sidewall oxide layer much less stress and encroachment. The electrical property of the active regions and the isolation quality between the active regions can be assured. The ISSG process can densify the oxide in a shallow trench isolation to prevent the oxide from being lost in the following clean process.

Abstract: In a combined isolation oxide film (BT1), a part closer to a gate electrode (GT13) reaches a buried oxide film (2) through an SOI layer (3) while a part closer to another gate electrode (GT12) has a sectional shape provided with a well region on its lower portion. The shape of an edge portion of the combined isolation oxide film (BT1) is in the form of a bird's beak in a LOCOS isolation oxide film. Consequently, the thicknesses of portions defining edge portions of the gate oxide films (GO12, GO13) are locally increased. Thus provided are a semiconductor device including a MOS transistor having a gate oxide film prevented from dielectric breakdown without increasing its thickness and a method of manufacturing the same.

Abstract: A wafer stage having a built-in heater therein mounts a heat conductive disk which mounts thereon an object wafer having an AlAs layer therein. The heat conductive disk has a thermal conductivity equal to or higher than 100 watts/K/meter. The Al-oxidized area in the AlAs layer has excellent in-plane uniformity for the width thereof due to desirable heat distribution of the wafer caused by the heat conductive disk.

Abstract: A method of wafer reclaim, at least includes: provide a wafer; perform a first semiconductor process to let both film layer and numerous particles are formed on the wafer; perform chemical mechanical polishing process to let part of film layer is removed and scales of part of particles are decreased; perform wet etching process to let both residual film layer and residual particles are further removed; perform cleaning process to let surface of wafer is cleaned; and perform second semiconductor process to let a semiconductor structure is formed on wafer. Furthermore, concepts of the invention that both film layer and particles are thoroughly removed by both chemical mechanical polishing process and wet etching process can be applied as a method for cleaning wafer and a method for planarizing wafer.

Abstract: A method for manufacturing a GaN-based semiconductor device in which an ohmic contact can be provided between the semiconductor layer and the electrode material. In a method for manufacturing wherein an n-GaN layer, an emissive layer, a p-GaN layer are formed on a substrate in that order; etching is performed to expose a portion of the n-GaN layer; and a negative electrode is formed on the n-GaN layer, the etching is performed in two sub-steps, an etching step using BCl3 gas and an etching step using Cl2 gas. The surface of the n-GaN layer is exposed in the first sub-step and the B (boron) contamination layer is removed in the second sub-step.

Abstract: A method for fabricating a semiconductor device which can improve the operational characteristics of the device by preventing the deactivation of dopants caused by a supplementary thermal treatment. The method for fabricating a semiconductor includes: defining an active region by forming a device isolation layer on a semiconductor substrate; forming a gate electrode in the active region and forming a LDD region on the surface of the substrate at both sides of the gate electrode; forming a gate sidewall at the sides of the gate electrode and forming a silicide layer on the top surface of the gate electrode and the exposed surface of the substrate; implanting impurity ions for forming a source/drain by using the gate electrode as a mask; and activating the impurity ions for forming a source/drain by annealing after forming first and second dielectric layers on the whole surface of the substrate.

Abstract: A method of manufacturing an SOI (silicon on insulator) wafer includes the step of selective anisotropic etching to form, in the substrate, trenches which extend to a predetermined depth from a major surface of the substrate and between which pillar portions of the substrate are defined. The method further includes the step of selective isotropic etching to enlarge the trenches, starting at a predetermined distance from the major surface, thus reducing the thicknesses of the pillar portions of the substrate between adjacent trenches. Also, the method includes the steps of selective oxidation to convert the pillar portions of reduced thickness of the substrate into silicon dioxide and to fill the trenches with silicon dioxide, starting substantially from the predetermined distance, and epitaxial growth of a silicon layer on the major surface of the substrate.

Abstract: A manufacturing process is carried out starting from an SOI type wafer including a top silicon layer and a bottom silicon layer separated from each other by a buried silicon dioxide layer. In the top layer, a LOCOS type sacrificial region is formed and then removed, so as to form a cavity that extends in depth as far as the buried oxide layer. Subsequently, the cavity is filled with epitaxial or polycrystalline silicon, so as to form a power region extending between the top surface and the bottom surface of the wafer; then lateral insulation regions are formed that insulate the power region from the circuitry region.

Abstract: An oxynitride film on the surface of a silicon or silicon germanium substrate is described where film is substantially an oxide film at the film oxide interface, and the nitrogen content of the film increases with the distance away from the substrate. The film is made by a process of rapidly processing a clean silicon wafer in an atmosphere of a nitrogen containing gas containing a very small percentage of oxygen containing gas.

Abstract: A method for making contact with a covered semiconductor layer through a contact hole, includes producing a contact hole in an insulator layer for making contact with at least one covered semiconductor layer. A heavily doped polysilicon layer is produced on the surface of the insulator layer and the contact hole is at least partially filled with heavily doped polysilicon. A metal layer is applied on the heavily doped polysilicon layer for establishing an ohmic connection to the outside. A semiconductor component fabricated according to the method is also provided.

Abstract: A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.

Abstract: In producing a thin film transistor, after an amorphous silicon film is formed on a substrate, a nickel silicide layer is formed by spin coating with a solution (nickel acetate solution) containing nickel as the metal element which accelerates (promotes) the crystallization of silicon and by heat treating. The nickel silicide layer is selectively patterned to form island-like nickel silicide layer. The amorphous silicon film is patterned. A laser light is irradiated while moving the laser, so that crystal growth occurs from the region in which the nickel silicide layer is formed and a region equivalent to a single crystal (a monodomain region) is obtained.

Abstract: A method of forming a semiconductor device includes forming a moat stack outwardly from a substrate, the moat stack comprising a dielectric pad disposed outwardly from the substrate, a silicon buffer structure disposed outwardly from the dielectric pad, and a protective dielectric cap disposed outwardly from the silicon buffer structure. The method further comprises forming a protective sidewall structure outwardly from at least a sidewall of the silicon buffer structure, forming an isolation dielectric region adjacent to the moat stack, after formation of the isolation dielectric region, removing the protective dielectric cap, and forming a conductive gate comprising the silicon buffer structure.

Abstract: A method of fabricating a semiconductor device and the device which includes initially providing a layer of silicon having a thin oxide layer thereon and a patterned layer of a masking material not permeable to at least selected oxygen-bearing species and having a sidewall disposed over said oxide layer to provide an exposed intersection of the masking material and the oxide layer. An oxygen-bearing species conductive path is then formed on the sidewall of the masking material extending to the exposed intersection for conducting the selected oxygen-bearing species. A sidewall layer of a material different from the conductive path is formed on the conductive path. An oxygen-bearing species is then applied to the exposed intersection through the path and a thick oxide surrounding the masking material is fabricated concurrently or as a separate step. The masking material is preferably silicon nitride, the path is preferably silicon oxide and the sidewall layer is preferably silicon nitride.

Abstract: In the method for the aligned joining of wafers (8, 11), the wafers (8, 11) are adjusted to a parallel position of their sides facing towards each other, are aligned according to alignment marks provided on these sides, and are then joined in a processing station (1). Both wafers (8, 11) are mounted on substrate carriers (5, 10), of which the one can be moved in only one direction from the processing station (1) into a measuring station (2), whereas the other one can in addition be adjusted in two further coordinate directions and can slightly be rotated about a vertical axis. In the measuring station there are provided microscope units with coaxial lenses (26, 27) facing towards each other. Upon introducing the first wafer (8), the microscope units are adjusted to its alignment marks.

Abstract: Silicon-on-insulator (SOI) islands are formed in a silicon substrate. A first set of trenches formed in the silicon substrate, leaving laterally-isolated rows of silicon between the trenches. The first set of trenches is then filled with silicon oxide. A second set of trenches is then formed in the silicon substrate at a direction orthogonal to the first set of trenches. Silicon nitride is then deposited over the sidewalls of the second set of trenches. An isotropic chemical etch is then used to fully undercut narrow the laterally-isolated rows of silicon between the second set of trenches to form evacuated regions beneath silicon islands. A subsequent oxidation step fills the evacuated regions to form de SOI islands.

Abstract: Using sub-micron technology, silicon on insulator (SOI) rows and islands are formed in a silicon substrate. Trenches are directionally-etched in the silicon substrate, leaving rows of silicon between the trenches. Silicon nitride is then deposited over the trenches, extending partly down the sides of the trenches. An isotropic chemical etch is then used to partially undercut narrow rows of silicon in the substrate. A subsequent oxidation step fully undercuts the rows of silicon, isolating the silicon rows from adjacent active areas. Devices, such as transistors for CMOS and DRAMs, are then formed in active areas, wherein the active areas are defined on the silicon rows by LOCal Oxidation of Silicon (LOCOS).

Abstract: A field oxide film which is fine and having smaller upheaval of a bird's head is formed, so as to improve electrical characteristic of a conductive layer formed with end portions positioned on the field oxide film. A planarizing silicon film is formed on a silicon nitride film and a thermal oxide film, so as to planarize a concave generated between the thermal oxide film and a silicon nitride film. The planarizing silicon film is thermally oxidized, so as to form a planarizing thermal oxide film integrated with the thermal oxide film. Thereafter, the planarizing thermal oxide film is etched back to form the field oxide film, and the silicon nitride film and a polycrystalline silicon film are removed. Thereafter, the conductive layer with end portions positioned on the field oxide film is formed.