Refilling Multiple Grooves Of Different Widths Or Depths Patents (Class 438/427)
  • Patent number: 11908732
    Abstract: A method of forming a pitch pattern is provided. The method includes forming two adjacent mandrels separated by a first distance, D1, on a substrate, and forming a first set of alternating sidewall spacers between the two adjacent mandrels. The method further includes removing the two adjacent mandrels, and forming a second set of alternating sidewall spacers and a third set of alternating sidewall spacers on opposite sides of the first set of sidewall spacers.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: February 20, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, Chanro Park, Koichi Motoyama
  • Patent number: 11769691
    Abstract: The method includes providing a to-be-etched layer including an first region and a second region adjoining the first region, forming a first mask layer on the to-be-etched layer, forming a patterned core layer on the first mask layer of the first region, forming a sidewall spacer on the core layer and the first mask layer, forming a first sacrificial layer on the sidewall spacer on the surface of the first mask layer of the second region, forming a second sacrificial layer on the sidewall spacer, removing the first sacrificial layer, the sidewall spacer on the surface of the first mask layer of the second region, and the sidewall spacer on a top of the core layer, removing the core layer, etching the first mask layer of the first region to form a first trench, and etching the first mask layer of the second region to form a second trench.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: September 26, 2023
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Jisong Jin, Abraham Yoo
  • Patent number: 11699694
    Abstract: Methods of manufacturing a semiconductor package structure are provided. A method includes: bonding dies and dummy dies to a wafer; forming a dielectric material layer on the wafer to cover the dies and the dummy dies; performing a first planarization process to remove a first portion of the dielectric material layer over top surfaces of the dies and the dummy dies; and performing a second planarization process to remove portions of the dies, portions of the dummy dies and a second portion of the dielectric material layer, and a dielectric layer is formed laterally aside the dies and the dummy dies; wherein after the second planarization process is performed, a total thickness variation of the dies is less than a total thickness variation of the dummy dies.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: July 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Hsiu Chen, Chen-Hua Yu, Ming-Fa Chen, Wen-Chih Chiou
  • Patent number: 11646238
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device with fin structures having different top surface crystal orientations and/or different materials. The present disclosure provides a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and with fin structures having different materials. The present disclosure provides a method to fabricate a semiconductor structure including n-type FinFET devices and p-type FinFET devices with different top surface crystal orientations and different materials to achieve optimized electron transport and hole transport. The present disclosure also provides a diode structure and a bipolar junction transistor structure that includes SiGe in the fin structures.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Chiang, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 11239089
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first isolation feature in a peripheral region of a substrate; recessing the cell region of the substrate after forming the first isolation feature; forming a second isolation feature in a cell region of the substrate after recessing the cell region of the substrate; forming a plurality of control gates over the cell region of the substrate; and forming a gate stack over the peripheral region of the substrate.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Chih-Ren Hsieh, Chih-Pin Huang, Ching-Wen Chan
  • Patent number: 11205697
    Abstract: Provided is a shallow trench isolating structure and a semiconductor device. The trench isolating structure is formed in a substrate and includes a first and a second part. The first part has a first side wall extending from a surface of the substrate to a location, the first side wall has a first slope, and a surface of it has a first roughness. The second part has a second side wall extending from the first side wall to a location, the second side wall has a second slope, and a surface of it has a second roughness, the second slope is greater than the first slope, and the second roughness is greater than the first roughness. The disclosure solves the problem that it is difficult to fill the shallow trench isolating structure, and an undersized available space of the surface of the substrate may not be caused.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: December 21, 2021
    Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Hsienshih Chu, Dehao Huang, Yunfan Chou, Yaoguang Xu, Yucheng Tung
  • Patent number: 11177367
    Abstract: A method is presented for forming a vertical transport field effect transistor (VTFET). The method includes forming a plurality of fins over a substrate, depositing a sacrificial material adjacent the plurality of fins, forming self-aligned spacers adjacent the plurality of fins, removing the sacrificial material to define openings under the self-aligned spacers, filling the openings with bottom spacers, depositing an interlayer dielectric (ILD) after patterning, laterally etching the substrate such that bottom surfaces of the plurality of fins are exposed, the lateral etching defining cavities within the substrate, and filling the cavities with an epitaxial material such that epitaxial regions are defined each having a symmetric tapered shape under a twin-fin structure. The single fin device can be formed through additional patterning and bottom epi under the single fin device that has an asymmetric tapered shape.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: November 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tao Li, Ruilong Xie, Sung Dae Suk, Heng Wu
  • Patent number: 11043596
    Abstract: A method for forming a semiconductor device is disclosed. A substrate having at least two fins thereon and an isolation trench between the at least two fins is provided. A liner layer is then deposited on the substrate. The liner layer conformally covers the two fins and interior surface of the isolation trench. A stress-buffer film is then deposited on the liner layer. The stress-buffer film completely fills a lower portion that is located at least below half of a trench depth of the isolation trench. A trench-fill oxide layer is then deposited to completely fill an upper portion of the isolation trench.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: June 22, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Wei Su, Hao-Hsuan Chang, Chih-Wei Chang, Chi-Hsuan Cheng, Ting-An Chien, Bin-Siang Tsai
  • Patent number: 11031280
    Abstract: A method includes etching a semiconductor substrate to form trenches extending into the semiconductor substrate, and depositing a first dielectric layer into the trenches. The first dielectric layer fills lower portions of the trenches. A Ultra-Violet (UV) treatment is performed on the first dielectric layer in an oxygen-containing process gas. The method further includes depositing a second dielectric layer into the trenches. The second dielectric layer fills upper portions of the trenches. A thermal treatment is performed on the second dielectric layer in an additional oxygen-containing process gas. After the thermal treatment, an anneal is performed on the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung Han Hsu, Kuan-Cheng Wang, Han-Ti Hsiaw, Shin-Yeu Tsai
  • Patent number: 10886422
    Abstract: This invention concerns a grouped nanostructured unit system forming a metamaterial within the silicon and the manufacturing process to arrange them therein in an optimal manner. The nanostructured units are grouped and conditioned in an optimal arrangement inside the silicon material. The process comprises the modification of the elementary crystal unit together with the stress field, the electric field and a heavy impurity doping in order to form a superlattice of nanostructured units grouped in an optimal arrangement so as to improve the efficiency of the light-to-electricity conversion by means of efficient use of the kinetic energy of hot electrons and efficient collection of all electrons generated within the converter.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: January 5, 2021
    Assignee: SEGTON ADVANCED TECHNOLOGY
    Inventors: Zbigniew Kuznicki, Patrick Meyrueis
  • Patent number: 10847476
    Abstract: A semiconductor package includes a connection structure, a semiconductor chip, and an encapsulant. The connection structure includes an insulating layer, a redistribution layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the redistribution layer. The semiconductor chip has an active surface on which connection pads are disposed and an inactive surface opposing the active surface, and the active surface is disposed on the connection structure to face the connection structure. The encapsulant covers at least a portion of the semiconductor chip. The semiconductor chip includes a groove formed in the active surface and a dam structure disposed around the groove in the active surface.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Woo Myung, Jae Kul Lee, Seon Ho Lee
  • Patent number: 10818682
    Abstract: To provide, in an increased production yield, a reliability-improved semiconductor product having both a planar type transistor and a fin type transistor. A semiconductor device having both a planar type transistor and a fin type transistor is manufactured by decreasing the thickness of a hard mask for the formation of element isolation in the planar type transistor region prior to formation of element isolation in the fin type transistor region.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: October 27, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Shigeki Katou
  • Patent number: 10811318
    Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure, and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzung-Yi Tsai, Yen-Ming Chen, Tsung-Lin Lee, Chih-Chieh Yeh
  • Patent number: 10643883
    Abstract: A method of forming an isolation structure includes the following steps. A substrate having a first trench, a second trench and a third trench is provided, wherein the opening of the third trench is larger than the opening of the second trench, and the opening of the second trench is larger than the opening of the first trench. A first oxide layer is formed to conformally cover the first trench, the second trench and the third trench by an atomic layer deposition (ALD) process. A second oxide layer fills up the first trench by an in-situ steam generation (ISSG) process.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 5, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Chun Chen, Hsuan-Tung Chu, Yi-Wei Chen, Wei-Hsin Liu, Yu-Cheng Tung, Chia-Lung Chang
  • Patent number: 10636673
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The method includes performing a first planarization process over the second layer until the stop layer is exposed. The method includes performing an etching process to remove the second layer, the stop layer, and an upper portion of the first layer. The method includes performing a second planarization process over the first layer.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: April 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chen Wei, Chun-Chieh Chan, Chun-Jui Chu, Jen-Chieh Lai, Shih-Ho Lin
  • Patent number: 10439136
    Abstract: A method of forming a nanoparticle includes forming a layer of semiconductor material on a substrate, forming a first layer on the semiconductor material, and etching the semiconductor layer to form the nanoparticle including the first layer on a first side of the nanoparticle and the semiconductor material on a second side of the nanoparticle.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: October 8, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Qing Cao, Kangguo Cheng, Zhengwen Li, Fei Liu
  • Patent number: 10332780
    Abstract: A semiconductor device includes a substrate having a first active pattern and a second active pattern, the first active pattern including a first recess region dividing an upper portion thereof into a first portion and a second portion, the second active pattern including a second recess region dividing an upper portion thereof into a first portion and a second portion, a first insulating pattern covering an inner sidewall of the first recess region, and a second insulating pattern covering an inner sidewall of the second recess region. The first insulating pattern and the second insulating pattern include the same insulating material, and a volume fraction of the first insulating pattern with respect to a volume of the first recess region is smaller than a volume fraction of the second insulating pattern with respect to a volume of the second recess region.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunki Min, Songe Kim, Koungmin Ryu, Je-Min Yoo
  • Patent number: 10256136
    Abstract: A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches communicate with each other, the second trench may be formed wider than the first trench; forming a liner layer over an inner surface of the first trench and over an inner surface of the second the trench; forming a capping layer over the liner layer to form a merged overhang and a non-merged overhang, the merged overhang may be fill a top portion of the first trench, the non-merged overhang may be open a top portion of the second trench; and forming a gap-fill layer over the capping layer to fill a lower portion of the first trench and the second trench.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: April 9, 2019
    Assignee: SK hynix Inc.
    Inventors: Eun-Jeong Kim, Jin-Yul Lee, Han-Sang Song, Su-Ho Kim
  • Patent number: 10103019
    Abstract: The present invention provides a method of fabricating a semiconductor structure. Firstly, a substrate is provided, a dense region and an isolation region are defined, next, a first dielectric layer is formed on the dense region and the isolation region, and then a plurality of first recesses are formed in the first dielectric layer within the dense region, and a second recess is formed in the first dielectric layer within the isolation region, wherein the width of the second recess is greater than three times of the width of each first recess. Afterwards, a second dielectric layer is then filled in each first recess and the second recess, wherein a top surface of the second dielectric layer within the isolation region is higher than a top surface of the second dielectric layer within the dense region. Next, an etching back process is performed, to remove the second dielectric layer.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: October 16, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee
  • Patent number: 9899476
    Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: February 20, 2018
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Guilhem Bouton, Pascal Fornara, Christian Rivero
  • Patent number: 9818646
    Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: November 14, 2017
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Joblot, Pierre Bar
  • Patent number: 9779983
    Abstract: A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a first dielectric material in the trench, forming a second dielectric material above the first dielectric material, forming a first air gap in the first dielectric material in the trench, and forming a second air gap in the second dielectric material above the first air gap.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: October 3, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Oshi Wakamatsu, Yasuhiro Domae
  • Patent number: 9761499
    Abstract: A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and the handle wafer; a first set of fins disposed in the top wafer and oriented in a <110> direction of the (100) silicon; and a second set of fins disposed in the handle wafer and oriented in a <112> direction of the (110) silicon. The first set of fins and the second set of fins are aligned.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: September 12, 2017
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Ali Khakifirooz, Shogo Mochizuki, Alexander Reznicek
  • Patent number: 9673300
    Abstract: Semiconductor devices and methods of fabricating the same are provided. The methods may include forming an isolation region defining a fin active region, forming a sacrificial field gate pattern on the isolation region and forming a sacrificial fin gate pattern on the fin active region. The method may also include forming a field gate cut zone comprising a first recess exposing a surface of the isolation region and a fin active cut zone comprising a second recess exposing a surface of the fin active region, forming a fin active recess in the second recess of the fin active cut zone and forming a field gate core and a fin active core by forming an insulation material in the first recess of the field gate cut zone and the fin active recess, respectively.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: June 6, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungseok Ha, Keunhee Bai, Kyounghwan Yeo, Eunsil Park, Heonjong Shin
  • Patent number: 9589828
    Abstract: A layer of partially planarized organosilicate (DUO) is spin-coated onto a layer of high density plasma (HDP) oxide on a silicon wafer after the shallow trench isolation (STI) is filled with the HDP oxide. Then the DUO layer is etched using a specialized process specifically tuned to etch the DUO and high density plasma (HDP) oxide at a certain selectivity. The higher areas of the wafer topography (active Si areas) have thinner DUO and as the etch process proceeds it starts to etch through the HDP oxide in these areas (active Si areas). The etch process is stopped after a certain depth is reached and before touching down on the silicon nitride oxidation layer. The DUO is removed and a standard chemical-mechanical polish (CMP) is performed on the silicon wafer. After the CMP step the silicon nitride is removed, exposing the silicon substrate between the field oxides.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: March 7, 2017
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Justin Hiroki Sato, Gregory Allen Stom
  • Patent number: 9577002
    Abstract: A solid-state imaging device includes a plurality of photoelectric conversion portions each provided in a semiconductor substrate and receives incident light through a light sensing surface, and a pixel separation portion provided to electrically separate a plurality of pixels. At least a pinning layer and a light shielding layer are provided in an inner portion of a trench provided on a side portion of each of the photoelectric conversion portions in an incident surface side, the trench includes a first trench and a second trench formed to be wider than the first trench in a portion shallower than the first trench, the pinning layer is formed in an inner portion of the first trench to cover an inside surface of the second trench, and the light shielding layer is formed to bury an inner portion of the second trench at least via the pinning layer.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: February 21, 2017
    Assignee: Sony Corporation
    Inventor: Takayuki Enomoto
  • Patent number: 9570570
    Abstract: The present disclosure relates to a silicon carbide (SiC) field effect device that has a gate assembly formed in a trench. The gate assembly includes a gate dielectric that is an dielectric layer, which is deposited along the inside surface of the trench and a gate dielectric formed over the gate dielectric. The trench extends into the body of the device from a top surface and has a bottom and side walls that extend from the top surface of the body to the bottom of the trench. The thickness of the dielectric layer on the bottom of the trench is approximately equal to or greater than the thickness of the dielectric layer on the side walls of the trench.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: February 14, 2017
    Assignee: Cree, Inc.
    Inventors: Daniel Jenner Lichtenwalner, Lin Cheng, Anant Kumar Agarwal, John Williams Palmour
  • Patent number: 9553172
    Abstract: A semiconductor device and a method of forming the same are disclosed. The method includes receiving a substrate having a fin projecting through an isolation structure over the substrate; etching a portion of the fin, resulting in a trench; forming a doped material layer on sidewalls of the trench; and growing at least one epitaxial layer in the trench. The method further includes exposing a first portion of the at least one epitaxial layer over the isolation structure; and performing an annealing process, thereby driving dopants from the doped material layer into a second portion of the at least one epitaxial layer. The first portion of the at least one epitaxial layer provides a strained channel for the semiconductor device and the second portion of the at least one epitaxial layer provides a punch-through stopper.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: January 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yong-Yan Lu, Chia-Wei Soong, Hou-Yu Chen
  • Patent number: 9543416
    Abstract: One illustrative method disclosed herein includes, among other things, forming a first plurality of fins in the first region of the substrate, a second plurality of fins in the second region of the substrate, and a space in the substrate between two adjacent fins in the second region that corresponds to a first isolation region to be formed in the second region, forming a fin removal masking layer above the first and second regions of the substrate, wherein the fin removal masking layer has an opening positioned above at least a portion of at least one of the first plurality of fins, while masking all of the second plurality of fins in the second region and the space for the first isolation region, and performing an etching process through the first opening to remove the portions of the at least one of the first plurality of fins.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: January 10, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Min Gyu Sung, Ryan Ryoung-Han Kim
  • Patent number: 9536773
    Abstract: Embodiments of a mechanism for forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer are provided. The mechanism involves using one or more low-temperature thermal anneal processes with oxygen sources and one or more microwave anneals to convert a flowable dielectric material to silicon oxide. The low-temperature thermal anneal processes with oxygen sources and the microwave anneals are performed at temperatures below the ranges that could cause significant dopant diffusion, which help dopant profile control for advanced manufacturing technologies. In some embodiments, an implant to generate passages in the upper portion of the flowable dielectric layer is also used in the mechanism.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Tsan-Chun Wang
  • Patent number: 9461109
    Abstract: A method of forming a superjunction device includes providing a semiconductor layer having first and second opposing main surfaces and a first doping concentration of a dopant of a first conductivity type, forming at least one device proximate the first main surface, forming at least one trench adjacent to the device and extending into the semiconductor layer from the first main surface, doping at least a portion of a sidewall of the trench with a dopant of a second, different conductivity type to form a first region in the semiconductor layer adjacent to the sidewall and extending at least partially between the first and second main surfaces, providing a substrate with a first dielectric layer arranged thereon, bonding the first dielectric layer to the first main surface to cover the trench and at least a portion of the device, and removing the substrate.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 4, 2016
    Assignee: Icemos Technology, Ltd.
    Inventors: Takeshi Ishiguro, Samuel Anderson
  • Patent number: 9431495
    Abstract: A method of manufacturing a trench power MOSFET device with improved UIS performance and a high avalanche breakdown voltage is disclosed. The method includes performing a first etching of the epitaxial layer to form an active trench with an initial depth in an active area of the semiconductor substrate and a termination trench with a desired depth in a termination area of the semiconductor substrate, wherein the initial depth of the active trench is smaller than the desired depth of the termination trench and performing a second etching to increase the depth of the active trench to a desired depth wherein a depth difference between the desired depth of the active trench and the desired depth of the termination trench is smaller than a depth difference between the initial depth of the active trench and the desired depth of the termination trench.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: August 30, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yongping Ding, Yeeheng Lee, Xiaobin Wang, Madhur Bobde
  • Patent number: 9396985
    Abstract: Disclosed are an element isolation structure of a semiconductor device and a method for forming the same, the method including preparing a semiconductor substrate having an inactive region and an active region defined thereon, forming a first hard mask on the semiconductor substrate, exposing the inactive region of the semiconductor substrate by patterning the first hard mask, forming a second hard mask on the entire surface of the semiconductor substrate including the first hard mask, forming a deep trench in the semiconductor substrate by patterning the second hard mask and the semiconductor substrate, removing the patterned second hard mask, forming a shallow trench overlapped with the deep trench by patterning the semiconductor substrate using the first hard mask as a mask, forming an insulation film on the entire surface of the substrate including the shallow trench and the deep trench, filling the shallow trench and the deep trench by forming an element isolation film on the insulation film, and forming
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: July 19, 2016
    Assignee: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventor: Yang-Beom Kang
  • Patent number: 9331144
    Abstract: A semiconductor device includes, on one semiconductor substrate: a first element isolation region having a first width, wherein a liner oxide film, a liner nitride film and a silicon dioxide film are provided in succession from an outer peripheral side of an upper surface of the first element isolation region; and a second element isolation region having a second width that is larger than the first width, wherein a liner oxide film and a silicon dioxide film are provided in succession from an outer peripheral side of an upper surface of the second element isolation region.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: May 3, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Shingo Ujihara, Koji Taniguchi
  • Patent number: 9305826
    Abstract: A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second trench isolation areas in a substrate, with the openings for the second trench isolation areas being wider than the openings for the first trench isolation areas. The first and second trench isolation areas are etched in the substrate through the mask. The second trench isolation areas are further etched to the deeper than the first trench isolation areas. The trench isolation areas are filled with oxide material. Electrical devices can be formed on the substrate and electrically isolated by the first trench isolation areas and photonic devices can be formed over the second trench isolation areas and be optically isolated from the substrate.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: April 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Roy Meade, Gurtej Sandhu
  • Patent number: 9299584
    Abstract: Devices and methods of forming an integrated circuit and a FinFET device with a planarized permanent layer are provided. In an embodiment, a method of forming a planarized permanent layer includes providing a base substrate that has an uneven surface topography. A permanent layer is conformally formed over the base substrate. The permanent layer includes raised portions and sunken portions that correspond to the surface topography of the base substrate. A sacrificial layer is conformally formed over the permanent layer. The sacrificial layer and the raised portions of the permanent layer are chemical-mechanical planarized to provide the planarized permanent layer. The sacrificial layer is substantially completely removed after chemical-mechanical planarizing.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: March 29, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Dinesh Koli, Deepasree Konduparthi
  • Patent number: 9287497
    Abstract: Integrated circuits with a Hall effect sensor and methods for fabricating such integrated circuits are provided. The method includes forming a buried plate layer within a substrate and overlying a substrate base, where the buried plate layer is doped with an “N” type dopant. A cover insulating layer if formed overlying the buried plate layer, and a plurality of contact points are formed adjacent to the cover insulating layer.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Xinfu Liu
  • Patent number: 9269712
    Abstract: A method for making a semiconductor device may include forming a first semiconductor layer on a substrate comprising a first semiconductor material, forming a second semiconductor layer on the first semiconductor layer comprising a second semiconductor material, and forming mask regions on the second semiconductor layer and etching through the first and second semiconductor layers to define a plurality of spaced apart pillars on the substrate. The method may further include forming an oxide layer laterally surrounding the pillars and mask regions, and removing the mask regions and forming inner spacers on laterally adjacent corresponding oxide layer portions atop each pillar. The method may additionally include etching through the second semiconductor layer between respective inner spacers to define a pair of semiconductor fins of the second semiconductor material from each pillar, and removing the inner spacers and forming an oxide beneath each semiconductor fin.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: February 23, 2016
    Assignees: STMICROELECTRONICS, INC., GLOBALFOUNDRIES INC
    Inventors: Qing Liu, Ruilong Xie, Hyun-Jin Cho
  • Patent number: 9263320
    Abstract: An object of the invention is to provide a semiconductor device having improved performance. A method of manufacturing a semiconductor device includes: forming a trench and then forming a first insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to cover the side surface of the trench with the insulating film; forming a second insulating film made of a silicon oxide film through PECVD to cover the side surface of the trench with the second insulating film via the first insulating film; and forming a third insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to close the trench with the third insulating film while leaving a space in the trench.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: February 16, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsunori Murata, Takahiro Maruyama
  • Patent number: 9171848
    Abstract: An integrated circuit structure provides at least one metal-insulator-metal (MIM) capacitor and a moat isolation structure wherein the number of processes required is substantially minimized and the formation of the MIM capacitor and the moat isolation structure effectively decouple while the number of processes common to the moat isolation structure and the MIM capacitor are maximized. Additional required processes are non-critical and tolerant of overlay positioning error.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: October 27, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Thomas Walter Dyer, Herbert Lei Ho, Jin Liu
  • Patent number: 9147579
    Abstract: A method of manufacturing a semiconductor device with an SON structure having a thick cavity inside a semiconductor substrate is disclosed. The method forms a plurality of trenches with a predetermined distance between adjacent trenches. Each trench has, at a middle portion between the trench top and bottom, an outwardly expanding sectional shape. High temperature annealing is conducted driving surface migration of silicon atoms in the surface region of the silicon substrate to close the top of the trench, resulting in formation of a plurality of small cavities composed of the trenches in the silicon substrate. Further high temperature annealing joins the plurality of small cavities to form a single cavity. Second opening width x2 at the middle portion ranges from 1.1 times to 1.5 times of first opening width x1 at the top of the trench. Aspect ratio of the trench is at least 8.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: September 29, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Reiko Hiruta
  • Patent number: 9123782
    Abstract: An amorphous silicon film formation method includes transferring a base in a process chamber, heating the base in the process chamber, setting a process pressure inside the process chamber, forming a seed layer on a surface of the base by flowing aminosilane-based gas in the process chamber under a process condition in which the aminosilane-based gas is not thermally decomposed and adsorbing the aminosilane-based gas onto the surface of the base, the process condition having a first temperature, and forming an amorphous silicon film on the seed layer by heating the base at a second temperature higher than the first temperature, flowing silane-based gas containing no amino group in the process chamber, and thermally decomposing the silane-based gas containing no amino group, wherein the forming of the seed layer and the forming of the amorphous silicon film are successively performed in the process chamber.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: September 1, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuhide Hasebe, Hiroki Murakami, Akinobu Kakimoto
  • Patent number: 9087757
    Abstract: Disclosed herein is a semiconductor device including an element isolation region configured to be formed on a semiconductor substrate, wherein the element isolation region is formed of a multistep trench in which trenches having different diameters are stacked and diameter of an opening part of the lower trench is smaller than diameter of a bottom of the upper trench.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: July 21, 2015
    Assignee: Sony Corporation
    Inventor: Yuki Miyanami
  • Patent number: 9087790
    Abstract: According to example embodiments of inventive concepts, a method of fabricating a 3D semiconductor device may include: forming a stack structure including a plurality of horizontal layers sequentially stacked on a substrate including a cell array region and a contact region; forming a first mask pattern covering the cell array region and defining openings extending in one direction over the contact region; performing a first etching process with a first etch-depth using the first mask pattern as an etch mask on the stack structure; forming a second mask pattern covering the cell array region and exposing a part of the contact region; and performing a second etching process with a second etch-depth using the second mask pattern as an etch mask structure on the stack structure. The second etch-depth may be greater than the first etch-depth.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: July 21, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ik Oh, Daehyun Jang, Ha-Na Kim, Seongsoo Lee
  • Patent number: 9048136
    Abstract: A static random access memory cell is provided formed in a silicon layer over a buried oxide layer on a substrate and including first and second inverters each having a pull-up and pull-down transistor configured to form a cell node. Each of the pull-down transistors of the first and second inverters are formed over first regions below the buried oxide layer with the first regions having a first doping level forming first backgates for the pull-down transistors. A pair of passgate transistors respectively couples to the cell nodes of the first and second inverters and each are formed over second regions below the buried oxide layer with the second regions having a second doping level forming second backgates for the passgate transistors. Active bias circuitry applies potentials to the first and second backgates during read, standby and write operations of the static random access memory cell.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: June 2, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Randy W. Mann, Scott D. Luning
  • Publication number: 20150145043
    Abstract: An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer, a transistor disposed on the second semiconductor substrate and having a bottom insulated by the insulating layer, a plurality of shallow trench isolations disposed on opposite sides of the transistor, a cavity disposed below the bottom of the transistor, and a plurality of isolation plugs disposed on opposite sides of the cavity. By having a cavity located below the transistor, parasitic couplings between the transistor and the substrate are reduced and the performance of the integrated circuit is improved.
    Type: Application
    Filed: September 24, 2014
    Publication date: May 28, 2015
    Inventors: HERB HE HUANG, ZHONGSHAN HONG
  • Patent number: 9034707
    Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: May 19, 2015
    Assignee: SK Hynix Inc.
    Inventor: Nam-Jae Lee
  • Patent number: 9034724
    Abstract: A method of forming a substrate with isolation areas suitable for integration of electronic and photonic devices is provided. A common reticle and photolithographic technique is used to fabricate a mask defining openings for etching first and second trench isolation areas in a substrate, with the openings for the second trench isolation areas being wider than the openings for the first trench isolation areas. The first and second trench isolation areas are etched in the substrate through the mask. The second trench isolation areas are further etched to the deeper than the first trench isolation areas. The trench isolation areas are filled with oxide material. Electrical devices can be formed on the substrate and electrically isolated by the first trench isolation areas and photonic devices can be formed over the second trench isolation areas and be optically isolated from the substrate.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: May 19, 2015
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Roy Meade, Gurtej Sandhu
  • Publication number: 20150132919
    Abstract: In a method for manufacturing a dual shallow trench isolation structure, a substrate is provided, and a mask layer is formed on the substrate. The mask layer is patterned by using a photomask to form at least one first hole and at least one second hole in the mask layer, in which a depth of the at least one first hole is different from a depth of the at least one second hole. The mask layer and the substrate are etched to form at least one first trench having a first depth and at least one second trench having a second depth, in which the first depth is different from the second depth. The remaining mask layer is removed. A first isolation layer and A second isolation layer are respectively formed in the at least one first trench and the at least one second trench.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Cheng CHANG, Chai-Der YEN, Fu-Tsun TSAI, Chi-Cherng JENG, Chih-Mu HUANG
  • Patent number: 9029935
    Abstract: A nonvolatile memory device includes a floating gate formed over a semiconductor substrate, an insulator formed on a first sidewall of the floating gate, a dielectric layer formed on a second sidewall and an upper surface of the floating gate, and a control gate formed over the dielectric layer.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: May 12, 2015
    Assignee: SK Hynix Inc.
    Inventor: Nam-Jae Lee