Grooved And Refilled With Deposited Dielectric Material Patents (Class 438/424)
  • Patent number: 11404305
    Abstract: A manufacturing method a semiconductor device includes the following steps. A first mask pattern and a second mask pattern are formed on a first region and a second region of a substrate respectively. The second region is located adjacent to the first region. A top surface of the first mask pattern is lower than a top surface of the second mask pattern in a thickness direction of the substrate. A trench is formed in the substrate. The trench is partly located in the first region and partly located in the second region. A first etching process is performed for reducing a thickness of the second mask pattern and reducing a height difference between the top surface of the first mask pattern and the top surface of the second mask pattern in the thickness direction of the substrate. An isolation structure is formed in the trench after the first etching process.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: August 2, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ta-Wei Chiu, Shin-Hung Li, Tsung-Yu Yang, Ruei-Jhe Tsao
  • Patent number: 11403454
    Abstract: A system and method for placement and simulation of a cell in proximity to a cell with a diffusion break is herein disclosed. According to one embodiment, an integrated circuit is designed to include a first cell that has a first edge and a second edge opposite the first edge. The first cell may also include a diffusion region that extends from the first edge to the second edge with a diffusion break separating the diffusion region. The diffusion break may be spaced away from the second edge by a distance that degrades a metric (e.g., a delay, a slew, dynamic power, or leakage) of a second cell placed next to the second edge beyond a threshold level.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: August 2, 2022
    Assignee: Synopsys, Inc.
    Inventors: Deepak Dattatraya Sherlekar, Shanie George
  • Patent number: 11404323
    Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. The isolation regions extend into a semiconductor substrate. The method further includes etching a portion of the semiconductor fin to form a trench, filling the trench with a first dielectric material, wherein the first dielectric material has a first bandgap, and performing a recessing process to recess the first dielectric material. A recess is formed between opposing portions of the isolation regions. The recess is filled with a second dielectric material. The first dielectric material and the second dielectric material in combination form an additional isolation region. The second dielectric material has a second bandgap smaller than the first bandgap.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chung-Ting Ko, Chi On Chui
  • Patent number: 11380583
    Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: July 5, 2022
    Assignee: TESSERA LLC
    Inventors: Lawrence A. Clevenger, Carl J. Radens, John H. Zhang
  • Patent number: 11355464
    Abstract: A semiconductor device structure includes a silicon layer disposed over a first semiconductor die, and a first mask layer disposed over the silicon layer. The semiconductor device structure also includes a second semiconductor die disposed over the first mask layer, and a through silicon via penetrating through the silicon layer and the first mask layer. A bottom surface of the through silicon via is greater than a top surface of the through silicon via, and the top surface of the through silicon via is greater than a cross-section of the through silicon via between and parallel to the top surface and the bottom surface of the through silicon via.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: June 7, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Tse-Yao Huang
  • Patent number: 11355498
    Abstract: A method of manufacturing an integrated circuit device includes: over a substrate, forming first hard mask patterns extending in a first direction parallel to a top surface of the substrate and arranged at a first pitch in a second direction; forming a plurality of first trenches in the substrate using the first hard mask patterns as etching masks; forming a plurality of first gate electrodes on inner walls of the plurality of first trenches; over the substrate, forming second hard mask patterns extending in the first direction and arranged at a second pitch in the second direction; forming a plurality of second trenches in the substrate using the second hard mask patterns as etching masks, each of the plurality of second trenches being disposed between two adjacent first trenches; and forming a plurality of second gate electrodes on inner walls of the plurality of second trenches.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: June 7, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaybok Choi, Yongseok Ahn, Seunghyung Lee
  • Patent number: 11342217
    Abstract: The present disclosure provides a method for improving HDP filling defects through an STI etching process, comprises a wafer uniformly distributed with pixel areas and logical areas, and dividing the wafer into quadrants 1 to 4; placing the second quadrants in an etching chamber in a manner of facing to a cantilever of an etching machine; etching the wafer to form STI areas with the same depth in the pixel areas and the logical areas of the quadrants 1 to 4; removing the wafer from the etching machine and covering the STI areas of the pixel areas with a photoresist; placing the wafer on an electrostatic chuck of the etching chamber again, and enabling any quadrant except the second quadrant to face to the cantilever; continuously etching the STI areas of the logical areas of the quadrants 1 to 4 to form deep STI areas.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: May 24, 2022
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventors: Zhengying Wei, Xuedong Fan, Zhiyong Wu
  • Patent number: 11282890
    Abstract: A method of fabricating a target shallow trench isolation (STI) structure between devices in a wafer-level image sensor having a large number of pixels includes etching a trench, the trench having a greater depth and width than a target STI structure and epitaxially growing the substrate material in the trench for a length of time necessary to provide the target depth and width of the isolation structure. An STI structure formed in a semiconductor substrate includes a trench etched in the substrate having a depth and width greater than that of the STI structure, and semiconductor material epitaxially grown in the trench to provide a critical dimension and target depth of the STI structure. An image sensor includes a semiconductor substrate, a photodiode region, a pixel transistor region and an STI structure between the photodiode region and the pixel transistor region.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: March 22, 2022
    Assignee: OmniVision Technologies, Inc.
    Inventor: Seong Yeol Mun
  • Patent number: 11239315
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to dual trench isolation structures and methods of manufacture. The structure includes: a doped well region in a substrate; a dual trench isolation region within the doped well region, the dual trench isolation region comprising a first isolation region of a first depth and a second isolation region of a second depth, different than the first depth; and a gate structure on the substrate and extending over a portion of the dual trench isolation region.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: February 1, 2022
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Shiv Kumar Mishra, Baofu Zhu, Arkadiusz Malinowski, Kaushikee Mishra
  • Patent number: 11227767
    Abstract: A substrate is provided with a patterned layer over a stack of one or more processing layers. The processing layers include at least one patterned layer and one etch target layer. CD trimming between the CD of the patterned layer and the CD of the etch target layer may be achieved after the pattern is transferred to the etch target layer. After the etch target layer is patterned, a plasma free gas phase etch process may be used to trim the CD of the etch target layer to finely tune the CD. In an alternate embodiment, plasma etch trim processes may be used in combination with the gas phase etch process. In such an embodiment, partial CD trimming may be achieved via the plasma etching of the various process layers and then additional CD trimming may be achieved by subjecting the etch target layer to the plasma free gas phase etch after the desired pattern has been formed in the etch target layer.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: January 18, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Angelique Raley, Kal Subhadeep
  • Patent number: 11227789
    Abstract: There is provided a method of filling one or more recesses by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, introducing a second reactant to the substrate with a second dose, wherein the first and the second doses overlap in an overlap area where the first and second reactants react and leave an initially substantially unreacted area where the first and the second areas do not overlap; introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant to form deposited material; and etching the deposited material. An apparatus for filling a recess is also disclosed.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: January 18, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami Pore, Zecheng Liu
  • Patent number: 11217621
    Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Chou, Chih-Yu Lai, Shih Pei Chou, Yen-Ting Chiang, Hsiao-Hui Tseng, Min-Ying Tsai
  • Patent number: 11211293
    Abstract: FinFET device and method of forming the same are provided. The method of forming the FinFET device includes the following steps. A substrate having a plurality of fins is provided. An isolation structure is on the substrate surrounding lower portions of the fins. A hybrid fin is formed aside the fins and on the isolation structure. A plurality of gate lines and a dielectric layer are formed. The gate lines are across the fins and the hybrid fin, the dielectric layer is aside the gate lines. A portion of the gate lines is removed, so as to form first trenches in the dielectric layer and in the gate lines, exposing a portion of the hybrid fin and a portion of the fins underlying the portion of the gate lines. The portion of the fins exposed by the first trench and the substrate underlying thereof are removed, so as to form a second trench under the first trench. An insulating structure is formed in the first trench and the second trench.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Chung-Wei Hsu
  • Patent number: 11208319
    Abstract: A method for manufacturing a MEMS unit for a micromechanical pressure sensor. The method includes the steps: providing a MEMS wafer including a silicon substrate and a first cavity formed therein, under a sensor membrane; applying a layered protective element on the MEMS water; and exposing a sensor core from the back side, a second cavity being formed between the sensor core and the surface of the silicon substrate, and the second cavity being formed with the aid of an etching process which is carried out with the aid of etching parameters changed in a defined manner; and removing the layered protective element.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: December 28, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Arne Dannenberg, Joachim Fritz, Thomas Friedrich, Torsten Kramer
  • Patent number: 11201082
    Abstract: A method includes forming an isolation region between a plurality of active regions of a semiconductor substrate, forming at least one deep trench extending from the isolation region toward a bottom of the semiconductor substrate, and forming an interlayer dielectric layer over the semiconductor substrate. The interlayer dielectric layer fills in the deep trench to form a deep trench isolation structure and an air void in the deep trench isolation structure.
    Type: Grant
    Filed: November 16, 2019
    Date of Patent: December 14, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Hua Yen, Ching-Hung Kao, Po-Jen Wang, Tsung-Han Tsai
  • Patent number: 11201156
    Abstract: A semiconductor device includes a substrate that includes a cell region and a peripheral circuit region, a cell insulating pattern disposed in the cell region of the substrate that defines a cell active region, and a peripheral insulating pattern disposed in the peripheral circuit region of the substrate that defines a peripheral active region. The peripheral insulating pattern includes a first peripheral insulating pattern having a first width and a second peripheral insulating pattern having a second width greater than the first width. A topmost surface of at least one of the first peripheral insulating pattern and the second peripheral insulating pattern is positioned higher than a topmost surface of the cell insulating pattern.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: December 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chan-Sic Yoon, Dongoh Kim, Kiseok Lee, Sunghak Cho, Jemin Park
  • Patent number: 11171035
    Abstract: Techniques of fabricating shallow trench isolation structures that reduce or minimize the number of trench cones during the formation of shallow trenches. The disclosed techniques introduce separate etch steps for etching shallow trenches with small feature dimensions and for etching shallow trenches with large feature dimensions. As an example, the disclosed techniques involve etching a first shallow trench in a first region of a substrate with a first etching parameter, and etching a second shallow trench in a second region of a substrate with a second etching parameter different from the first etching parameter. Among other things, the etching parameter may include an etching selectivity ratio of silicon to an etch retardant that contributes to cone formations. Because of the separate etch steps, the disclosed techniques allow the sidewall slopes between the first and second shallow trenches to be within a few degrees of deviation.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: November 9, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Karen Hildegard Ralston Kirmse, Jonathan Philip Davis
  • Patent number: 11145539
    Abstract: The present disclosure describes a fabrication method that can form air-gaps in shallow trench isolation structures (STI) structures. For example, the method includes patterning a semiconductor layer over a substrate to form semiconductor islands and oxidizing the sidewall surfaces of the semiconductor islands to form first liners on the sidewall surfaces. Further, the method includes depositing a second liner over the first liners and the substrate and depositing a first dielectric layer between the semiconductor islands. The second liner between the first dielectric layer and the first liners is removed to form openings between the first dielectric layer and the first liners. A second dielectric layer is deposited over the first dielectric layer to enclose the openings and form air-gaps between the first dielectric layer and the first liners so that the gaps are positioned along the first liners.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh Singh, Hsin-Chi Chen, Kun-Tsang Chuang
  • Patent number: 11145733
    Abstract: The present invention discloses a method for forming a semiconductor device with a reduced silicon horn structure. After a pad nitride layer is removed from a substrate, a hard mask layer is conformally deposited over the substrate. The hard mask layer is then etched and trimmed to completely remove a portion of the hard mask layer from an active area and a portion of the hard mask layer from an oblique sidewall of a protruding portion of a trench isolation region around the active area. The active area is then etched to form a recessed region. A gate dielectric layer is formed in the recessed region and a gate electrode layer is formed on the gate dielectric layer.
    Type: Grant
    Filed: September 27, 2020
    Date of Patent: October 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chin-Hung Chen, Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Yu-Hsiang Lin, Po-Wen Su, Chung-Fu Chang, Guang-Yu Lo, Chun-Tsen Lu
  • Patent number: 11139172
    Abstract: A manufacturing method of a gate structure includes steps of forming a mask oxide layer on the substrate, performing a photolithography process on the mask oxide layer and the substrate to form a trench, etching the trench, removing the mask oxide layer, forming a bottom oxide layer on a surface of the substrate and a trench surface of the trench, forming a silicon nitride layer on the trench, removing a part of the bottom oxide layer, removing the silicon nitride layer, forming a gate oxide layer on the surface and a part of the trench surface, and forming a poly layer on the trench. Therefore, the advantages of simplifying the gate structure process and reducing the production cost are achieved.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: October 5, 2021
    Assignee: MOSEL VITELIC INC.
    Inventors: Shih-Chi Lai, Hung-Chih Chung, Hsien-Yi Cheng, Chia-Ming Kuo
  • Patent number: 11127840
    Abstract: Disclosed is a method for manufacturing an isolation structure for LDMOS, the method comprising: forming a first groove on the surface of a wafer; filling the first groove with silicon oxide; removing part of the surface of the silicon oxide within the first groove by means of etching; forming a silicon oxide corner structure at the corner of the top of the first groove by means of thermal oxidation; depositing a nitrogen-containing compound on the surface of the wafer to cover the surface of the silicon oxide within the first groove and the surface of the silicon oxide corner structure; dry-etching the nitrogen-containing compound to remove the nitrogen-containing compound from the surface of the silicon oxide within the first groove, and thereby forming a nitrogen-containing compound side wall residue; with the nitrogen-containing compound side wall residue as a mask, continuing to etch downwards to form a second groove; forming a silicon oxide layer on the side wall and the bottom of the second groove; rem
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: September 21, 2021
    Assignee: CSMC TECHNOLOGIES FAB2 CO., LTD.
    Inventors: Shukun Qi, Guipeng Sun
  • Patent number: 11127842
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: September 21, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Haiting Wang, Hong Yu, Zhenyu Hu
  • Patent number: 11114545
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a cyclic deposition-etch process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes forming a dielectric cap layer on the conformal film. The method includes performing an anneal process on the conformal film.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: September 7, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen
  • Patent number: 11069559
    Abstract: A semiconductor structure and method for forming such a structure are disclosed by the present invention. In the method, before a first trench in a pre-processed substrate is filled with any filling material, an auxiliary layer is formed over an inner surface of the first trench. Afterward, a first filling dielectric is formed and an etch back process is performed so that a top surface of the first filling dielectric is higher than that of the pre-processed substrate, and a second filling dielectric is then formed and subject to a second planarization process.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: July 20, 2021
    Assignee: NEXCHIP SEMICONDUCTOR CORPORATION
    Inventors: Sun-Hung Chen, Tsun-Min Cheng, Jui-Min Lee, Wei Xiang, Renwei Zhu
  • Patent number: 11056478
    Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shiang-Bau Wang, Ryan Chia-Jen Chen, Shu-Yuan Ku, Ming-Ching Chang
  • Patent number: 11011616
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Byron Ho, Michael L. Hattendorf, Christopher P. Auth
  • Patent number: 11011504
    Abstract: An optoelectronic semiconductor chip includes a semiconductor body including a first semiconductor region and a second semiconductor region, a recess extending through the first semiconductor region, the recess having a bottom surface, where the second semiconductor region is exposed, and a blocking element arranged on the bottom surface, wherein the at least one recess has a first width and a second width parallel to the main extension plane of the semiconductor body, and the first width is smaller than the second width.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: May 18, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Thomas Oszinda, Ban Loong Chris Ng
  • Patent number: 11011430
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region; forming a first gate structure and a second gate structure on the first fin-shaped structure; using a patterned mask to remove the first gate structure and part of the first fin-shaped structure to form a first trench; and forming a first dielectric layer in the first trench to form a first single diffusion break (SDB) structure and around the second gate structure.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: May 18, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Kai-Lin Lee, Wei-Jen Chen
  • Patent number: 10943812
    Abstract: A semiconductor device includes a first trench on the device region, a first device isolation layer in the first trench and defining an active pattern of the device region, a second trench on the interface region, and a second device isolation layer in the second trench. The second isolation layer includes a buried dielectric pattern, a dielectric liner pattern on the buried dielectric pattern, and a first gap-fill dielectric pattern on the dielectric liner pattern. The buried dielectric pattern includes a floor segment on a floor of the second trench, and a sidewall segment on a sidewall of the second trench. The sidewall segment has a thickness different from a thickness of the floor segment.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: March 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Semyeong Jang, Bong-Soo Kim, Heejae Chae
  • Patent number: 10886121
    Abstract: A method of reducing silicon consumption of a silicon material. The method comprises cleaning a silicon material and subjecting the cleaned silicon material to a vacuum anneal at a temperature below a melting point of silicon and under vacuum conditions. The silicon material is subjected to additional process acts without substantially removing silicon of the silicon material. Additional methods of forming a semiconductor structure and forming isolation structures are also disclosed.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Gurtej S. Sandhu
  • Patent number: 10879461
    Abstract: In a method for fabricating an electronic device including a semiconductor memory, the method includes: forming stack structures, each of the stack structures including a variable resistance pattern; forming capping layers on the stack structures, the capping layers including an impurity; forming a gap fill layer between the stack structures; and removing the impurity from the capping layers and densifying the gap fill layer by irradiating the capping layers and the gap fill layer with ultraviolet light.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyo June Kim, Chi Ho Kim, Sang Hoon Cho, Eung Rim Hwang
  • Patent number: 10861748
    Abstract: Provided are a semiconductor arrangement and a method for manufacturing the same. An example arrangement may comprise: a bulk semiconductor substrate; a fin formed on the substrate; a first FinFET and a second FinFET formed on the substrate, wherein the first FinFET comprises a first gate stack intersecting the fin and a first gate spacer disposed on sidewalls of the first gate stack, the second FinFET comprises a second gate stack intersecting the fin and a second gate spacer disposed on sidewalls of the second gate stack; a dummy gate spacer formed between the first FinFET and the second FinFET and intersecting the fin; a first isolation section self-aligned to a space defined by the dummy gate spacer, wherein the isolation section electrically isolates the first FinFET from the second FinFET; and a second isolation layer disposed under a bottom surface of the first isolation section.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: December 8, 2020
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 10833673
    Abstract: An operation adjustment method of an SOI device comprises steps of: (a) obtaining a drain current-substrate bias voltage characteristic of an NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of a PMOS transistor as a voltage obtained by subtracting a built-in potential of a pn junction from the lowest substrate bias voltage; and (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit. Reduction in the power consumption and maintenance of the radiation tolerance are both achieved for the SOI device.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: November 10, 2020
    Assignees: MITSUBISHI HEAVY INDUSTRIES, LTD., JAPAN AEROSPACE EXPLORATION AGENCY
    Inventors: Daisuke Matsuura, Takanori Narita, Masahiro Kato, Daisuke Kobayashi, Kazuyuki Hirose, Osamu Kawasaki, Yuya Kakehashi, Taichi Ito
  • Patent number: 10825809
    Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Seok Ha, Hyun Seung Song, Hyo Jin Kim, Kyoung Mi Park, Guk Il An
  • Patent number: 10770309
    Abstract: Systems and methods for improving process uniformity in a millisecond anneal system are provided. In some implementations, a process for thermally treating a substrate in a millisecond anneal system can include obtaining data indicative of a temperature profile associated with one or more substrates during processing in a millisecond anneal system. The process can include one or more of (1) changing the pressure inside the processing chamber of the millisecond anneal system; (2) manipulating the irradiation distribution by way of the refracting effect of a water window in the millisecond anneal system; (3) adjusting the angular positioning of the substrate; and/or (4) configuring the shape of the reflectors used in the millisecond anneal system.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 8, 2020
    Assignees: MATTSON TECHNOLOGY, INC., BEIJING E-TOWN SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Alexandr Cosceev, Markus Hagedorn, Christian Pfahler
  • Patent number: 10770341
    Abstract: A method for manufacturing a semiconductor device according to an embodiment includes forming a first insulating film on a semiconductor substrate, the first insulating film being patterned; forming a trench in the semiconductor substrate using the first insulating film as a mask; depositing a second insulating film in the trench and on the first insulating film; removing the second insulating film on the first insulating film using a CMP method; removing a portion of the first insulating film; removing a portion of the second insulating film using isotropic etching; and removing a remaining portion of the first insulating film.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: September 8, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Takahito Nakajima, Shinya Ito
  • Patent number: 10720438
    Abstract: An embodiment includes a system comprising: first, second, and third word lines on a semiconductor material; first, second, and third channels; first, second, and third capacitors including a ferroelectric material; a bit line; first, second, third, fourth, and fifth semiconductor nodes, wherein the first semiconductor node couples the first capacitor to the first channel, the second semiconductor node couples the bit line to the first channel; the third semiconductor node couples the second capacitor to the second channel, the fourth semiconductor node couples the third capacitor to the third channel, and the fifth semiconductor node couples the bit line to the third channel; wherein the first channel has a long axis and a short axis; wherein the long axis intersects a continuous, uninterrupted portion of the semiconductor material from the first channel to the third channel.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
  • Patent number: 10720362
    Abstract: A device includes a semiconductor fin, a first source/drain feature, a second source/drain feature, and a dielectric plug. The first source/drain feature adjoins the semiconductor fin. The second source/drain feature adjoins the semiconductor fin. The dielectric plug extends from above the semiconductor fin into the semiconductor fin, the dielectric plug is between the first source/drain feature and the second source/drain feature. The dielectric plug includes a waist and a first portion below the waist, and a width of the waist is less than a width of the first portion of the dielectric plug.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuei-Ming Chang, Rei-Jay Hsieh, Cheng-Han Wu, Chie-Iuan Lin
  • Patent number: 10714599
    Abstract: A semiconductor device including a first fin type pattern and a second fin type pattern which protrude from a substrate and are spaced apart from each other to extend in a first direction, a dummy fin type pattern protruding from the substrate between the first fin type pattern and the second fin type pattern, a first gate structure extending in a second direction intersecting with the first direction, on the first fin type pattern, a second gate structure extending in the second direction, on the second fin type pattern, and a capping pattern extending in the second direction, on the first gate structure and the second gate structure, wherein the capping pattern includes a separation part which is in contact with an upper surface of the dummy fin type pattern, and the dummy fin type pattern and the separation part separate the first gate structure and the second gate structure.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yun II Lee, Sung II Park, Jae Hyun Park, Hyung Suk Lee
  • Patent number: 10685953
    Abstract: An integrated semiconductor device includes a first transistor and a second transistor formed on a semiconductor substrate, and an isolation structure located adjacent to the transistors, including deep trenches, trapping regions formed between the deep trenches, and trench bottom doping regions formed at the end of each of the deep trenches, wherein each of the trapping regions includes a buried layer, a well region formed on the buried layer, and a highly doped region formed on the well region.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: June 16, 2020
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Hyun Chul Kim, Hee Baeg An, In Chul Jung, Jung Hwan Lee, Kyung Ho Lee
  • Patent number: 10685963
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises forming an active structure including a plurality of active patterns, a device isolation layer defining the active patterns, and a gate structure across the active patterns and extending in a first direction, forming a first mask pattern on the active structure, and forming a trench by using the first mask pattern as an etching mask to pattern the active structure. Forming the first mask pattern comprises forming in a first mask layer a plurality of first openings extending in a second direction intersecting the first direction, and forming in the first mask layer a plurality of second openings extending in a third direction intersecting the first and second directions.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kiseok Lee, Keunnam Kim, Eun A Kim, Eunjung Kim, Jeongseop Shim
  • Patent number: 10680070
    Abstract: A trench gate manufacturing method includes the following steps: Step 1, forming a trench in the surface of a semiconductor substrate; Step 2, forming a first oxide layer; Step 3, selecting a coating according to the depth-to-width ratio of the trench and forming the coating completely filling the trench; Step 4, etching back the coating through a dry etching process; Step 5, conducting wet etching on the first oxide layer with the coating reserved at the bottom of the trench as a mask so as to form a gate bottom oxide; Step 6, removing the coating; and Step 7, growing a gate oxide. By adoption of the trench gate manufacturing method, a BTO can be realized at a low cost, and can be well-formed in trenches with smaller depth-to-width ratios and thus is suitable for forming BTOs in trenches with various depth-to-width ratios, thereby having a wider application range.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: June 9, 2020
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Jiye Yang, Hao Li, Lei Wang, Longjie Zhao, Xiaoxiang Sun
  • Patent number: 10672873
    Abstract: Provided is a semiconductor device including a substrate having a first conductivity type, an isolation structure, a well region having the first conductivity type, a gate structure, and doped regions having a second conductivity type. The isolation structure is disposed in the substrate to form an active region of the substrate. The well region is disposed in the active region and surrounds sidewalls of the isolation structure to form a native region in the active region. The gate structure is disposed over the substrate in the native region. The doped regions are disposed respectively in the well region and the native region of the substrate at two sides of the gate structure. A method of fabricating the semiconductor device is also provided.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu
  • Patent number: 10615253
    Abstract: A semiconductor device and its manufacturing method, relating to semiconductor techniques, are presented. The semiconductor device includes a substrate, comprising an NMOS region that has a first groove; and a first separation structure, comprising: a first liner layer on the bottom of the first groove and a side surface of a lower portion of the first groove, a first separation material layer on the first liner layer filling the lower portion of the first groove, a second liner layer on a side surface of an upper portion of the first groove, and a second separation material layer on the first separation material layer and the second liner layer filling the upper portion of the first groove. This inventive concepts improves the performance of an NMOS device.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: April 7, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Guo Bin Yu, Xiao Ping Xu
  • Patent number: 10534260
    Abstract: According to one embodiment, a pattern formation method can include performing a first processing of causing a surface of a first member of a processing body to be hydrophobic. The processing body includes the first member and a second member. The second member is provided at a portion of the first member. The method can include performing a second processing of causing the processing body to contact an atmosphere including a metal compound. The second processing is after the first processing. The method can include performing a third processing of processing the processing body in an atmosphere including at least one selected from the group consisting of water, oxygen, and ozone. The third processing is after the second processing. In addition, the method can include removing, after the third processing, at least a portion of another portion of the first member by using the second member as a mask.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: January 14, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tomoaki Sawabe, Shinobu Sugimura, Koji Asakawa
  • Patent number: 10522546
    Abstract: A semiconductor device includes a substrate; semiconductor fins over the substrate and oriented lengthwise along a first direction; first multi-dielectric-layer (MDL) fins and second MDL fins over the substrate and oriented lengthwise along the first direction, wherein the first and the second MDL fins are intermixed with the semiconductor fins, wherein each of the first MDL fins and the second MDL fins includes an outer dielectric layer and an inner dielectric layer, wherein the outer dielectric layer and the inner dielectric layer have different dielectric materials; and gate structures oriented lengthwise along a second direction generally perpendicular to the first direction, wherein the gate structures are spaced from each other along the first direction, and are separated by the first MDL fins along the second direction, wherein the gate structures engage the semiconductor fins and the second MDL fins.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventor: Jhon Jhy Liaw
  • Patent number: 10510892
    Abstract: Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: December 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Huiming Bu, Kangguo Cheng, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu
  • Patent number: 10504795
    Abstract: Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlOx). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kun-Yu Lee, Huicheng Chang, Che-Hao Chang, Ching-Hwanq Su, Weng Chang, Xiong-Fei Yu
  • Patent number: 10460980
    Abstract: A method for fabricating semiconductor device comprising the steps of: forming a first trench and a second trench in a substrate; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.
    Type: Grant
    Filed: February 4, 2018
    Date of Patent: October 29, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Chia-Huei Lin, Kuo-Yuh Yang
  • Patent number: 10446448
    Abstract: A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure; a first oxide layer on the first fin-shaped structure; a second oxide layer on and directly contacting the first oxide layer and the STI; and a third oxide layer on the second fin-shaped structure, wherein a thickness of the third oxide layer is less than a thickness of the first oxide layer.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Hao Lin, Hsin-Yu Chen, Chun-Tsen Lu, Shou-Wei Hsieh