Abstract: An electro-optical device is fabricated on a semiconductor-on-insulator (SOI) substrate. The electro-optical device comprises a silicon dioxide layer, and an active layer having ferroelectric properties on the silicon dioxide layer. The silicon dioxide layer includes a first silicon dioxide layer of the SOI substrate and a second silicon dioxide layer converted from a silicon layer of the SOI substrate. The active layer includes a buffer layer epitaxially grown on the silicon layer of the SOI substrate and a ferroelectric layer epitaxially grown on the buffer layer. The electro-optical device further comprises one or more additional layers over the active layer, and first and second contacts to the active layer through at least one of the one or more additional layers. Methods of fabricating the electro-optical device are also described herein.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a main surface, a diode region of the first conductivity type formed in a surface layer portion of the main surface of the semiconductor layer, a carrier trapping region including crystal defects and formed along a peripheral edge of the diode region in the surface layer portion of the main surface of the semiconductor layer, and an anode electrode formed on the main surface of the semiconductor layer and forming a Schottky junction with the diode region.

Abstract: A Fin FET semiconductor device includes a fin structure extending in a first direction and extending from an isolation insulating layer. The Fin FET device also includes a gate stack including a gate electrode layer, a gate dielectric layer, side wall insulating layers disposed at both sides of the gate electrode layer, and interlayer dielectric layers disposed at both sides of the side wall insulating layers. The gate stack is disposed over the isolation insulating layer, covers a portion of the fin structure, and extends in a second direction perpendicular to the first direction. A recess is formed in an upper surface of the isolation insulating layer not covered by the side wall insulating layers and the interlayer dielectric layers. At least part of the gate electrode layer and the gate dielectric layer fill the recess.

Abstract: A method for forming a gate oxide film of a transistor device includes: step 1: forming a hard mask layer on the surface of a semiconductor substrate, etching the hard mask layer and the semiconductor substrate to form shallow trenches; step 2: performing an tilt-angle ion implantation to the upper area of the side surfaces of each shallow trench to form an upper doped region; step 3: filling a field oxide layer into the shallow trenches and removing the hard mask layer; and step 4: performing thermal oxidation to form a gate oxide film on the surface of an active region. The method can improve the morphology of the gate oxide film, thus increase the breakdown voltage threshold and reliability of the device.

Abstract: A method for producing semiconductor regions including impurities includes forming a trench in a first surface of a semiconductor body. Impurity atoms are implanted into a bottom of the trench. The trench is extended deeper into the semiconductor body, thereby forming a deeper trench. Impurity atoms are implanted into a bottom of the deeper trench.

Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then reoxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

Abstract: The semiconductor device according to the present invention includes a semiconductor layer of a first conductivity type made of SiC, a body region of a second conductivity type formed on a surface layer portion of the semiconductor layer, a gate trench dug down from a surface of the semiconductor layer with a bottom surface formed on a portion of the semiconductor layer under the body region, source regions of the first conductivity type formed on a surface layer portion of the body region adjacently to side surfaces of the gate trench, a gate insulating film formed on the bottom surface and the side surfaces of the gate trench so that the thickness of a portion on the bottom surface is greater than the thickness of portions on the side surfaces, a gate electrode embedded in the gate trench through the gate insulating film, and an implantation layer formed on a portion of the semiconductor layer extending from the bottom surface of the gate trench to an intermediate portion of the semiconductor layer in the t

Abstract: A semiconductor device is formed in a semiconductor layer. A gate stack is formed over the semiconductor layer and comprises a first conductive layer and a second layer over the first layer. The first layer is more conductive and provides more stopping power to an implant than the second layer. A species is implanted into the second layer. Source/drain regions are formed in the semiconductor layer on opposing sides of the gate stack. The gate stack is heated after the step of implanting to cause the gate stack to exert stress in the semiconductor layer in a region under the gate stack.

Abstract: An arrangement, process and mask for implementing single-scan continuous motion sequential lateral solidification of a thin film provided on a sample such that artifacts formed at the edges of the beamlets irradiating the thin film are significantly reduced. According to this invention, the edge areas of the previously irradiated and resolidified areas which likely have artifacts provided therein are overlapped by the subsequent beamlets. In this manner, the edge areas of the previously resolidified irradiated areas and artifacts therein are completely melted throughout their thickness. At least the subsequent beamlets are shaped such that the grains of the previously irradiated and resolidified areas which border the edge areas melted by the subsequent beamlets grow into these resolidifying edges areas so as to substantially reduce or eliminate the artifacts.

Abstract: A method for decreasing polysilicon gate resistance in a carbon co-implantation process which includes: depositing a first salicide block layer on a formed gate of a MOS device and etching it to form a first spacer of a side surface of the gate of the MOS device; performing a P-type heavily doped boron implantation process and a thermal annealing treatment, so as to decrease the resistance of the polysilicon gate; removing said first spacer, performing a lightly doped drain process, and performing a carbon co-implantation process at the same time, so as to form ultra-shallow junctions at the interfaces between a substrate and source region and drain region below the gate; re-depositing a second salicide block layer on the gate and etching the mask to form a second spacer; forming a self-aligned silicide on the surface of the MOS device. The invention can decrease the resistance of the P-type polysilicon gate.

Abstract: A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region.

Abstract: Methods of forming coplanar active regions and isolation regions and structures thereof are disclosed. One embodiment includes shallow-trench-isolation (STI) formation in a semiconductor-on-insulator (SOI) layer on a substrate of a semiconductor structure; and bonding a handle wafer to the STI and SOI layer to form an intermediate structure. The intermediate structure may have a single layer including at least one STI region and at least one SOI region therein disposed between the damaged substrate and the handle wafer. The method may also include cleaving the hydrogen implanted substrate and removing any residual substrate to expose a surface of the at least one STI region and a surface of the at least one SOI region. The exposed surface of the at least one STI region forms an isolation region and the exposed surface of the at least one SOI region forms an active region, which are coplanar to each other.

Abstract: Embodiments of this method improve the results of a chemical mechanical polishing (CMP) process. A surface is implanted with a species, such as, for example, Si, Ge, As, B, P, H, He, Ne, Ar, Kr, Xe, and C. The implant of this species will at least affect dishing, erosion, and polishing rates of the CMP process. The species may be selected in one embodiment to either accelerate or decelerate the CMP process. The dose of the species may be varied over the surface in one particular embodiment.

Abstract: The leakage current generated due to the extension of the depleted layer to the end of the chip is reduced. In MOSFET 100, the depths of the trenches 112 in the gate pad portion 50 and the circumference portion 70 are larger than the depths of the trenches 111 in the cell region 60. Therefore, the depleted layer extending from the cell region 60 along the direction toward the gate pad portion 50 or the direction toward the circumference portion 70 is blocked by the presence of the trench 112. In other words, an extending of the depleted layer can be terminated by disposing the trench 112, so as to avoid reaching the depleted layer to the end of the semiconductor chip. Accordingly, a leakage current generated from the cell region 60 along the direction toward the end of the semiconductor chip can be reduced.

Abstract: A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.

Abstract: A method for forming isolation structure for MOS transistor is disclosed, which includes forming a first photoresist layer over a sacrificed oxide layer of a semiconductor substrate, patterning the first photoresist layer to define a PMOS active region and a PMOS isolation region; implanting nitrogen ions into the PMOS isolation region through the sacrificed oxide layer by using the first photoresist layer as a mask; removing the first photoresist layer; forming a second photoresist layer over the sacrificed oxide layer, patterning the second photoresist layer to define a NMOS active region and a NMOS isolation region; implanting oxygen ions into the NMOS isolation region through the sacrificed oxide layer by using the second photoresist layer as a mask; removing the second photoresist layer and the sacrificed oxide layer; and annealing the semiconductor substrate to form isolation structures of PMOS and NMOS, respectively.

Abstract: A pad oxide layer is formed on a substrate. A pad nitride layer is formed on the pad oxide layer. The pad nitride layer and the pad oxide layer are patterned. Predetermined portions of the substrate are etched using the pad nitride layer as an etch barrier to thereby form trenches used as device isolation regions. The trenches are filled with an insulation layer to thereby form device isolation regions. The pad nitride layer is removed. Recesses are formed by etching predetermined portions of the pad oxide layer and the substrate. The pad oxide layer is removed. A gate oxide layer is formed on the recesses and on the substrate. Gate structures of which bottom portions are buried in the recesses on the gate oxide layer are formed.

Abstract: A semiconductor structure includes a semiconductor substrate; a planar transistor on a first portion of the semiconductor substrate, wherein the first portion of the semiconductor substrate has a first top surface; and a multiple-gate transistor on a second portion of the semiconductor substrate. The second portion of the semiconductor substrate is recessed from the first top surface to form a fin of the multiple-gate transistor. The fin is electrically isolated from the semiconductor substrate by an insulator.

Abstract: An implanter provides two-dimensional scanning of a substrate relative to an implant beam so that the beam draws a raster of scan lines on the substrate. The beam current is measured at turnaround points off the substrate and the current value is used to control the subsequent fast scan speed so as to compensate for the effect of any variation in beam current on dose uniformity in the slow scan direction. The scanning may produce a raster of non-intersecting uniformly spaced parallel scan lines and the spacing between the lines is selected to ensure appropriate dose uniformity.

Abstract: A method in which a SOI substrate structure is fabricated by oxidation of graded porous Si is provided. The graded porous Si is formed by first implanting a dopant (p- or n-type) into a Si-containing substrate, activating the dopant using an activation anneal step and then anodizing the implanted and activated dopant region in a HF-containing solution. The graded porous Si has a relatively coarse top layer and a fine porous layer that is buried beneath the top layer. Upon a subsequent oxidation step, the fine buried porous layer is converted into a buried oxide, while the coarse top layer coalesces into a solid Si-containing over-layer by surface migration of Si atoms.

Abstract: Embodiments relate to the lowered reliability of a device due to deterioration caused by the concentration of an electric field in the top corner of an STI. To solve the reliability problem, the STI top corners have a local oxidation of silicon, the top corners of the STI are rounded, and the STI steps are increased in a semiconductor device fabricated according to embodiments. Embodiments relate to an STI in high and low voltage regions of a semiconductor device which can be fabricated by providing a semiconductor substrate having a shallow trench isolation structure, a high voltage region and a low voltage region. A capping layer is formed over the entire surface of the top of the high voltage region and the low voltage region, including the shallow trench isolation structure. A photoresist pattern is formed over the top of the capping layer to expose the high voltage region, including a portion of the shallow trench isolation structure formed within the high voltage region.

Abstract: Hetero-semiconductor structures possessing an SOI structure containing a silicon-germanium mixed crystal are produced at a low cost and high productivity. The semiconductor substrates comprise a first layer formed of silicon having germanium added thereto, a second layer formed of an oxide and adjoined to the first layer, and a third layer derived from the same source as the first layer, but having an enriched content of germanium as a result of thermal oxidation and thinning of the third layer.

Abstract: A semiconductor device includes a first insulating isolation film provided on a main surface of a semiconductor substrate, an active region surrounded by the first insulating isolation film, and a second insulating isolation film provided on the main surface of the semiconductor substrate, having a thickness smaller than that of the first insulating isolation film and separating the active region into a first active region and a second active region.

Abstract: To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form an buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.

Abstract: Disclosed is a method for manufacturing a semiconductor device. The method includes the steps of forming an insulating layer on a substrate, partially exposing the substrate by selectively etching the insulating layer, implanting ions into the exposed substrate using the etched insulating layer as an ion implantation mask, and removing the etched insulating layer from the ion-implanted substrate.

Abstract: A method for fabricating a trench isolation structure wherein a trench is formed in a silicon body and an oxide layer is formed in the trench. The silicon body is exposed at the bottom of the trench by means of an etching step, and silicon oxide is selectively grown on the silicon exposed at the bottom of the trench, the silicon oxide being grown from the bottom of the trench toward an upper edge of the trench.

Abstract: A phase change material is formed over a dielectric material. An impurity is introduced into the dielectric to improve the adherence of said dielectric to said phase change material.

Abstract: A method of fabricating a semiconductor device having a silicon layer disposed on an insulating film. Oxygen ions are implanted into selected parts of the silicon layer, which are then oxidized to form isolation regions dividing the silicon layer into a plurality of mutually isolated active regions. As the oxidation process does not create steep vertical discontinuities, fine patterns can be formed easily on the combined surface of the active and isolation regions. The implanted oxygen ions cause oxidation to proceed quickly, finishing before a pronounced bird's beak is formed. The isolation regions themselves can therefore be narrow and finely patterned.

Abstract: A method of isolating semiconductor devices including forming a pad layer on a semiconductor substrate, forming a trench by etching the semiconductor substrate to a predetermined depth using the pad layer as an etch barrier, implanting ion impurities into a bottom of the trench so as to increase an oxidation rate thereat, performing heat treatment for activating ion implanted impurities, growing a liner oxide film on a bottom and a sidewall of the trench, forming an isolation film on the liner oxide film so as to fill the trench, and smoothing the isolation film.

Abstract: Methods of reducing a short channel phenomena for an NMOS device formed in an SOI layer, wherein the short channel phenomena is created by boron movement from a channel region to adjacent insulator regions, has been developed. A first embodiment of this invention entails the formation of a boron or nitrogen doped insulator layer located underlying the NMOS device. This is accomplished via formation of shallow trench openings in composite silicon nitride-silicon shapes, followed by lateral pull back of the silicon nitride shapes exposing portions of the top surface of the silicon shapes, followed by implantation of boron or nitrogen ions into portions of the insulator layer exposed in the STI openings and into portions of the insulator layer underlying exposed portions of the silicon shapes. A subsequent hydrogen anneal procedure finalizes the doped insulator layer which alleviates boron segregation from an overlying NMOS channel region.

Abstract: Process for forming dual gate oxides for DRAMS by incorporating different thicknesses of gate oxides by using nitrogen implantation. Either angled nitrogen implantation or nitride spacers is used to create a “shadow effect” or area, which limits the nitrogen dose close to the edges of the active area. The reduction of nitrogen dose leads to an increased gate oxide thickness at the active area (AA) adjacent to the shallow trench, increases the threshold of the parasitic corner device and reduces sub Vt (threshold voltage) and junction leakage.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor layer on a substrate. The first region of the substrate is expanded to push up the first portion of the semiconductor layer, thereby applying tensile stress to the first portion. The second region of the substrate is compressed to pull down the second portion of the semiconductor layer, thereby applying compressive stress to the second portion. An N type device is formed over the first portion of the semiconductor layer, and a P type device is formed over the second portion of the semiconductor layer.

Abstract: Disclosed are an SOI substrate and a method for manufacturing the same. The SOI substrate comprises a silicon substrate including an active region defined by a field region. The field region includes a first oxygen-ion-injected isolation region having a first thickness and being formed under the active region. The center of the first region is at a first depth from a top surface of the silicon substrate. The field region of the SOI substrate further includes a second oxygen-ion-injected region having a second thickness greater than the first thickness. The second region is formed at sides of the active region and is also formed from a top surface of the silicon substrate. The center of the second ion injected region is at a second depth from the top surface of the silicon substrate. The first and second ion injected regions surround the active region for device isolation. The SOI substrate is formed by implementing two sequential ion injecting processes.

Abstract: The aim of the invention is a method for producing a layer (2) of a first material embedded in a substrate (1) comprising at least one second material. The method comprises the following stages: formation in the substrate (1), at the level of the desired embedded layer, of a layer of microcavities intended to serve as centers of nucleation to produce said first material in said second material, formation of precipitate embryos from the nucleation centers formed, the precipitate embryos corresponding to the first material, growth of the precipitates from the embryos through species concentration corresponding to the first material and carried to the microcavity layer.

Abstract: Within a method for forming a microelectronic fabrication, there is ion implanted into a corner of a topographic feature within a microelectronic substrate a dose of an implanting ion such as to effect rounding of the corner of the topographic feature when thermally oxidizing the microelectronic substrate. The dose of the implanting ion is implanted while employing a laterally etched mask layer as an ion implantation mask layer which exposes the corner. The dose of the implanting ion is selected from the group consisting of silicon containing ions, germanium containing ions, arsenic containing ions, phosphorus containing ions and boron containing ions, such to provide for rounding of the corner with enhanced process efficiency.

Abstract: An OLED device having pillars with cross section that is wider on the top. The pillars structure a conductive layer during deposition into distinct portions located between the pillars and on the top of the pillars. In one embodiment, the grooves between the pillars extend outside the electrode region to prevent shorting of adjacent electrodes.

Abstract: Semiconductor devices and methods for manufacturing the same in which deterioration of the electrical characteristic is suppressed are described. One method for manufacturing a semiconductor device includes the steps of: forming a first polysilicon layer 32 on a gate dielectric layer 20; forming a silicon nitride layer 92 on the first polysilicon layer 32; forming a second polysilicon layer 94 on the silicon nitride layer 92; forming sidewall spacers; forming an insulation layer 60 that covers the second polysilicon layer 94; planarizing the insulation layer 60 until an upper surface of the second polysilicon layer 94 is exposed; removing the second polysilicon layer 94; removing the silicon nitride layer 92 to form a recessed section 80; and filling a metal layer 34 in the recessed section 80 to form a gate electrode 30 that includes at least the first polysilicon layer 32 and the metal layer 34.

Abstract: Disclosed are an SOI substrate and a method for manufacturing the same. The SOI substrate comprises a silicon substrate including an active region defined by a field region. The field region includes a first oxygen-ion-injected isolation region having a first thickness and being formed under the active region. The center of the first region is at a first depth from a top surface of the silicon substrate. The field region of the SOI substrate further includes a second oxygen-ion-injected region having a second thickness greater than the first thickness. The second region is formed at sides of the active region and is also formed from a top surface of the silicon substrate. The center of the second ion injected region is at a second depth from the top surface of the silicon substrate. The first and second ion injected regions surround the active region for device isolation. The SOI substrate is formed by implementing two sequential ion injecting processes.

Abstract: The present invention relates to a method for forming an isolation film for semiconductor devices.

Abstract: Forming a vertical MOS transistor or making another three-dimensional integrated circuit structure in a silicon wafer exposes planes having at least two different crystallographic orientations. Growing oxide on different crystal planes is inherently at different growth rates because the inter-atomic spacing is different in the different planes. Heating the silicon in a nitrogen-containing ambient to form a thin layer of nitride and then growing the oxide through the thin nitrided layer reduces the difference in oxide thickness to less than 1%.

Abstract: A method of forming a BiCMOS device having a deep subcollector region and self-aligned alignment marks is provided. The inventive method includes the steps of: (a) lithographically forming a first patterned layer comprising a thick dielectric material on a surface of a material stack formed on a semiconductor substrate, the first patterned layer including at least one opening therein and the semiconductor substrate having at least an alignment area; (b) performing a high-energy/high-dose implant through the at least one opening and the material stack so as to form at least one deep subcollector region in the semiconductor substrate; (c) lithographically forming a second patterned layer (photoresist or dielectric) predominately outside the first patterned layer in the alignment area; and (d) etching through the material stack to form alignment marks in the underlying semiconductor substrate using the first patterned layer as an alignment mark mask.

Abstract: Disclosed is a semiconductor device having a reduced size, increased accuracy, and flattened element isolation regions with an decreased size. A plurality of MOSFETs having gate oxide films with different thicknesses and element isolation regions are formed by a manufacturing method employing oxygen implantation. An oxygen-ion implantation process and an annealing process are applied to a method of manufacturing the semiconductor device.

Abstract: A method of fabricating a silicon-on-insulator (SOI) substrate including at least one patterned buried oxide region having well defined edges is provided. The method includes a step of implanting first ions into a surface of a Si-containing substrate so as to form an implant region of the first ions in the Si-containing substrate. Following the first implant step, a selective implant process is employed wherein second ions that are insoluble in SiO2 are incorporated into portions of the Si-containing substrate. The second ions employed in the selective implant step are capable of preventing the implant region of first ions from forming an oxide region during a subsequent annealing step. An annealing step is then performed which causes formation of a buried oxide region in the implant region of first ions that does not include the second ions.

Abstract: A shallow trench isolated integrated circuit may be formed by creating an oxidation enhancing region at the corner between a semiconductor structure surface and the trench. This region may be formed by ion implantation or solid source diffusion in a way which decreases crystallographic defects. As a result, oxidation at the trench may be enhanced without adverse effects on leakage currents. In some embodiments, the impurity laden region is formed first and the trench is etched through the region leaving an impurity laden remnant at the corner between the trench and the structure surface.

Abstract: An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

Abstract: The present invention provides a method of forming different thickness” of a gate oxide layer simultaneously, by employing a pulse Nitrogen plasma implantation. The method provides a semiconductor substrate with the surface of the silicon in the semiconductor substrate separated into a first region and a second region at least. Then a thin surface on the surface of the silicon of the first region is implanted using a first predetermined concentration of the Nitrogen ions. The thin surface on the surface of the silicon in the second region is implanted using a second predetermined concentration of the Nitrogen ions. An oxidation process is subsequently performed. The first predetermined thickness and the second predetermined thickness of the silicon oxide layer are formed simultaneously on the surface of the silicon in the first region and in the second region. The Nitrogen ions are implanted in the surface of the silicon by forming the pulse nitrogen plasma in-situ.

Abstract: Within a local oxidation of silicon (LOCOS) method for forming a silicon oxide isolation region, there is first amorphized areally completely at least a surface sub-layer portion of a silicon layer within an isolation region location within the silicon layer defined by an oxidation mask layer formed over the silicon layer, to form an amorphized silicon region within the isolation region location. Thus, when thermally oxidizing the silicon layer having formed thereover the oxidation mask layer to form at least in part from the amorphized silicon region a silicon oxide isolation region, the silicon oxide isolation region is formed with an attenuated bird's beak extension.

Abstract: The present invention relates to the formation of multiple gettering structures within a semiconductive substrate by ion implantation through recesses in the semiconductive substrate. A preferred embodiment of the present invention includes forming the recesses by using a reactive anisotropic etching medium, followed by implanting a gettering material. The gettering material is implanted by changing the gettering material for the reactive anisotropic etching medium. An advantage of the method of the present invention is that gettering structures are formed without the cost of an extra masking procedure and without the expense of MeV implantation equipment and procedures. As a result, metallic contaminants will not move as freely through the semiconductive substrate in the region of an active area proximal to the gettering structures.

Abstract: There is described a method for manufacturing a semiconductor device, in which an isolation oxide film having a superior dimensional accuracy and an isolation oxide film of a high withstanding voltage are manufactured in simple processes. A semiconductor device including a plurality of isolation oxide films of different thickness is manufactured. A nitride film and a resist film are grown on a silicon substrate, and openings are formed in the resist film. Openings are formed in the nitride film while the resist film is used as a mask. Isolation oxide films are formed below the openings through thermal oxidation. An opening diameter of the large opening formed in the nitride film is set to a value of more than 0.6 &mgr;m, whereas an opening diameter of the smaller opening is set a predetermined value of less than 0.6 &mgr;m. More specifically, the removal value of the smaller opening is set to a value required for imparting a desired thickness to the isolation oxide film 42.

Abstract: A method for fabricating polycrystalline silicon film is to add a semitransparent film between a substrate and silicon film. When using the laser to light to the silicon film, the semitransparent film absorbs a portion of laser energy and thus the semitransparent film keeps in high temperature during solidification of silicon film. The silicon film will keep molten for a long time and therefore have more time for crystal grain growth. The crystal grain size of polycrystalline silicon film in this method is much larger than normal substrate heating method.