Abstract: An SCR-type component of vertical structure has a main upper electrode formed on a silicon region of a first conductivity type which is formed in a silicon layer of a second conductivity type. The silicon region is interrupted in first areas where the material of the silicon layer comes into contact with the upper electrode, and is further interrupted in second areas filled with resistive porous silicon extending between the silicon layer and the main upper electrode.

Abstract: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.

Abstract: A package stack structure includes a lower semiconductor chip on a lower package substrate having a plurality of lower via plug lands, a lower package having a lower molding compound surrounding a portion of a top surface of the lower package substrate and side surfaces of the lower semiconductor chip, an upper semiconductor chip on an upper package substrate having a plurality of upper via plug lands, an upper package having an upper molding compound covering the upper semiconductor chip, via plugs vertically penetrating the lower molding compound, the via plugs connecting the lower and upper via plug lands, respectively, and a fastening element and an air space between a top surface of the lower molding compound and a bottom surface of the upper package substrate.

Abstract: A method of fabricating an electrically conductive mechanical interconnection element (12) comprises: a first stage of electrochemically depositing a structure comprising a plurality of metal wires (2a) of sub-micrometric diameter projecting from the likewise metallic surface of a substrate (2); and a second stage of controlled partial dissolution of said wires to reduce their diameter. A method of making a mechanical and/or electrical interconnection, the method comprising the steps consisting in: fabricating two interconnection elements by a method as described above; and placing said interconnection elements face to face and pressing one against the other so as to cause the nanometric wires projecting from the surfaces of said elements to interpenetrate and tangle together. A three-dimensional electronic device comprising a stack of microelectronic chips mechanically and electrically connected to one another by such interconnection elements.

Abstract: A method and intermediate product for structuring a substrate is disclosed. At least one seed layer including a first metal compound is positioned at least partially on the substrate. The seed layer is subjected to a solution comprising ions of a second metal compound. The ions are reduced in the solution by reduction means so that the second metal compound is deposited as mask layer on the seed layer.

Abstract: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.

Abstract: A semiconductor substrate shaped to have a curved surface profile by anodization. Prior to being anodized, the substrate is finished with an anode pattern on its bottom surface so as to be consolidated into a unitary structure in which the anode pattern is precisely reproduced on the substrate. The anodization utilizes an electrolytic solution which etches out an oxidized portion as soon as it is formed as a result of the anodization, to thereby develop a porous layer in a pattern in match with the anode pattern. The anode pattern brings about an in-plane distribution of varying electric field intensity by which the porous layer develops into a shape complementary to a desired surface profile. Upon completion of the anodization, the curves surface is revealed on the surface of the substrate by etching out the porous layer and the anode pattern from the substrate.

Abstract: A method of fabricating silicon-on-insulators (SOIs) having a thin, but uniform buried oxide region beneath a Si-containing over-layer is provided. The SOI structures are fabricated by first modifying a surface of a Si-containing substrate to contain a large concentration of vacancies or voids. Next, a Si-containing layer is typically, but not always, formed atop the substrate and then oxygen ions are implanted into the structure utilizing a low-oxygen dose. The structure is then annealed to convert the implanted oxygen ions into a thin, but uniform thermal buried oxide region.

Abstract: A method in which a SOI substrate structure is fabricated by oxidation of graded porous Si is provided. The graded porous Si is formed by first implanting a dopant (p- or n-type) into a Si-containing substrate, activating the dopant using an activation anneal step and then anodizing the implanted and activated dopant region in a HF-containing solution. The graded porous Si has a relatively coarse top layer and a fine porous layer that is buried beneath the top layer. Upon a subsequent oxidation step, the fine buried porous layer is converted into a buried oxide, while the coarse top layer coalesces into a solid Si-containing over-layer by surface migration of Si atoms.

Abstract: The invention relates to a method of forming an isolation layer in a flash memory device and comprises providing a semiconductor substrate in which a tunnel insulating layer and a conductive layer are formed on an active region and a trench is formed on an isolation region; forming a first insulating layer in a lower portion of the trench; forming a second insulating layer on the semiconductor substrate and the first insulating layer including the trench to protect a side wall of the conductive layer; forming a third insulating layer in the trench to form an isolation layer; and adjusting an effective field height (EFH) of the isolation layer through a first etching process.

Abstract: A method for producing a dielectric layer on a substrate made of a conductive substrate material includes reducing a leakage current that flows through defects of the dielectric layer at least by a self-aligning and self-limiting electrochemical conversion of the conductive substrate material into a nonconductive substrate follow-up material in sections of the substrate that are adjacent to the defects. Also provided is a configuration including a dielectric layer with defects, a substrate made of a conductive substrate material, and reinforcement regions made of the nonconductive substrate follow-up material in sections adjacent to the defects.

Abstract: A method in which a recess is formed in the surface of a semiconductor substrate and a material is grown on the inner wall of the recess, includes the steps of producing an electrically insulating layer on the surface of the substrate outside the recess, and selectively growing the material on the inner wall of the recess as a result of the substrate, as an electrode, being brought into contact with an electrolysis liquid and electrolysis being carried out, during which the insulating layer prevents the material from growing outside the recess. Before the electrolysis is carried out, a reserve material is epitaxially deposited on the inner wall of the recess and, during the electrolysis, the reserve material is converted into the material being grown by electrolysis.

Abstract: A method of fabricating a nitride read only memory. A trapping dielectric sandwiched structure, including an insulation layer, a charge trap layer and an insulation layer, is formed on a substrate. An opening with indented sidewalls is formed in the insulation layer. A thermal oxide layer is formed to fill the opening, such that the indented sidewalls are completely sealed. The charge trap layer is thus sealed by the insulation layers and the thermal oxide layer to avoid the direct contact between the control gate and the charge trap layer, so as to prevent the data loss.

Abstract: In a process for the electrochemical oxidation of a semiconductor substrate that has recesses, such as for example, capacitor trenches or mesopores, formed in a silicon surface region, self-limited oxide formation takes place. The end of this formation is reached as a function of the process parameters such as the doping of the silicon region, the applied voltage and the composition of the electrolyte used, as soon as either a predetermined maximum layer thickness of the formed oxide or a predetermined minimum residual silicon layer thickness between two adjacent recesses is reached. The self-limiting is achieved either as a result of the overall voltage applied over the silicon oxide layer, which has already formed, dropping or as a result of the space charge regions of adjacent recesses coming into contact with one another.

Abstract: In one aspect, the invention includes a method of semiconductive wafer processing comprising forming a silicon nitride layer over a surface of a semiconductive wafer, the silicon nitride layer comprising at least two portions, one of said at least two portions generating a compressive force against the other of the at least two portions, and the other of the at least two portions generating a tensile force against the one of the at least two portions.

Abstract: A method for fabricating a semiconductor device, in accordance with the present invention, includes the steps of providing a semiconductor wafer having exposed p-doped silicon regions and placing the wafer in an electrochemical cell such that a solution including electrolytes interacts with the exposed p-doped silicon regions to form an oxide on the exposed p-doped silicon regions when a potential difference is provided between the wafer and the solution.

Abstract: A method for electrochemical local oxidation of silicon of selected regions of a silicon substrate of a semiconductor wafer avoids the formation of bird's beak structures of the prior art. The method involves the initial formation of a patterned generally non-conductive layer such as silicon nitride on a silicon substrate of a semiconductor wafer. The semiconductor wafer is then immersed in a bath of oxidizing electrolyte solutions such as pure water, acid, or ammonium. While immersed, the semiconductor wafer is subjected to an electrical field. The electrical field is created by connecting a power source both to a cathode located within the bath and to the semiconductor wafer, thereby employing the semiconductor wafer as an anode. The electrical field causes the oxygen of the bath to react with the silicon substrate and form patterned oxide regions in the locations where the silicon substrate was left unmasked by the patterned generally non-conductive layer.

Abstract: A method for electrochemical local oxidation of silicon of selected regions of a silicon substrate of a semiconductor wafer avoids the formation of bird's beak structures of the prior art. The method involves the initial formation of a patterned generally nonconductive layer such as silicon nitride on a silicon substrate of a semiconductor wafer. The semiconductor wafer is then immersed in a bath of oxidizing electrolyte solutions such as pure water, acid, or ammonium. While immersed, the semiconductor wafer is subjected to an electrical field. The electrical field is created by connecting a power source both to a cathode located within the bath and to the semiconductor wafer, thereby employing the semiconductor wafer as an anode. The electrical field causes the oxygen of the bath to react with the silicon substrate and form patterned oxide regions in the locations where the silicon substrate was left unmasked by the patterned generally non-conductive layer.

Abstract: A method for forming field isolation regions in multilayer semiconductor devices comprises the steps of masking active regions of the substrate, forming porous silicon in the exposed field isolation regions, removing the mask and oxidizing the substrate. A light ion impurity implant is used to create pores in the substrate. Substrate oxidation proceeds by rapid thermal annealing because the increased surface area of the pores and the high reactivity of unsaturated bonds on these surfaces provides for enhanced oxidation.

Abstract: A semiconductor substrate and a method of fabricating the same, and provides which the active area to be formed the active element is defined by the trench filled with any conductive polycrystal silicon in which any portion of a large number of the epitaxial layer is crystally grown on any conductive silicon substrate, and the multi-aperture silicon oxide layer is formed from the metal line to be used to the passive element or the transmitting line outside the trench, so that the interference between the passive element and the semiconductor substrate is prevented, and to attenuate the transmitting signal prevents to be attenuated in the high frequency band operation. Therefore, the semiconductor substrate for a unit active element and the MMIC to be able to operate the high frequency band is manufactured into the silicon, and thus it is advantageous to reduce the cost and enhance the yield.