Dopant Introduction Into Semiconductor Region Patents (Class 438/45)
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Patent number: 12256636Abstract: A light-emitting device includes: a first electrode; a second electrode facing the first electrode; and an interlayer between the first electrode and the second electrode and including a first layer, wherein the first electrode has a work function value of about ?5.5 eV to about ?6.1 eV, and the interlayer includes a second layer doped with a non-lead-based perovskite compound.Type: GrantFiled: December 7, 2021Date of Patent: March 18, 2025Assignee: Samsung Display Co., Ltd.Inventors: Heechang Yoon, Dongchan Kim, Yoonseok Ka, Jiyoung Moon, Haemyeong Lee, Yoonhyeung Cho
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Patent number: 12249672Abstract: In an embodiment a method for manufacturing a semiconductor device include providing a growth substrate, depositing an n-doped first layer, depositing an active region on the n-doped first layer, depositing a second layer onto the active region, depositing magnesium (Mg) in the second layer and subsequently to depositing Mg, depositing zinc (Zn) in the second layer such that a concentration of Zn in the second layer decreases from a first value to a second value in a first area of the second layer adjacent to the active region, the first area being in a range of 5 nm to 200 nm.Type: GrantFiled: May 19, 2020Date of Patent: March 11, 2025Assignee: OSRAM Opto Semiconductors GmbHInventors: Philipp Kreuter, Andreas Biebersdorf, Christoph Klemp, Jens Ebbecke, Ines Pietzonka, Petrus Sundgren
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Patent number: 12206048Abstract: The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, an integrated circuit includes a field effect transistor (FET) and a waveguide coupled to the FET, wherein the waveguide comprises a signal conductor. The FET can include: a substrate comprising a first oxide material; an epitaxial semiconductor layer on the substrate, the epitaxial semiconductor layer comprising a second oxide material with a first bandgap; a gate layer on the epitaxial semiconductor layer, the gate layer comprising a third oxide material with a second bandgap, wherein the second bandgap is wider than the first bandgap; and electrical contacts. The electrical contacts can include: a source electrical contact coupled to the epitaxial semiconductor layer; a drain electrical contact coupled to the epitaxial semiconductor layer; and a first gate electrical contact coupled to the gate layer.Type: GrantFiled: October 3, 2023Date of Patent: January 21, 2025Assignee: Silanna UV Technologies Pte LtdInventor: Petar Atanackovic
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Patent number: 12125944Abstract: A light emitting diode includes an n-type semiconductor layer including a pit structure formed therein, active layers grown only on sidewalls of the pit structure and configured to emit light, and a p-type semiconductor layer on the active layers and at least partially in the pit structure. In one embodiment, the pit structure is characterized by a shape of an inverted pyramid. The pit structure is formed in the n-type semiconductor layer by, for example, etching the n-type semiconductor layer using an etch mask layer having apertures with slanted sidewalls, or growing the n-type semiconductor layer on a substrate through a mask layer having an array of apertures.Type: GrantFiled: October 25, 2021Date of Patent: October 22, 2024Assignee: META PLATFORMS TECHNOLOGIES, LLCInventors: Wei Sin Tan, Andrea Pinos, Xiang Yu, Samir Mezouari
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Patent number: 12125946Abstract: The present disclosure describes methods and epitaxial oxide devices with impact ionization. A method can comprise: applying a bias across a semiconductor structure using a first electrical contact and a second electrical contact; injecting a hot electron, from the first electrical contact, through a second semiconductor layer, and into a conduction band of a first epitaxial oxide material; and forming an excess electron-hole pair in an impact ionization region of the first semiconductor layer via impact ionization. The semiconductor structure can comprise: the first electrical contact; the first semiconductor layer with the first epitaxial oxide material with a first bandgap coupled to the first electrical contact; a second semiconductor layer with a second epitaxial oxide material with a second bandgap coupled to the first semiconductor layer; and a second electrical contact coupled to the second semiconductor layer, wherein the second bandgap is wider than the first bandgap.Type: GrantFiled: May 23, 2022Date of Patent: October 22, 2024Assignee: Silanna UV Technologies Pte LtdInventor: Petar Atanackovic
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Patent number: 12125947Abstract: A light emitting device includes n columnar parts, and an electrode configured to inject an electrical current into the n columnar parts, wherein each of the n columnar parts includes a first semiconductor layer, a second semiconductor layer different in conductivity type from the first semiconductor layer, and a light emitting layer disposed between the first semiconductor layer and the second semiconductor layer, when viewed from a stacking direction of the first semiconductor layer and the light emitting layer, p first columnar parts out of the n columnar parts fail to overlap an outer edge of the electrode, q second columnar parts out of the n columnar parts overlap the outer edge of the electrode, a number of the second columnar parts centers of which overlap the electrode out of the q second columnar parts is larger than a number of the second columnar parts centers of which fail to overlap the electrode, and n=p+q is fulfilled.Type: GrantFiled: December 17, 2021Date of Patent: October 22, 2024Assignee: SEIKO EPSON CORPORATIONInventors: Takafumi Noda, Yoji Kitano
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Patent number: 12080823Abstract: Diffusion-based and ion implantation-based methods are provided for fabricating planar photodetectors. The methods may be used to fabricate planar photodetectors comprising type II superlattice absorber layers but without mesa structures. The fabricated planar photodetectors exhibit high quantum efficiencies, low dark current densities, and high specific detectivities as compared to photodetectors having mesa structures.Type: GrantFiled: March 17, 2023Date of Patent: September 3, 2024Assignee: Northwestern UniversityInventor: Manijeh Razeghi
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Patent number: 12068579Abstract: A semiconductor laser includes an active region, a first distributed-Bragg-reflector region disposed contiguously with the active region, and a second distributed-Bragg-reflector region. The first distributed-Bragg-reflector region is formed contiguously with one side of the active region in a waveguide direction and includes a first diffraction grating. The second distributed-Bragg-reflector region is formed contiguously with to the other side of the active region in the waveguide direction and includes a second diffraction grating. The first diffraction grating includes recessed portions formed through a diffraction grating layer formed in the first distributed-Bragg-reflector region and convex portions adjacent to the recessed portions. The diffraction grating layer is made of a dielectric material.Type: GrantFiled: December 2, 2019Date of Patent: August 20, 2024Assignee: Nippon Telegraph and Telephone CorporationInventors: Erina Kanno, Koji Takeda, Takaaki Kakitsuka, Shinji Matsuo
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Patent number: 11887817Abstract: The disclosed plasma processing apparatus is provided with a chamber, a substrate support, and a power source system. The substrate support has an electrode and configured to support a substrate in the chamber. The power source system is electrically connected to the electrode and configured to apply a bias voltage to the electrode to draw ions from a plasma in the chamber into the substrate on the substrate support. The power source system is configured to output a first pulse to the electrode in a first period and output a second pulse to the electrode in a second period after the first period, as the bias voltage. Each of the first pulse and the second pulse is a pulse of a voltage. A voltage level of the first pulse is different from a voltage level of the second pulse.Type: GrantFiled: April 16, 2021Date of Patent: January 30, 2024Assignee: Tokyo Electron LimitedInventor: Koichi Nagami
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Patent number: 11624973Abstract: A light emitting device includes a substrate, a first semiconductor layer provided to the substrate, a laminated structure disposed at an opposite side to the substrate of the first semiconductor layer, and including a plurality of columnar parts, a first electrically-conductive layer as a surface layer at laminated structure side in the first semiconductor layer, and a second electrically-conductive layer opposed to the first electrically-conductive layer via the laminated structure, wherein the columnar part includes a light emitting layer configured to emit light, a second semiconductor layer which is disposed between the light emitting layer and the first electrically-conductive layer, and a third semiconductor layer disposed between the light emitting layer and the second electrically-conductive layer, concavo-convex shapes are formed on a surface of the first electrically-conductive layer, an insulating layer is disposed on the first electrically-conductive layer, and electrode layers are disposed so asType: GrantFiled: September 28, 2020Date of Patent: April 11, 2023Inventor: Takashi Miyata
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Patent number: 11611011Abstract: An improved heterostructure for an optoelectronic device is provided. The heterostructure includes an active region, an electron blocking layer, and a p-type contact layer. The heterostructure can include a p-type interlayer located between the electron blocking layer and the p-type contact layer. In an embodiment, the electron blocking layer can have a region of graded transition. The p-type interlayer can also include a region of graded transition.Type: GrantFiled: October 1, 2020Date of Patent: March 21, 2023Assignee: Sensor Electronic Technology, Inc.Inventors: Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur
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Patent number: 11569636Abstract: A light emitting device includes a substrate, a laminated structure provided to the substrate, and including a plurality of columnar parts, and an electrode disposed at an opposite side to the substrate of the laminated structure, wherein the columnar parts have a light emitting layer, the columnar parts are disposed between the electrode and the substrate, light generated in the light emitting layer propagates through the plurality of columnar parts to cause laser oscillation, and the electrode is provided with a hole.Type: GrantFiled: June 26, 2020Date of Patent: January 31, 2023Inventor: Takashi Miyata
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Patent number: 11569469Abstract: A light emitting device, a method of manufacturing the same, and a display device including the same are disclosed. The light emitting device including a first electrode and a second electrode facing each other, an emission layer disposed between the first electrode and the second electrode, the emission layer including quantum dots, and a charge auxiliary layer disposed between the emission layer and the second electrode, wherein the emission layer includes a first surface facing the charge auxiliary layer and an opposite second surface, the quantum dots include a first organic ligand on a surface of the quantum dots, in the emission layer, an amount of the first organic ligand in a portion adjacent to the first surface is larger than an amount of the first organic ligand in a portion adjacent to the second surface.Type: GrantFiled: March 18, 2021Date of Patent: January 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae Young Chung, Kwanghee Kim, Hongkyu Seo, Eun Joo Jang, Oul Cho, Tae Hyung Kim, Yuho Won, Hee Jae Lee
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Patent number: 11508875Abstract: To provide a bonding-type semiconductor light-emitting device which has excellent reliabilities with smaller time deviations of the light output power and the forward voltage. A semiconductor light-emitting device 100 according to the present disclosure includes a conductive support substrate 80; a metal layer 60 containing a reflective metal provided on the conductive support substrate 10; a semiconductor laminate 30 formed from a stack of a plurality of InGaAsP group III-V compound semiconductor layers containing at least In and P provided on the reflective metal layer 60; an n-type InGaAs contact layer 20A provided on the semiconductor laminate 30; and an n-side electrode 93 provided on the n-type InGaAs contact layer 20A, wherein the center emission wavelength of light emitted from the semiconductor laminate 30 is 1000 to 2200 nm.Type: GrantFiled: December 20, 2018Date of Patent: November 22, 2022Assignee: DOWA Electronics Materials Co., Ltd.Inventors: Jumpei Yamamoto, Tetsuya Ikuta
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Patent number: 11437255Abstract: A structure, comprising an island comprising a III-N material. The island extends over a substrate and has a sloped sidewall. A cap comprising a III-N material extends laterally from a top surface and overhangs the sidewall of the island. A device, such as a transistor, light emitting diode, or resonator, may be formed within, or over, the cap.Type: GrantFiled: September 27, 2017Date of Patent: September 6, 2022Assignee: Intel CorporationInventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul Fischer, Kevin Lin
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Patent number: 11355540Abstract: An optical device includes a first conductive layer, a first junction layer, a light absorption layer, a second junction layer, and a second conductive layer. The first junction layer is disposed on the first conductive layer. The light absorption layer is disposed on the first junction layer, wherein the light absorption layer includes a plurality of unit cells, each of the unit cells includes a plurality of pillar structures, and the pillar structures of each of the unit cells are different sizes. The second junction layer is disposed on the light absorption layer. The second conductive layer is disposed on the second junction layer.Type: GrantFiled: April 15, 2020Date of Patent: June 7, 2022Assignee: VISERA TECHNOLOGIES COMPANY LIMITEDInventors: Kuo-Feng Lin, Chin-Chuan Hsieh
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Patent number: 11258011Abstract: An RRAM structure and its manufacturing method are provided. The RRAM structure includes a bottom electrode layer, a resistance switching layer, and an implantation control layer sequentially formed on a substrate. The resistance switching layer includes a conductive filament confined region and an outer region surrounding the conductive filament confined region. The RRAM structure includes a protective layer and a top electrode layer. The protective layer conformally covers the bottom electrode layer, the resistance switching layer, and the implantation control layer and has a first opening. The top electrode layer is located on the implantation control layer, and a portion of the top electrode layer is filled into the first opening. The position of the top electrode layer corresponds to that of the conductive filament confined region, and the top surface of the top electrode layer is higher than that of the protective layer.Type: GrantFiled: June 26, 2020Date of Patent: February 22, 2022Assignee: WINBOND ELECTRONICS CORP.Inventors: Bo-Lun Wu, Po-Yen Hsu, Ting-Ying Shen, Meng-Hung Lin
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Patent number: 10873029Abstract: A vapor deposition mask preparation body in which a metal mask is provided on one surface of a resin plate for obtaining a resin mask, and a protective sheet with peel strength not less than about 0.0004 N/10 mm and less than about 0.2 N/10 mm in conformity with JIS Z-0237:2009 is provided on the other surface of the resin plate is prepared, with respect to the vapor deposition mask preparation body, the resin plate is irradiated with laser light from the metal mask side to form a resin mask opening corresponding to a pattern to be produced by vapor deposition in the resin plate, and the protective sheet is peeled off from the resin mask in which the resin mask opening corresponding to the pattern to be produced by vapor deposition is formed.Type: GrantFiled: April 7, 2020Date of Patent: December 22, 2020Assignee: Dai Nippon Printing Co., Ltd.Inventors: Toshihiko Takeda, Kumiko Hokari, Yasuko Sone, Katsunari Obata
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Patent number: 10396283Abstract: A vapor deposition mask preparation body in which a metal mask is provided on one surface of a resin plate for obtaining a resin mask, and a protective sheet with peel strength not less than about 0.0004 N/10 mm and less than about 0.2 N/10 mm in conformity with JIS Z-0237:2009 is provided on the other surface of the resin plate is prepared, with respect to the vapor deposition mask preparation body, the resin plate is irradiated with laser light from the metal mask side to form a resin mask opening corresponding to a pattern to be produced by vapor deposition in the resin plate, and the protective sheet is peeled off from the resin mask in which the resin mask opening corresponding to the pattern to be produced by vapor deposition is formed.Type: GrantFiled: June 29, 2016Date of Patent: August 27, 2019Assignee: Dai Nippon Printing Co., Ltd.Inventors: Toshihiko Takeda, Kumiko Hokari, Yasuko Sone, Katsunari Obata
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Patent number: 10131835Abstract: A phosphor composition is derived from combining K2SiF6:Mn4+ in solid form with a saturated solution of a manganese-free complex fluoride including a composition of formula I: A3[MF6], where A is selected from Na, K, Rb, and combinations thereof and M is selected from Al, Ga, In, Sc, Y, Gd, and combinations thereof. The composition of formula I: A3[MF6] has a water solubility lower than a water solubility of K2SiF6. A lighting apparatus including the phosphor composition is also provided.Type: GrantFiled: December 16, 2014Date of Patent: November 20, 2018Assignee: General Electric CompanyInventors: Anant Achyut Setlur, Robert Joseph Lyons, Prasanth Kumar Nammalwar, James Edward Murphy, Florencio Garcia, Ravikumar Hanumantha
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Patent number: 10032967Abstract: A phosphor comprising: a chemical composition expressed by the following formula (K1-p, Mp)a(Si1-y, Mny)Fb (M is at least one element selected from the group consisting of Na and Ca, and p satisfies 0?p?0.01, a satisfies 1.5?a?2.5, b satisfies 5.5?b?6.5, and y satisfies 0<y?0.1), Wherein the phosphor satisfies I (2,500-3,000)/I (1,200-1,240)<0.04, when I (1,200-1,240) is an intensity of a highest peak in a range of 1,200-1,240 cm?1 and I (2,500-3,000) is an intensity of a highest peak in a range of 2,500-3,000 cm?1 in an infrared spectrum.Type: GrantFiled: March 9, 2017Date of Patent: July 24, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Keiko Albessard, Ryosuke Hiramatsu, Kunio Ishida, Yasushi Hattori, Masahiro Kato
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Patent number: 10032758Abstract: According to one embodiment, at first, a compound semiconductor layer is bonded to a position straddling a plurality of chip formation regions arranged on a substrate. One of the chip formation regions has a first size, and the compound semiconductor layer has a second size smaller than the first size. Thereafter, the compound semiconductor layer is processed to provide compound semiconductor elements on the chip formation regions. Then, the substrate is divided to correspond to the chip formation regions.Type: GrantFiled: September 6, 2016Date of Patent: July 24, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoichiro Kurita, Hideto Furuyama, Hiroshi Uemura, Fumitaka Ishibashi
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Patent number: 9647036Abstract: Resistive RAM (RRAM) devices having increased uniformity and related manufacturing methods are described. Greater uniformity of performance across an entire chip that includes larger numbers of RRAM cells can be achieved by uniformly creating enhanced channels in the switching layers through the use of radiation damage. The radiation, according to various described embodiments, can be in the form of ions, electromagnetic photons, neutral particles, electrons, and ultrasound.Type: GrantFiled: January 29, 2016Date of Patent: May 9, 2017Inventors: Shih-Yuan Wang, Shih-Ping Wang
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Patent number: 9640722Abstract: A semiconducting structure configured to emit electromagnetic radiation. The structure includes a first zone and a second zone with first and second types of conductivities respectively opposite to each other, the first and second zones being connected to each other to form a semiconducting junction. The first zone includes at least a first and a second part, the first and the second parts being separated from each other by an intermediate layer, as a spreading layer, extending approximately parallel to a junction plane along a major part of the junction. The spreading layer can cause spreading of carriers in the plane of the spreading layer.Type: GrantFiled: January 21, 2014Date of Patent: May 2, 2017Assignee: Commissariat à l'énergie atomique et aux énergies alternativesInventor: David Vaufrey
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Patent number: 9515262Abstract: Resistive RAM (RRAM) devices having increased uniformity and related manufacturing methods are described. Greater uniformity of performance across an entire chip that includes larger numbers of RRAM cells can be achieved by uniformly creating enhanced channels in the switching layers through the use of radiation damage. The radiation, according to various described embodiments, can be in the form of ions, electromagnetic photons, neutral particles, electrons, and ultrasound.Type: GrantFiled: August 18, 2015Date of Patent: December 6, 2016Inventors: Shih-Yuan Wang, Shih-Ping Wang
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Patent number: 9306125Abstract: A light-emitting device, according to one embodiment, comprises: a light-emitting structure comprising a first conductive semiconductor layer, an active layer which is underneath the first conductive semiconductor layer, and a second conductive semiconductor layer which is underneath the active layer; a reflective electrode, which is arranged under the light-emitting structure; and an electrode which is arranged inside the first conductive semiconductor layer and comprises a conductive ion injection layer.Type: GrantFiled: May 24, 2013Date of Patent: April 5, 2016Assignee: LG INNOTEK CO., LTD.Inventor: Hwan Hee Jeong
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Patent number: 9236548Abstract: A light-emitting device comprises an active-region sandwiched between an n-type layer and a p-type layer, that allows lateral carrier injection into the active-region so as to reduce heat generation in the active-region and to minimize additional forward voltage increase associated with bandgap discontinuity. In some embodiments, the active-region is a vertically displaced multiple-quantum-well (MQW) active-region. A method for fabricating the same is also provided.Type: GrantFiled: March 18, 2013Date of Patent: January 12, 2016Assignee: INVENLUX CORPORATIONInventors: Chunhui Yan, Jianping Zhang, Ying Liu, Fanghai Zhao
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Patent number: 9236528Abstract: The present invention provides an electronic apparatus, such as a lighting device comprised of light emitting diodes (LEDs) or a power generating apparatus comprising photovoltaic diodes, which may be created through a printing process, using a semiconductor or other substrate particle ink or suspension and using a lens particle ink or suspension. An exemplary apparatus comprises a base; at least one first conductor; a plurality of substantially spherical or optically resonant diodes coupled to the at least one first conductor; at least one second conductor coupled to the plurality of diodes; and a plurality of substantially spherical lenses suspended in a polymer attached or deposited over the diodes. The lenses and the suspending polymer have different indices of refraction. In some embodiments, the lenses and diodes have a ratio of mean diameters or lengths between about 10:1 and 2:1.Type: GrantFiled: February 9, 2013Date of Patent: January 12, 2016Assignee: NthDegree Technologies Worldwide IncInventors: William Johnstone Ray, Mark D. Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
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Patent number: 9034670Abstract: A method (100; 100a; 100b; 100c) for manufacturing a solar cell from a semiconductor substrate (1) of a first conductivity type, the semiconductor substrate having a front surface (2) and a back surface (3). The method includes in a sequence: texturing (102) the front surface to create a textured front surface (2a); creating (103) by diffusion of a dopant of the first conductivity type a first conductivity-type doped layer (2c) in the textured front surface and a back surface field layer (4) of the first conductivity type in the back surface; removing (105; 104a) the first conductivity-type doped layer from the textured front surface by an etching process adapted for retaining texture of the textured front surface; creating (106) a layer of a second conductivity type (6) on the textured front surface by diffusion of a dopant of the second conductivity type into the textured front surface.Type: GrantFiled: August 24, 2010Date of Patent: May 19, 2015Assignee: Stichting Energieonderzoek Centrum NederlandInventors: Paul Cornelis Barton, Ronald Cornelis Gerard Naber, Arno Ferdinand Stassen
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Publication number: 20150125980Abstract: Provided is a novel method for producing an m-plane nitride-based LED, the method making it possible to obtain an m-plane nitride-based LED reduced in forward voltage. The method comprising (i) a step of forming an active layer consisting of a nitride semiconductor over an n-type nitride semiconductor layer in which an angle between the thickness direction and the m-axis of a hexagonal crystal is 10 degrees or less, (ii) a step of forming an AlGaN layer doped with a p-type impurity over the active layer, (iii) a step of forming a contact layer consisting of InGaN is formed on the surface of the AlGaN layer, and (iv) a step of forming an electrode on the surface of the contact layer.Type: ApplicationFiled: December 24, 2014Publication date: May 7, 2015Applicants: MITSUBISHI CHEMICAL CORPORATION, SEOUL VIOSYS CO., LTD.Inventors: Kaori Kurihara, Yutaro Takeshita, Kenji Shimoyama, Shinji Takai
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Patent number: 9024344Abstract: A semiconductor device has a multilayer doping to provide improved passivation by quantum exclusion. The multilayer doping includes at least two doped layers fabricated using MBE methods. The dopant sheet densities in the doped layers need not be the same, but in principle can be selected to be the same sheet densities or to be different sheet densities. The electrically active dopant sheet densities are quite high, reaching more than 1×1014 cm?2, and locally exceeding 1022 per cubic centimeter. It has been found that silicon detector devices that have two or more such dopant layers exhibit improved resistance to degradation by UV radiation, at least at wavelengths of 193 nm, as compared to conventional silicon p-on-n devices.Type: GrantFiled: March 8, 2013Date of Patent: May 5, 2015Assignee: California Institute of TechnologyInventor: Michael E. Hoenk
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Patent number: 9012888Abstract: According to one embodiment, a semiconductor light emitting device includes a first layer of n-type and a second layer of p-type including a nitride semiconductor, a light emitting unit provided between the first and second layers, a first stacked structure provided between the first layer and the light emitting unit, and a second stacked structure provided between the first layer and the first stacked structure. The light emitting unit includes barrier layers and a well layer provided between the barrier layers. The first stacked structure includes third layers including a nitride semiconductor, and fourth layers stacked with the third layers and including GaInN. The fourth layers have a thinner thickness than the well layer. The second stacked structure includes fifth layers including a nitride semiconductor, and sixth layers stacked with the fifth layers and including GaInN. The sixth layers have a thinner thickness than the well layer.Type: GrantFiled: February 28, 2012Date of Patent: April 21, 2015Assignee: Kabushiki kaisha ToshibaInventors: Mitsuhiro Kushibe, Yasuo Ohba, Hiroshi Katsuno, Kei Kaneko, Shinji Yamada
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Patent number: 8994064Abstract: A strain release layer adjoining the active layer in a blue LED is bounded on the bottom by a first relatively-highly silicon-doped region and is also bounded on the top by a second relatively-highly silicon-doped region. The second relatively-highly silicon-doped region is a sublayer of the active layer of the LED. The first relatively-highly silicon-doped region is a sublayer of the N-type layer of the LED. The first relatively-highly silicon-doped region is also separated from the remainder of the N-type layer by an intervening sublayer that is only lightly doped with silicon. The silicon doping profile promotes current spreading and high output power (lumens/watt). The LED has a low reverse leakage current and a high ESD breakdown voltage. The strain release layer has a concentration of indium that is between 5×1019 atoms/cm3 and 5×1020 atoms/cm3, and the first and second relatively-highly silicon-doped regions have silicon concentrations that exceed 1×1018 atoms/cm3.Type: GrantFiled: January 17, 2014Date of Patent: March 31, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Zhen Chen, Yi Fu
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Patent number: 8980658Abstract: A light-emitting element includes a n-type silicon oxide film and a p-type silicon nitride film. The n-type silicon oxide film and the p-type silicon nitride film formed on the n-type silicon oxide film form a p-n junction. The n-type silicon oxide film includes a plurality of quantum dots composed of n-type Si while the p-type silicon nitride film includes a plurality of quantum dots composed of p-type Si. Light emission occurs from the boundary between the n-type silicon oxide film and the p-type silicon nitride film by injecting electrons from the n-type silicon oxide film side and holes from the p-type silicon nitride film side.Type: GrantFiled: January 31, 2013Date of Patent: March 17, 2015Assignee: Hiroshima UniversityInventor: Shin Yokoyama
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Patent number: 8981340Abstract: A nitride semiconductor device according to the present invention includes a p-type nitride semiconductor layer, an n-type nitride semiconductor layer, and an active layer interposed between the p-type nitride semiconductor layer and the n-type nitride semiconductor layer. The p-type nitride semiconductor layer includes: a first p-type nitride semiconductor layer containing Al and Mg; and a second p-type nitride semiconductor layer containing Mg. The first p-type nitride semiconductor layer is located between the active layer and the second p-type nitride semiconductor layer, and the second p-type nitride semiconductor layer has a greater band gap than a band gap of the first p-type nitride semiconductor layer.Type: GrantFiled: April 4, 2013Date of Patent: March 17, 2015Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Yasutoshi Kawaguchi, Toshitaka Shimamoto, Akihiko Ishibashi, Isao Kidoguchi, Toshiya Yokogawa
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Publication number: 20150060762Abstract: According to example embodiments, a semiconductor light emitting device includes a first semiconductor layer, a pit enlarging layer on the first semiconductor layer, an active layer on the pit enlarging layer, a hole injection layer, and a second semiconductor layer on the hole injection layer. The first semiconductor layer is doped a first conductive type. An upper surface of the pit enlarging layer and side surfaces of the active layer define pits having sloped surfaces on the dislocations. The pits are reverse pyramidal spaces. The hole injection layer is on a top surface of the active layer and the sloped surfaces of the pits. The second semiconductor layer doped a second conductive type that is different than the first conductive type.Type: ApplicationFiled: May 28, 2014Publication date: March 5, 2015Inventors: Jae-kyun KIM, Joo-sung KIM, Jun-youn KIM, Young-soo PARK, Young-jo TAK
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Publication number: 20150064827Abstract: A first pixel includes a first charge accumulation portion of a first conductivity type in a first region. A second pixel includes a second charge accumulation portion of the first conductivity type in a second region and a semiconductor region of a second conductivity type in a third region. Impurities of the second conductivity type are doped in the third region and the impurities of the second conductivity type are doped in at least the second region to generate a first difference between quantities of doping the impurities of the second conductivity type in the first and second regions. Impurities are doped in the first and second regions to reduce a second difference, caused by the first difference, between net quantities of doping impurities of the first conductivity type in the first and second regions.Type: ApplicationFiled: August 1, 2014Publication date: March 5, 2015Inventor: Hideyuki Itoh
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Publication number: 20150055671Abstract: The present disclosure involves a light-emitting device. The light-emitting device includes an n-doped gallium nitride (n-GaN) layer located over a substrate. A multiple quantum well (MQW) layer is located over the n-GaN layer. An electron-blocking layer is located over the MQW layer. A p-doped gallium nitride (p-GaN) layer is located over the electron-blocking layer. The light-emitting device includes a hole injection layer. In some embodiments, the hole injection layer includes a p-doped indium gallium nitride (p-InGaN) layer that is located in one of the three following locations: between the MQW layer and the electron-blocking layer; between the electron-blocking layer and the p-GaN layer; and inside the p-GaN layer.Type: ApplicationFiled: November 5, 2014Publication date: February 26, 2015Inventors: Zhen-Yu Li, Tzu-Te Yang, Hon-Way Lin, Chung-Pao Lin, Kuan-Chun Chen, Ching-Yu Chen, You-Da Lin, Hao-Chung Kuo
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Patent number: 8964807Abstract: In an example, the present invention provides a gallium and nitrogen containing laser diode device. The device has a gallium and nitrogen containing substrate material comprising a surface region, which is configured on either a non-polar ({10-10}) crystal orientation or a semi-polar ({10-10} crystal orientation configured with an offcut at an angle toward or away from the [0001] direction). The device also has a GaN region formed overlying the surface region, an active region formed overlying the surface region, and a gettering region comprising a magnesium species overlying the surface region. The device has a p-type cladding region comprising an (InAl)GaN material doped with a plurality of magnesium species formed overlying the active region.Type: GrantFiled: May 9, 2013Date of Patent: February 24, 2015Assignee: Soraa Laser Diode, Inc.Inventors: Melvin McLaurin, James W. Raring, Christiane Elsass
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Patent number: 8963122Abstract: In a semiconductor light emitting element outputting light indicating green color by using a group III nitride semiconductor, light emission output is improved. A semiconductor light emitting element includes: an n-type cladding layer containing n-type impurities (Si); a light emitting layer laminated on the n-type cladding layer; and a p-type cladding layer containing p-type impurities and laminated on the light emitting layer. The light emitting layer has a barrier layer including first to fifth barrier layers and a well layer including first to fourth well layers, and has a multiple quantum well structure to sandwich one well layer by two barrier layers. The light emitting layer is configured such that the first to fourth well layers are set to have a composition to emit green light, and the first barrier layer is doped with n-type impurities, whereas the other barrier layers are not doped with n-type impurities.Type: GrantFiled: August 12, 2013Date of Patent: February 24, 2015Assignee: Toyoda Gosei Co., Ltd.Inventors: Katsuki Kusunoki, Hisao Sato
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Publication number: 20150048379Abstract: Disclosed are a light emitting diode having an n-doped ohm contact buffer layer and a manufacturing method therefor. In the present invention, a highly n-doped ohm contact buffer layer with an electronic concentration up to 1×1018 cm3 is formed on the n side of a light emitting epitaxy layer; when a growth substrate is removed, the n-type ohm contact buffer layer on the surface is exposed, which is a no-nitride polarity-face n-type GaN base material with a lower energy gap; an n-type ohm contact electrode is prepared on the n-type ohm contact buffer layer and follows the Ti/Al ohm contact electrode, which can overcome the problem of the existing vertical gallium nitride-based vertical light emitting diode that the voltage of the thin film GaN base light emitting device is unreliable because the ohm contact electrode on the nitride-face GaN base semiconductor layer is easy to crack due to temperature.Type: ApplicationFiled: January 7, 2013Publication date: February 19, 2015Inventors: Meng-Hsin Yeh, Jyh-Chiarng Wu, Shaohua Huang, Chi-Lun Chou
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Patent number: 8956890Abstract: The present invention provides a method for producing a Group III nitride semiconductor light-emitting device wherein a p-cladding layer has a uniform Mg concentration. A p-cladding layer having a superlattice structure in which AlGaN and InGaN are alternately and repeatedly deposited is formed in two stages of the former process and the latter process where the supply amount of the Mg dopant gas is different. The supply amount of the Mg dopant gas in the latter process is half or less than that in the former process. The thickness of a first p-cladding layer formed in the former process is 60% or less than that of the p-cladding layer, and 160 ? or less.Type: GrantFiled: August 15, 2013Date of Patent: February 17, 2015Assignee: Toyoda Gosei Co., Ltd.Inventors: Atsushi Miyazaki, Koji Okuno
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Patent number: 8940624Abstract: A method of manufacturing a p type nitride semiconductor layer doped with carbon in a highly reproducible manner with an increased productivity is provided. The method includes supplying an III-group material gas for a predetermined time period T1, supplying a V-group material gas containing a carbon source for a predetermined time period T2 when a predetermined time period t1 (t1+T2>T1) elapses after the supply of the III-group material gas begins, repeating the step of supplying the III-group material gas and the step of supplying the V-group material gas when a predetermined time period t2 (t1+T2?t2>T1) elapses after the supply of the V-group material gas begins, and thus forming an AlxGa1-xN semiconductor layer (0<x?1) at a growth temperature of 1190° C.˜1370° C. or a growth temperature at which a substrate temperature is 1070° C.˜1250° C. using a chemical vapor deposition method or a vacuum evaporation method. Nitrogen sites within the semiconductor layer are doped with carbon.Type: GrantFiled: April 18, 2013Date of Patent: January 27, 2015Assignee: Seoul Semiconductor Co., Ltd.Inventor: Hideo Kawanishi
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Publication number: 20150024531Abstract: A light emitting diode (LED) comprises an n-type Group III-V semiconductor layer, an active layer adjacent to the n-type Group III-V semiconductor layer, and a p-type Group III-V semiconductor layer adjacent to the active layer. The active layer includes one or more V-pits. A portion of the p-type Group III-V semiconductor layer is in the V-pits. A p-type dopant injection layer provided during the formation of the p-type Group III-V layer aids in providing a predetermined concentration, distribution and/or uniformity of the p-type dopant in the V-pits.Type: ApplicationFiled: July 14, 2014Publication date: January 22, 2015Applicant: MANUTIUS IP INC.Inventor: Steve Ting
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Publication number: 20150014642Abstract: A donor substrate for a laser transfer includes a base layer, a primer layer disposed on the base layer, a light-to-heat conversion layer disposed on the primer layer, and an intermediate layer disposed on the light-to-heat conversion layer, where the light-to-heat conversion layer includes graphene.Type: ApplicationFiled: December 18, 2013Publication date: January 15, 2015Applicant: Samsung Display Co., Ltd.Inventors: Ji-Young KWON, Ji-Hwan YOON, Sang-Woo PYO, Ha-Jin SONG, Byeong-Wook YOO, Bum-Suk LEE, Ji-Myoung YE, Yi-Seul KIM
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Patent number: 8932888Abstract: A method of applying a conversion means to an optoelectronic semiconductor chip includes preparing the optoelectronic semiconductor chip having a main radiation face, preparing the conversion means, the conversion means being applied to a main carrier face of a carrier, arranging the conversion means such that it faces the main radiation face and has a spacing relative to the main radiation face, and releasing the conversion means from the carrier and applying the conversion means to the main radiation face by irradiation and heating of an absorber constituent of the conversion means and/or of a release layer located between the conversion means and the carrier with a pulsed laser radiation which passes through the carrier.Type: GrantFiled: September 6, 2011Date of Patent: January 13, 2015Assignee: OSRAM Opto Semiconductors GmbHInventor: Ralph Wagner
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Patent number: 8912079Abstract: Provided is a compound semiconductor deposition method of adjusting the luminous wavelength of a compound semiconductor of a ternary or higher system in a nanometer order in depositing the compound semiconductor on a substrate.Type: GrantFiled: April 28, 2010Date of Patent: December 16, 2014Assignees: The University of Tokyo, V Technology Co., Ltd.Inventors: Motoichi Ohtsu, Takashi Yatsui, Tadashi Kawazoe, Shunsuke Yamazaki, Koichi Kajiyama, Michinobu Mizumura, Keiichi Ito
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Patent number: 8900891Abstract: A method for manufacturing interdigitated back contact photovoltaic cells is disclosed. In one aspect, the method includes providing on a rear surface of a substrate a first doped layer of a first dopant type, and providing a dielectric masking layer overlaying it. Grooves are formed through the dielectric masking layer and first doped layer, extending into the substrate in a direction substantially orthogonal to the rear surface and extending in a lateral direction underneath the first doped layer at sides of the grooves. Directional doping is performed in a direction substantially orthogonal to the rear surface, thereby providing doped regions with dopants of a second dopant type at a bottom of the grooves. Dopant diffusion is performed to form at the rear side of the substrate one of the emitter regions and back surface field regions between the grooves and the other at the bottom of the grooves.Type: GrantFiled: June 14, 2011Date of Patent: December 2, 2014Assignee: IMECInventors: Bartlomiej Jan Pawlak, Tom Janssens
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Patent number: 8895335Abstract: A method for impurity-induced disordering in III-nitride materials comprises growing a III-nitride heterostructure at a growth temperature and doping the heterostructure layers with a dopant during or after the growth of the heterostructure and post-growth annealing of the heterostructure. The post-growth annealing temperature can be sufficiently high to induce disorder of the heterostructure layer interfaces.Type: GrantFiled: July 26, 2012Date of Patent: November 25, 2014Assignee: Sandia CorporationInventors: Jonathan J. Wierer, Jr., Andrew A. Allerman
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Patent number: 8895336Abstract: To provide a method of manufacturing an infrared light-emitting element having a wavelength of 1.57 ?m, including: forming a SiO2 film on a Si substrate containing C; and performing RTA treatment in an atmosphere containing oxygen, or implanting impurity ions therein and thereafter performing RTA treatment in an atmosphere containing oxygen, thereby forming C centers.Type: GrantFiled: September 14, 2012Date of Patent: November 25, 2014Assignee: Panasonic CorporationInventors: Akihiko Sagara, Miori Hiraiwa, Satoshi Shibata