Abstract: Provided is an optoelectronic semiconductor chip including a semiconductor layer sequence in which an active zone for generating radiation is located between a first semiconductor region and a second semiconductor region. A first electrical contact of the semiconductor layer sequence is applied to the first semiconductor region. A second electrical contact is applied to the second semiconductor region. The second electrical contact is located in a trench of the second semiconductor region. The trench is restricted to the second semiconductor region and ends at a distance from the active zone. A distance between a bottom of the trench and the active zone is at most 3 ?m.

Abstract: A method of manufacturing a semiconductor device includes forming a lower metal layer, forming an interfacial oxide film on the lower metal layer, providing a metal precursor on the interfacial oxide film at a first pressure to adsorb the metal precursor into the interfacial oxide film, performing a first purge process at a second pressure to remove the unadsorbed metal precursor, the second pressure lower than the first pressure, providing an oxidizing gas at the first pressure to react with the adsorbed metal precursor, performing a second purge process at the second pressure to remove the unreacted oxidizing gas and form a dielectric film, and forming an upper metal layer on the dielectric film.

Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

Abstract: Embodiments relate to a semiconductor device, a semiconductor wafer structure, and a method for manufacturing or forming a semiconductor wafer structure. The semiconductor device includes a semiconductor substrate with a first region having a first conductivity type and a second region having a second conductivity type. The semiconductor device further includes an oxide structure with interrupted areas and a metal layer structure being in contact with the second region at least at the interrupted areas of the oxide.

Abstract: An embodiment of the disclosure includes a method of forming a semiconductor structure. A substrate has a region adjacent to a shallow trench isolation (STI) structure in the substrate. A patterned mask layer is formed over the substrate. The patterned mask layer covers the STI structure and a portion of the region, and leaves a remaining portion of the region exposed. A distance between an edge of the remaining portion and an edge of the STI structure is substantially longer than 1 nm. The remaining portion of the region is etched thereby forms a recess in the substrate. A stressor is epitaxially grown in the recess. A conductive plug contacting the stressor is formed.

Abstract: The present invention is directed to a thick film conductive composition comprising: (a) electrically conductive silver powder; (c) fluorine-containing glass frit; dispersed in (d) organic vehicle and devices made therefrom.

Abstract: A protective structure is produced by providing a semiconductor substrate having doping of a first conductivity type. A semiconductor layer having doping of a second conductivity type is applied at a surface of the semiconductor substrate. A buried layer with doping of a second conductivity type is formed in a first region of the semiconductor layer, producing a layer at the junction between the semiconductor layer and semiconductor substrate. A first dopant zone having doping of a first conductivity type is formed in the first region of the semiconductor layer above the buried layer. A second dopant zone having doping of a second conductivity type is formed in a second region of the semiconductor layer. An electrical insulation is formed between the first and second regions of the semiconductor layer. A common connection device is formed for the first and second dopant zones.

Abstract: A semiconductor structure and method of manufacturing the semiconductor structure, and more particularly to a semiconductor structure having reduced metal line resistance and a method of manufacturing the same in back end of line (BEOL) processes. The method includes forming a first trench extending to a lower metal layer Mx+1 and forming a second trench remote from the first trench. The method further includes filling the first trench and the second trench with conductive material. The conductive material in the second trench forms a vertical wiring line extending orthogonally and in electrical contact with an upper wiring layer and electrically isolated from lower metal layers including the lower metal layer Mx+1. The vertical wiring line decreases a resistance of a structure.

Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate using a hard mask layer as a barrier to form a trench defining a plurality of active regions, forming a gap-fill layer to gap-fill a portion of the inside of the trench so that the hard mask layer becomes a protrusion, forming spacers covering both sides of the protrusion, removing one of the spacers using a doped etch barrier as an etch barrier, and etching the gap-fill layer using a remaining spacer as an etch barrier to form a side trench exposing one side of the active region.

Abstract: A potassium hydroxide (KOH) etch process can produce deep high aspect ratio trenches in (110) oriented silicon substrates. The trenches, however, are perpendicular to the (111) direction of the silicon substrate's crystal lattice. The trenches are used to produce thermally isolating areas and through the wafer electrical connections. These structures can be produced in a cost effective manner because of the nearly ideal capabilities of the KOH etch process when it is applied to appropriate materials at appropriate orientations.

Abstract: A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2(CO)10 as the source material is used when Re is to be deposited.

Abstract: A semiconductor device having reliable electrode contacts. First, an interlayer dielectric film is formed from a resinous material. Then, window holes are formed. The interlayer dielectric film is recessed by oxygen plasma. This gives rise to tapering window holes. This makes it easy to make contacts even if the circuit pattern is complex.

Abstract: Word lines of a NAND flash memory array are formed by concentric, rectangular shaped, closed loops that have a width of approximately half the minimum feature size of the patterning process used. The resulting circuits have word lines linked together so that peripheral circuits are shared. Separate erase blocks are established by shield plates.

Abstract: The present invention provides methods of cleaning a semiconductor device by removing contaminants, such as particles and/or etching by-products, from a structure of a semiconductor device using a first cleaning solution including a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and deionized (DI) water, and a second cleaning solution including ozone (O3) water. The present invention also provides methods of manufacturing a semiconductor device using these methods of cleaning the semiconductor device.

Abstract: An integrated circuit die includes thereon a first device region, a second device region and a non-active region. A first implant mask, which covers the second device region and the non-active region, while exposing the first device region, is formed over the semiconductor substrate. Dopant species are implanted into the exposed semiconductor substrate within the first device region to form first doping regions therein. A second implant mask is formed over the semiconductor substrate. The second implant mask covers the first device region, while exposing the second device region and a portion of the non-active region. Dopant species are implanted into the exposed semiconductor substrate within the second device region to form second doping regions therein.

Abstract: A light emitting diode (LED) package and process of making the same includes a silicon-on-insulator (SOI) substrate that is composed of two silicon based materials and an insulation layer interposed therebetween. The two silicon based materials of silicon-on-insulator substrate are etched to form a reflective cavity and an insulation trench, respectively, for dividing the silicon-on-insulator substrate into contact surfaces of positive and negative electrodes. A plurality of metal lines are then formed to electrically connect the two silicon based materials such that the LED chip can be mounted on the reflective cavity and electrically connected to the corresponding electrodes of the silicon-on-insulator substrate by the metal lines. Thus the properties of heat resistance and heat dispersal can be improved and the process can be simplified.

Abstract: A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.

Abstract: There is provided a method for manufacturing a semiconductor device having a high breakdown voltage transistor and a low breakdown voltage transistor provided on a same semiconductor substrate.

Abstract: A method of making a semiconductor structure includes etching an isolation oxide. The isolation oxide is in a substrate, a gate layer is on the substrate, a patterned metallic layer is on the gate layer, and a first patterned etch-stop layer is on the metallic layer.

Abstract: A mounted display assembly comprises a flexible substrate that supports both display elements and control circuits. The display assembly generally comprises: an electrical connection formed on the flexible substrate, the electrical connection having first and second contact pads; a display element in electrical communication with the first contact pad; and a control circuit mounted on the flexible substrate and in electrical communication with the second contact pad. In a preferred embodiment, the display element comprises a microencapsulated electrophoretic display medium. In another preferred embodiment, printing processes are employed in manufacturing methods for the display assembly.

Abstract: A MEMS microphone is formed on a single substrate that also includes microelectronic circuitry. High-temperature tolerance metals are used to form contacts in a metallization step before performing deep reactive ion etching and back patterning steps to form a MEMS microphone. High-temperature tolerant metals such as titanium, tungsten, chromium, etc. can be used for the contacts. Another approach uses laser annealing in place of deep reactive ion etching so that high-temperature tolerant metals do not need to be used in earlier metallization steps. Different orderings for device, circuit, and metallization series of steps are presented.

Abstract: A method of forming a conductive via plug is disclosed. The conductive via plug is formed by printing a solution comprising a solvent with insulating material dissolve capability and a conductive material by an inkjet method. The formed conductive via plug has a low resistivity and thus may serve as an electrical connection between two separate conductive layers. This manufacturing method of the conductive via plug may achieve simultaneously deposition, patterning and etching purposes, which significantly simplifies the manufacturing process.

Abstract: The invention includes methods of forming trench isolation regions. In one implementation, a masking material is formed over a semiconductor substrate. The masking material comprises at least one of tungsten, titanium nitride and amorphous carbon. An opening is formed through the masking material and into the semiconductor substrate effective to form an isolation trench within semiconductive material of the semiconductor substrate. A trench isolation material is formed within the isolation trench and over the masking material outside of the trench effective to overfill the isolation trench. The trench isolation material is polished at least to an outermost surface of the at least one of tungsten, titanium nitride and amorphous carbon of the masking material. The at least one of tungsten, titanium nitride and amorphous carbon is/are etched from the substrate. Other implementations and aspects are contemplated.

Abstract: The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated.

Abstract: A method and apparatus are provided an interconnect cladding layer. In one embodiment, a first sacrificial layer is deposited over a substrate and patterned. In the vias created during the patterning operation, a conductive material is placed to create conductive interconnects. After planarizing the conductive material, the sacrificial layer is removed leaving the interconnect exposed. A cladding layer is then deposited over the conductive material.

Abstract: A method of manufacturing a photovoltaic device includes: a step of fixing thin metal wires which are coated with electroconductive resin, to a principal surface of a photovoltaic member; a step of heating the photovoltaic member to which the thin metal wires are fixed; and a step of pressing an elastic film against the photovoltaic member and the thin metal wires while the pressure of gas on the side opposite the photovoltaic member across the elastic film is larger than the pressure of gas on the photovoltaic member side. The thin metal wires to serve as a collector electrode provided in a photovoltaic member are prevented from bending. This makes it possible to produce, with high yield, photovoltaic devices that have no fear of being reduced in output by bent thin metal wires.

Abstract: The invention includes a method of forming semiconductor circuitry wherein a first semiconductor structure comprising a first monocrystalline semiconductor substrate is bonded to a second semiconductor structure comprising a second monocrystalline semiconductor substrate. The first semiconductor substrate has a semiconductive material projection extending therefrom, and the second semiconductor substrate has an electrically conductive interconnect extending therethrough. The interconnect electrically connects with the semiconductive material projection, and comprises a different dopant type than the semiconductor material projection. The invention also includes a method of bonding a first monocrystalline semiconductor substrate construction to a second monocrystalline semiconductor substrate construction, wherein the first construction is doped to a first dopant type, and the second construction is doped to a second dopant type different from the first dopant type.

Abstract: In a method for fabricating a semiconductor device different types of a metal-semiconductor compound are formed on or in at least two different conductive semiconductor regions so that for each semiconductor region the metal-semiconductor compound region may be formed to obtain an optimum overall performance of the semiconductor device. On one of the two semiconductor regions, the metal-semiconductor compound is formed of at least two different metal layers, whereas the metal-semiconductor compound in or on the other semiconductor region is formed from a single metal layer.

Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51< prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

Abstract: A manufacturing method of manufacturing a semiconductor device having a plurality of wiring layers. The method includes the steps of forming a wiring by a first wiring layer as a pattern by dividing a desired pattern into a plurality of patterns, connecting the divided patterns, and exposing them, wherein a position of the connection is formed in parallel with the wiring which is formed by the first wiring layer, and forming a wiring by a second wiring layer having an area which intersects the connecting position by a batch processing of exposure.

Abstract: Coplanar waveguides having a deep trench between a signal line and a ground plane and methods of their fabrication are disclosed. An oxide layer is provided over a silicon substrate and a photoresist is applied and patterned to define areas where the signal line and the ground plane will be formed. A barrier layer is provided over the oxide layer in the defined areas. A metal layer is then deposited over the barrier layer. An etch mask is deposited over the metal layer for the subsequent trench formation. The photoresist and the underlying portion of the oxide and barrier layers are removed and a deep trench is formed in the substrate between the signal line and the ground plane using etching through the mask.

Abstract: Recesses between gate layer stacks are filled with a first electrically insulating material. Cavities or voids are opened up during the removal of a portion of the first insulating material. These voids are filled during the application of a conductive layer and can then lead to short circuits. Inventively, a layer for closing up voids is produced before the conductive material is applied, as a result of growing a second electrically insulating material onto the surface of the remaining first insulating material. This second insulating layer closes up voids that have formed in the first insulating material so that they can no longer lead to short circuits. In particular, voids that are difficult to gain access to and open out into side walls of contact holes can in this way be closed up in a simple manner.

Abstract: A semiconductor device includes a multilayer interconnection structure including an organic interlayer insulation film in which a conductor pattern is formed by a damascene process, wherein the organic interlayer insulation film carries thereon an organic spin-on-glass film.

Abstract: A method of fabricating a trench capacitor of a mixed mode integrated circuit includes forming shallow trench isolation regions for isolating active/passive devices on a semiconductor substrate. The lower electrode layer of the polysilicon layer, the dielectric layer, and the upper electrode layer are formed in sequence in a plurality of shallow trench isolation regions to form a trench capacitor. The present invention uses a trench capacitor to substitute for the 3-dimensional structure capacitor to overcome the disadvantages of the conventional capacitor, resulting in increasing the surface area of electrode and the capacitance.

Abstract: An integrated circuit chip comprises a periphery portion and a memory portion. The memory portion includes a data storage layer and a logic layer formed underneath the data storage layer and is separated therefrom by an intermediate layer. A first conductive layer is formed within the intermediate layer to communicatively couple the periphery and memory portions of the integrated circuit chip, and a second conductive layer is formed within the intermediate layer to communicatively couple the periphery and memory portions of the integrated circuit chip. The first and second conductive layers provide addressing and data retrieval between the memory portion and the periphery portion.

Abstract: A system and method is provided that improves the propagation characteristics of an electrical conducting signal wire on an integrated circuit. The system includes a pair of parallel shielding wires positioned on opposite longitudinal sides of the signal wire. A shielding signal is applied to the shielding wires. The shielding signal is out of phase with the signal of interest propagated on the signal wire.

Abstract: A process for manufacturing a semiconductor wafer integrating electronic devices and a structure for electromagnetic decoupling are disclosed. The method includes providing a wafer of semiconductor material having a substrate; forming a plurality of first mutually adjacent trenches, open on a first face of the wafer, which have a depth and a width and define walls); by thermal oxidation, completely oxidizing the walls and filling at least partially the first trenches, so as to form an insulating structure of dielectric material; and removing one portion of the substrate comprised between the insulating structure and a second face of the wafer, opposite to the first face of the wafer.

Abstract: The present invention provides a semiconductor device, comprising a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and source-drain diffusion layer formed within the semiconductor substrate in the vicinity of the gate electrode. A silicide film is formed on each of the gate electrode and the source-drain diffusion layer. The silicide film positioned on the gate electrode is thicker than the silicide film positioned on the source-drain diffusion layer. The present invention also provides a method of manufacturing a semiconductor device, in which a gate electrode is formed on a gate insulating film covering a semiconductor substrate, followed by forming a source-drain diffusion layer within the semiconductor substrate.

Abstract: An integrated circuit chip comprises a periphery portion and a memory portion. The memory portion includes a data storage layer and a logic layer formed underneath the data storage layer and is separated therefrom by an intermediate layer. A first conductive layer is formed within the intermediate layer to communicatively couple the periphery and memory portions of the integrated circuit chip, and a second conductive layer is formed within the intermediate layer to communicatively couple the periphery and memory portions of the integrated circuit chip. The first and second conductive layers provide addressing and data retrieval between the memory portion and the periphery portion.

Abstract: According to an exemplary method for removing a hard mask in a deep trench isolation process, a hard mask is formed over the substrate, where the substrate includes at least one field oxide region. Thereafter, a trench is formed in the substrate, where the trench has a first sidewall and a second sidewall. According to this exemplary embodiment, the hard mask is removed after forming the trench. The hard mask may be removed by, for example, etching the hard mask in an anisotropic dry etch process, where the anisotropic dry etch process is selective to nitride and silicon. Next, an oxide liner is deposited by a CVD process on the first and second sidewalls of the trench and over the substrate after the hard mask has been removed.

Abstract: A static random access memory cell comprising a first inverter including a first p-channel pullup transistor, and a first n-channel pulldown transistor in series with the first p-channel pullup transistor; a second inverter including a second p-channel pullup transistor, and a second n-channel pulldown transistor in series with the second n-channel pullup transistor, the first inverter being cross-coupled with the second inverter, the first and second pullup transistors sharing a common active area; a first access transistor having an active terminal connected to the first inverter; a second access transistor having an active terminal connected to the second inverter; and an isolator isolating the first pullup transistor from the second pullup transistor.

Abstract: An integrated circuit includes memory cells having array transistors separated by minimum lithographic feature size, and unsilicided metal bit lines encapsulated by a diffusion barrier while high performance logic transistors may be formed on the same chip without compromise of performance including an effective channel silicided contacts for low source/drain contact resistance, extension and halo implants for control of short channel effects and a dual work function semiconductor gate having a high impurity concentration and correspondingly thin depletion layer thickness commensurate with state of the art gate dielectric thickness. This structure is achieved by of an easily planarized material, and using a similar mask planarized to the height of the structures of differing materials to decouple substrate and gate implantations in the logic transistors.

Abstract: A method enables a hole-type LPC mask to be employed instead of the conventional T-type LPC mask, thereby reducing time and manpower for the manufacture of the mask. The method comprises the steps of: arranging a plurality of bit lines at regular intervals in a longitudinal direction on a semiconductor substrate; arranging a plurality of gate lines at regular intervals in a transverse direction while intersecting the bit lines; forming isolation patterns on a semiconductor substrate, each of the isolation patterns having wing-like branches in a bent shape, each of the bit lines extending over and overlapping on central portions of the isolation patterns, each of the gate lines being in contact with side end portions of the isolation patterns; and forming first contact holes through the wing-like branches of each of the isolation patterns and forming a second contact hole through the central portion of each of the isolation patterns between the wing-like branches.

Abstract: A process of production of a semiconductor memory device having a memory array including memory cells and a peripheral circuit on one substrate comprising the process of forming an interlayer insulating layer covering the memory array and peripheral circuit; forming the memory cells; exposing a surface of diffusion regions in the peripheral circuit after forming the memory cells; and forming a covering conductive layer on the exposed region of the diffusion regions in peripheral circuit. A semiconductor memory device produced by such a process has memory area having a good data retention due to a low junction leakage in the diffusion regions of the memory cells, whereas it has a high processing speed peripheral circuit due to a low resistance of the diffusion regions of the peripheral circuit.

Abstract: A nonvolatile read-only memory device, wherein a word line is on a substrate and the word line includes a metal layer a polysilicon line. A trapping layer is further located between the word line and the substrate. A polysilicon protection line is formed over the substrate and the polysilicon protection line connects the word line and a grounded doped region in the substrate, wherein the resistance of the polysilicon protection line is higher than that of the word line.

Abstract: An object of the present invention is forming a concave portion (including a penetration hole) in a semiconductor substrate by a sandblast method without causing electrostatic breakdown. In order to achieve the object, in a wafer in which at least two chips are formed, metal films are formed at least in the vicinity of circumferential portions of regions in which the concave portions (including penetration holes) of the respective chips are to be formed. In addition, the metal films are extended from the vicinity of the circumferential portions to ends of the respective corresponding chips. Further, the metal films are connected with each other through regions between the chips. The entire surface of the wafer including the metal films is masked, except for the regions in which the concave portions of the respective chips are to be formed. At least a portion of the metal films is grounded and then the concave portions are formed in the respective chips formed on the wafer by the sandblast method.

Abstract: A process for high resolution patterning of noble metals, such as platinum, for forming various semiconductor devices, such as capacitors or wiring patterns, is disclosed. A layer of noble metal, which will form an upper electrode of a capacitor, is formed over a dielectric layer. A mask layer is then formed over the noble metal layer and patterned to leave a portion of the noble metal layer exposed. The portion of the exposed noble metal is subsequently converted to its silicide, the noble metal silicide is then etched and the dielectric layer is removed, leaving the noble metal layer patterned in an upper electrode of an IC capacitor.

Abstract: An integrated circuit device is fabricated by forming at least one isolation region in an area of a semiconductor substrate, such as a monolithic semiconductor substrate or a silicon on insulator (SOI) substrate. The at least one isolation region defines at least one active region. A plurality of dummy conductive regions is distributed in the area of the semiconductor substrate, with the dummy conductive regions being constrained to overlie the at least one isolation region. The dummy conductive regions may be formed from a conductive layer that is also used to form, for example, a gate electrode, a capacitor electrode or a wiring pattern. The dummy conductive regions may be formed on an insulation layer, e.g., a gate insulation layer or an interlayer dielectric layer. Preferably, the dummy conductive regions are noncontiguous. In one embodiment, a lattice-shaped isolation region is formed including an array of node regions linked by interconnecting regions and defining an array of dummy active regions.

Abstract: A semiconductor flash memory device is formed with shallow trench isolation (STI) and a low-resistance source bus line (Vss Bus). Embodiments include forming core and peripheral field oxide regions, as by conventional STI techniques, bit lines by ion implantation, polysilicon floating gates above the channel regions and polysilicon word lines. The Vss Bus is then formed by etching away portions of the field oxide between corresponding source regions of adjacent bit lines to expose portions of the substrate, ion implanting impurities into the source regions and the exposed substrate, forming insulating spacers on the sides of the floating gates and word lines, and forming a metal silicide layer, such as titanium silicide, on the implanted source regions and exposed portions of the substrate to form a continuous conductor between the source regions.

Abstract: A method of forming a recessed polysilicon contact is provided. The method includes: forming a trench in a substrate; overfilling the trench with polysilicon; removing the polysilicon outside of the trench to provide a substantially planar surface; oxidizing the surface of the polysilicon in the trench using plasma oxidation; and removing an upper portion of the polysilicon from the trench.