Field Plate Electrode Patents (Class 438/454)
  • Patent number: 10840372
    Abstract: An LDMOS device includes a handle portion having a buried dielectric layer and a semiconductor layer thereon doped a second dopant type. A drift region doped a first type is within the semiconductor layer providing a drain extension. A gate stack includes a gate electrode on a gate dielectric layer on respective sides of a junction with the drift region. A DWELL region is within the semiconductor layer. A source region doped the first type is within the DWELL region. A drain region doped the first type is within the drift region. A first partial buried layer doped the second type is in a first portion of the drift region including under the gate electrode. A second partial buried layer doped the first type is in a second portion of the drift region including under the drain.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: November 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Zachary K. Lee
  • Patent number: 10714589
    Abstract: A method produces a transistor, in particular a gallium nitride transistor based on high electron mobility. After a structured metal layer has been formed in a first gate region by a temporarily formed structured first photoresist layer, an intermediate layer has been deposited and a second insulation layer has been deposited, a second photoresist layer is structured in order to expose a second gate region, wherein subsequently a first field plate and a second field plate are formed as buried field plates on respective sides of the second gate region.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 14, 2020
    Assignee: United Monolithic Semiconductors GmbH
    Inventor: Dag Behammer
  • Patent number: 9406773
    Abstract: A semiconductor device which provides compactness and enhanced drain withstand voltage. The semiconductor device includes: a gate electrode; a source electrode spaced from the gate electrode; a drain electrode located opposite to the source electrode with respect to the gate electrode in a plan view and spaced from the gate electrode; at least one field plate electrode located between the gate and drain electrodes in a plan view, provided over the semiconductor substrate through an insulating film and spaced from the gate electrode, source electrode and drain electrode; and at least one field plate contact provided in the insulating film, coupling the field plate electrode to the semiconductor substrate. The field plate electrode extends from the field plate contact at least either toward the source electrode or toward the drain electrode in a plan view.
    Type: Grant
    Filed: October 18, 2014
    Date of Patent: August 2, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masayasu Tanaka
  • Patent number: 9362372
    Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes an isolation structure formed in a substrate to define an active region of the substrate. The active region has a field plate region therein. A step gate dielectric structure is formed on the substrate in the field plate region. The step gate dielectric structure includes a first layer of a first dielectric material and a second layer of the dielectric material, laminated vertically to each other. The first and second layers of the first dielectric material are separated from each other by a second dielectric material layer. An etch rate of the second dielectric material layer to an etchant is different from that of the second layer of the first dielectric material. A method for forming a semiconductor device is also disclosed.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: June 7, 2016
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Sue-Yi Chen, Chien-Hsien Song, Chih-Jen Huang
  • Patent number: 9209259
    Abstract: A customized shield plate field effect transistor (FET) includes a semiconductor layer, a gate dielectric, a gate electrode, and at least one customized shield plate. The shield plate includes a conductive layer overlying a portion of the gate electrode, one of the gate electrode sidewalls, and a portion of the substrate adjacent to the sidewall. The shield plate defines a customized shield plate edge at its lateral boundary. A distance between the customized shield plate edge and the sidewall of the gate electrode varies along a length of the sidewall. The customized shield plate edge may form triangular, curved, and other shaped shield plate elements. The configuration of the customized shield plate edge may reduce the area of the resulting capacitor and thereby achieve lower parasitic capacitance associated with the FET. The FET may be implemented as a lateral diffused MOS (LDMOS) transistor suitable for high power radio frequency applications.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: December 8, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Agni Mitra, David C. Burdeaux
  • Patent number: 9190510
    Abstract: A semiconductor device with a breakdown preventing layer is provided. The breakdown preventing layer can be located in a high-voltage surface region of the device. The breakdown preventing layer can include an insulating film with conducting elements embedded therein. The conducting elements can be arranged along a lateral length of the insulating film. The conducting elements can be configured to split a high electric field spike otherwise present in the high-voltage surface region during operation of the device into multiple much smaller spikes.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 17, 2015
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Remigijus Gaska
  • Patent number: 9064868
    Abstract: One illustrative device disclosed herein includes a transistor comprising a gate electrode and a drain region formed in a semiconducting substrate, an isolation structure formed in the substrate, wherein the isolation structure is laterally positioned between the gate electrode and the drain region, and a Faraday shield that is positioned laterally between the gate electrode and the drain region and above the isolation structure, wherein the Faraday shield has a long axis that is oriented substantially vertically relative to an upper surface of the substrate.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: June 23, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yanxiang Liu, Vara Vakada, Jerome Ciavatti
  • Publication number: 20150115391
    Abstract: A method for forming a semiconductor device includes providing a semiconductor substrate having a first area and a second area. A first metal layer structure is formed which includes at least a first metal portion in the first area and a second metal portion in the second area. A plating mask is formed on the first metal layer structure to cover the second metal portion, and a second metal layer structure is plated on and in ohmic contact with the first metal portion of the first metal layer structure.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Inventors: Roman Roth, Frank Umbach
  • Patent number: 9012303
    Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: April 21, 2015
    Assignee: Nanya Technology Corporation
    Inventors: Sheng-Wei Yang, Ying-Cheng Chuang, Shyam Surthi
  • Publication number: 20150102427
    Abstract: A semiconductor device includes a substrate having an active region, a drain region in the active region, a source region in the active region, a gate structure, and a conductive field plate. The gate structure extends in a first direction over the active region. The gate structure is arranged between the drain region and the source region in a second direction transverse to the first direction. The conductive field plate extends in the second direction over an edge of the active region.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu CHEN, Wan-Hua HUANG, Jing-Ying CHEN
  • Publication number: 20150097258
    Abstract: A semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by placing in series a wire and a via so as to be in contact with a through electrode, in a portion in which the through electrode passing through the wiring layer is formed; and the through electrode that is formed by being buried inside the guard ring.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 9, 2015
    Inventor: Takushi Shigetoshi
  • Patent number: 8999769
    Abstract: A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: April 7, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Purakh Raj Verma, Liang Yi, Yemin Dong
  • Publication number: 20150084111
    Abstract: A device and a method for forming a device are presented. The method includes providing a substrate having an array region in which memory cells are to be formed. Storage gates of the memory cells are formed in the array region. A guard ring surrounding the array region is formed. A gate electrode layer is formed on the substrate. The gate electrode layer fills gaps between the storage gates and guard ring. The gate electrode layer is planarized to produce a planar surface between the gate electrode layer, storage gates and guard ring. The guard ring maintains thickness of the gate electrode layer in the array region such that thickness of the storage gates across center and edge regions of the array region is uniform.
    Type: Application
    Filed: September 18, 2014
    Publication date: March 26, 2015
    Inventors: Ling WU, Jianbo YANG, Kian Hong LIM, Sung Mun JUNG
  • Patent number: 8987839
    Abstract: Various embodiments provide ground shield structures, semiconductor devices, and methods for forming the same. An exemplary structure can include a substrate and a dielectric layer disposed on the substrate. The structure can further include multiple conductive rings disposed in the substrate, in the dielectric layer, and/or on the dielectric layer. Each conductive ring of the multiple conductive rings can have openings of about three or more, and the openings of the each conductive ring can divide the multiple conductive rings into a plurality of sub-conductive rings arranged spaced apart. The structure can further a ground ring electrically connected to each of the plurality of sub-conductive rings.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Ling Liu, Jenhao Cheng, Xining Wang
  • Publication number: 20150079758
    Abstract: A method of manufacturing a semiconductor device includes forming trenches in a first conductivity type semiconductor layer. An insulating film is then formed to cover the inner surfaces of the trenches. A part of the insulating film which is covering a bottom part of the trenches is removed from at least a portion of the trenches. Dopant ions are implanted into regions of the semiconductor layer that are below the bottom parts of that portion of the trenches from which the portion of the insulating film has been removed.
    Type: Application
    Filed: February 28, 2014
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshifumi NISHIGUCHI
  • Publication number: 20150069410
    Abstract: A semiconductor device includes: a base; an electron transit layer layered on the base; an electron-supplying layer being configured by layering a plurality of AlN layers and GaN layers alternately on the electron transit layer and having an average Al composition x; an etching sacrificial layer layered on the electron-supplying layer and made of AlyGa1-yN (0<y<1) having an Al composition y; a field plate layer layered on the etching sacrificial layer and made of AlzGa1-zN (0?z<1, z<y) having an Al composition z; and an electrode connected to the etching sacrificial layer and being provided in an area in which a part of the field plate layer is removed until reaching the etching sacrificial layer.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 12, 2015
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Kazuyuki UMENO, Hiroshi Kambayashi, Keishi Takaki
  • Publication number: 20150037961
    Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.
    Type: Application
    Filed: October 21, 2014
    Publication date: February 5, 2015
    Inventors: Sheng-Wei Yang, Ying-Cheng Chuang, Shyam Surthi
  • Patent number: 8940605
    Abstract: A method for fabricating a high-voltage transistor with an extended drain region includes forming in a semiconductor substrate of a first conductivity type, first and second trenches that define a mesa having respective first and second sidewalls; then partially filling each of the trenches with a dielectric material that covers the first and second sidewalls. The remaining portions of the trenches are then filled with a conductive material to form first and second field plates. Source and body regions are formed in an upper portion of the mesa, with the body region separating the source from a lower portion of the mesa. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: January 27, 2015
    Assignee: Power Integrations, Inc.
    Inventor: Donald Ray Disney
  • Publication number: 20140374871
    Abstract: A semiconductor device which can suppress the influence of the external electric charge and can be efficiently manufactured is provided. The semiconductor device is provided with an active region in which a semiconductor element is disposed and a termination region between the active region and an edge surface of the semiconductor substrate. An insulating layer is disposed on at least a part of an upper surface of the termination region. A plurality of floating electrodes is disposed at an interval in the insulating layer in a direction from the active region toward the edge surface of the semiconductor substrate, and a width of the plurality of floating electrodes in a thickness direction of the semiconductor substrate is greater than a width of the plurality of floating electrodes in the direction from the active region toward the edge surface of the semiconductor substrate.
    Type: Application
    Filed: November 27, 2012
    Publication date: December 25, 2014
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yasuhiro Hirabayashi, Akinori Sakakibara
  • Publication number: 20140374774
    Abstract: This semiconductor device includes a silicon carbide layer of a first conductivity type having first and second principal surfaces and including an element region and a terminal region surrounding the element region on the first principal surface. The silicon carbide layer includes a first dopant layer of the first conductivity type contacting with the first principal surface and a second dopant layer of the first conductivity type located closer to the second principal surface than the first dopant layer is. The terminal region has, in its surface portion with a predetermined depth under the first principal surface, a terminal structure including respective portions of the first and second dopant layers and a ring region of a second conductivity type running through the first dopant layer to reach the second dopant layer. The dopant concentration of the first dopant layer is twice to five times as high as that of the second dopant layer 22.
    Type: Application
    Filed: November 26, 2013
    Publication date: December 25, 2014
    Inventors: Koutarou Tanaka, Masao Uchida
  • Publication number: 20140353793
    Abstract: The present invention provides a guarding ring structure of a semiconductor high voltage device and the manufacturing method thereof The guarding ring structure comprises a first N type monocrystalline silicon substrate (3), a second N type monocrystalline silicon substrate (8), a discontinuous oxide layer (2), a metal field plate (1), a device region (9), multiple P+ type diffusion rings (5) and an equipotential ring (4). The second N type monocrystalline silicon substrate (8) is a single N type crystalline layer epitaxially formed on the first N type monocrystalline silicon substrate (3) and has lower doping concentration than the first N type monocrystalline silicon substrate (3). N type diffusion rings (6) are embedded in the inner side of the P+ type diffusion rings (5) and are fully depleted at zero bias voltage. The guarding ring structure can achieve the same withstand voltage with less area and design time.
    Type: Application
    Filed: November 21, 2012
    Publication date: December 4, 2014
    Inventor: Deming Sun
  • Patent number: 8895423
    Abstract: A diode is described with a III-N material structure, an electrically conductive channel in the III-N material structure, two terminals, wherein a first terminal is an anode adjacent to the III-N material structure and a second terminal is a cathode in ohmic contact with the electrically conductive channel, and a dielectric layer over at least a portion of the anode. The anode comprises a first metal layer adjacent to the III-N material structure, a second metal layer, and an intermediary electrically conductive structure between the first metal layer and the second metal layer. The intermediary electrically conductive structure reduces a shift in an on-voltage or reduces a shift in reverse bias current of the diode resulting from the inclusion of the dielectric layer. The diode can be a high voltage device and can have low reverse bias currents.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: November 25, 2014
    Assignee: Transphorm Inc.
    Inventor: Yuvaraj Dora
  • Publication number: 20140339671
    Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 20, 2014
    Inventors: Sameer PENDHARKAR, Naveen TIPIRNENI
  • Publication number: 20140319622
    Abstract: A semiconductor device is disclosed. An isolation structure is formed in a substrate to define an active region of the substrate, wherein the active region has a field plate region. A gate dielectric layer is formed on the substrate outside of the field plate region. A step gate dielectric structure is formed on the substrate corresponding to the field plate region, wherein the step gate dielectric structure has a thickness greater than that of the gate dielectric layer and less than that of the isolation structure. A method for forming a semiconductor device is also disclosed.
    Type: Application
    Filed: April 25, 2013
    Publication date: October 30, 2014
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Sue-Yi CHEN, Chien-Hsien SONG, Chih-Jen HUANG
  • Publication number: 20140252532
    Abstract: Provided is a method for fabricating a semiconductor device, including the following steps. A substrate having a plurality of pillars is provided, wherein a plurality of trenches are formed around each pillar. A doped region is formed in the substrate and below each pillar. The doped region below each trench is removed to form an opening such that the doped regions below the adjacent pillars are separated from each other. A shielding layer is formed in each opening.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Sheng-Wei Yang, Ying-Cheng Chuang, Shyam Surthi
  • Patent number: 8802529
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: August 12, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Madhur Bobde
  • Patent number: 8796108
    Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Frederick G. Anderson, Natalie B. Feilchenfeld, David L. Harmon, Richard A. Phelps, Yun Shi, Michael J. Zierak
  • Publication number: 20140162421
    Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.
    Type: Application
    Filed: February 12, 2014
    Publication date: June 12, 2014
    Applicant: Transphorm Inc.
    Inventors: Rongming Chu, Robert Coffie
  • Patent number: 8748287
    Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: June 10, 2014
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Andre Hanke, Snezana Jenei, Oliver Nagy, Jiro Morinaga, Bernd Adler, Heinrich Koerner
  • Patent number: 8741736
    Abstract: A semiconductor device includes a source, a drain, and a gate configured to selectively enable a current to pass between the source and the drain. The semiconductor device includes a drift zone between the source and the drain and a first field plate adjacent the drift zone. The semiconductor device includes a dielectric layer electrically isolating the first field plate from the drift zone and charges within the dielectric layer close to an interface of the dielectric layer adjacent the drift zone.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: June 3, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Rudolf Berger, Franz Hirler, Ralf Siemieniec, Hans-Joachim Schulze
  • Publication number: 20140145212
    Abstract: A semiconductor device includes a silicon carbide semiconductor substrate, a transistor formed in a cell region of the semiconductor substrate, and a voltage-breakdown-resistant structure formed in a region which surrounds an outer periphery of the cell region. The semiconductor substrate includes a first conductivity type substrate, a first conductivity type drift layer on the first conductivity type substrate, a second conductivity type layer on the drift layer, and a first conductivity type layer on the second conductivity type layer. The voltage-breakdown-resistant structure includes a first recess which surrounds the outer periphery of the cell region and reaches the drift layer, a trench located at a side surface of the recess on an inner periphery of the recess, and a second conductivity type buried layer buried in the trench to provide the side surface of the first recess.
    Type: Application
    Filed: August 8, 2012
    Publication date: May 29, 2014
    Applicant: DENSO CORPORATION
    Inventors: Yuichi Takeuchi, Naohiro Suzuki
  • Patent number: 8729640
    Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: May 20, 2014
    Assignee: Silicon Space Technology Corporation
    Inventor: Wesley H. Morris
  • Patent number: 8722502
    Abstract: A method of manufacturing a semiconductor device, includes forming a trench surrounding a first area of a semiconductor substrate, the trench having a bottom surface and two side surfaces being opposite to each other, forming a silicon film on the bottom surface and side surfaces of the trench, forming an insulation film on the silicon film in the trench, grinding a bottom surface of the semiconductor substrate to expose the insulation film formed over the bottom surface of the trench, and forming a through electrode in the first area after grinding the bottom surface of the semiconductor substrate, the through electrode penetrating the semiconductor substrate.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: May 13, 2014
    Inventor: Shiro Uchiyama
  • Patent number: 8722483
    Abstract: The invention discloses a method for manufacturing a dual-layer polysilicon gate. The method includes: depositing silicon nitride on silicon oxide of an integrated circuit to be processed; performing anisotropic etching on the silicon nitride to form sidewalls of silicon nitride on sidewalls of a first layer of polysilicon gate of the integrated circuit to be processed; manufacturing a second layer of polysilicon gate; and rinsing the sidewalls of silicon nitride.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: May 13, 2014
    Assignees: Peking University Founder Group Co., Ltd., Founder Microelectronics International Co., Ltd.
    Inventor: Guangran Pan
  • Patent number: 8669639
    Abstract: A semiconductor element, a manufacturing method thereof and an operating method thereof are provided. The semiconductor element includes a substrate, a first well, a second well, a third well, a fourth well, a bottom layer, a first heavily doping region, a second heavily doping region, a third heavily doping region and a field plane. The first well, the bottom layer and the second well surround the third well for floating the third well and the substrate. The first, the second and the third heavily doping regions are disposed in the first, the second and the third wells respectively. The field plate is disposed above a junction between the first well and the fourth well.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: March 11, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Ling Hung, Chien-Wen Chu, Hsin-Liang Chen, Wing-Chor Chan
  • Patent number: 8652928
    Abstract: A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Bae Yoon, Jeong-Dong Choe, Dong-Hoon Jang, Ki-Hyun Kim
  • Patent number: 8642986
    Abstract: An integrated circuit (IC) having a microelectromechanical system (MEMS) device buried therein is provided. The integrated circuit includes a substrate, a metal-oxide semiconductor (MOS) device, a metal interconnect, and the MEMS device. The substrate has a logic circuit region and a MEMS region. The MOS device is located on the logic circuit region of the substrate. The metal interconnect, formed by a plurality of levels of wires and a plurality of vias, is located above the substrate to connect the MOS device. The MEMS device is located on the MEMS region, and includes a sandwich membrane located between any two neighboring levels of wires in the metal interconnect and connected to the metal interconnect.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: February 4, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Tzung-Han Tan, Bang-Chiang Lan, Ming-I Wang, Tzung-I Su, Chien-Hsin Huang, Hui-Min Wu, Chao-An Su, Min Chen, Meng-Jia Lin
  • Publication number: 20140017876
    Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.
    Type: Application
    Filed: September 13, 2013
    Publication date: January 16, 2014
    Inventors: Hans-Joachim Barth, Andre Hanke, Snezana Jenei, Oliver Nagy, Jiro Morinaga, Bernd Adler, Heinrich Koerner
  • Patent number: 8629041
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include die bonding to bond a semiconductor element to a first position of a base member via a bonding layer provided on one surface of the semiconductor element. The method can include wire bonding to connect a terminal formed on the semiconductor element to a terminal formed on the base member by a bonding wire. In addition, the method can include sealing to seal the semiconductor element and the bonding wire. Viscosity of the bonding layer in the bonding is controlled not to exceed the viscosity of the bonding layer in the sealing.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: January 14, 2014
    Assignees: Kabushiki Kaisha Toshiba, KYOCERA Chemical Corporation
    Inventors: Yasuo Tane, Yukio Katamura, Atsushi Yoshimura, Fumihiro Iwami, Kazuyoshi Sakurai
  • Patent number: 8629505
    Abstract: A semiconductor device includes: a drain layer; a drift layer provided on the drain layer; a base region provided on the drift layer; a source region selectively provided on a surface of the base region; a first gate; a field-plate; a second gate; a drain electrode; and a source electrode. The first gate electrode is provided in each of a plurality of first trenches via a first insulating film. The first trenches penetrate from a surface of the source region through the base region and contact the drift layer. The field-plate electrode is provided in the first trench under the first gate electrode via a second insulating film. The second gate electrode is provided in a second trench via a third insulating film. The second trench penetrates from the surface of the source region through the base region and contacts the drift layer between the first trenches.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: January 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuya Nishiwaki
  • Patent number: 8623743
    Abstract: Provided is a semiconductor chip. The semiconductor chip includes a semiconductor substrate including a main chip region and a scribe lane region surrounding the main chip region. An insulating layer is disposed over the semiconductor substrate. A guard ring is disposed in the insulating layer in the scribe lane region. The guard ring surrounds at least a portion of the main chip region. The guard ring has a brittleness greater than a brittleness of the insulating layer.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: January 7, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Do Lee, JongKook Kim, SeokWon Lee, Jaesik Lee, Hohyeuk Im, Su-Min Park
  • Patent number: 8609474
    Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device according to an exemplary embodiment of the present disclosure, at the time of forming a source electrode, a drain electrode, a field plate electrode, and a gate electrode on a substrate having a heterojunction structure such as AlGaN/GaN, the field plate electrode made of the same metal as the gate electrode is formed on the side surface of a second support part positioned below a head part of the gate electrode so as to prevent the gate electrode from collapsing and improve high-frequency and high-voltage characteristic of the semiconductor device.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: December 17, 2013
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jong-Won Lim, Hokyun Ahn, Dong Min Kang, Woojin Chang, Hae Cheon Kim, Eun Soo Nam
  • Patent number: 8597992
    Abstract: A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: December 3, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Masashi Tsubuku, Hitoshi Nakayama, Daigo Shimada
  • Patent number: 8592867
    Abstract: A HEMT comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the plurality of active layers. A spacer layer is formed on at least a portion of a surface of said plurality of active layers and covering the gate. A field plate is formed on the spacer layer and electrically connected to the source electrode, wherein the field plate reduces the peak operating electric field in the HEMT.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: November 26, 2013
    Assignee: Cree, Inc.
    Inventors: Yifeng Wu, Primit Parikh, Umesh Mishra, Marcia Moore
  • Patent number: 8587023
    Abstract: A guard ring system is disclosed for protecting an integrated circuit comprising. It has a first guard ring area formed by a well in the substrate, a capacitor area formed within the first guard ring area which further includes two well contacts formed into the well and biased by a first supply voltage, and a dielectric layer placed between the two contacts on the well with its first side in contact with the well. A second supply voltage complementary to the first supply voltage is applied to a second side of the dielectric layer so that a voltage difference across the dielectric layer provides a local capacitance embedded therein.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: November 19, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Cheng Hung Lee
  • Patent number: 8587061
    Abstract: A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: November 19, 2013
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yeeheng Lee, Yongping Ding, John Chen
  • Publication number: 20130299938
    Abstract: Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.
    Type: Application
    Filed: July 19, 2013
    Publication date: November 14, 2013
    Inventors: Frederick G. Anderson, Natalie B. Feilchenfeld, David L. Harmon, Richard A. Phelps, Yun Shi, Michael J. Zierak
  • Publication number: 20130277710
    Abstract: A semiconductor component having differently structured cell regions, and a method for producing it. For this purpose, the semiconductor component includes a semiconductor body. A first electrode on the top side of the semiconductor body is electrically connected to a first zone near the surface of the semiconductor body. A second electrode is electrically connected to a second zone of the semiconductor body. Furthermore, the semiconductor body has a drift path region, which is arranged in the semiconductor body between the first electrode and the second electrode. A cell region of the semiconductor component is subdivided into a main cell region and an auxiliary cell region, wherein the breakdown voltage of the auxiliary cells is greater than the breakdown voltage of the main cells.
    Type: Application
    Filed: June 13, 2013
    Publication date: October 24, 2013
    Inventor: Franz Hirler
  • Patent number: 8552496
    Abstract: A high-voltage transistor includes a drain, a source, and one or more drift regions extending from the drain toward the source. A field plate member laterally surrounds the drift regions and is insulated from the drift regions by a dielectric layer. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: October 8, 2013
    Assignee: Power Integrations, Inc.
    Inventor: Donald Ray Disney
  • Patent number: 8536683
    Abstract: Structures of a system on a chip are disclosed. In one embodiment, the system on a chip (SoC) includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary, and a conductive cage disposed enclosing the RF component. The conductive cage shields the semiconductor component from electromagnetic radiation originating from the RF circuit.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: September 17, 2013
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Barth, Andre Hanke, Snezana Jenei, Oliver Nagy, Jiro Morinaga, Bernd Adler, Heinrich Koerner