Hydrogen Plasma (i.e., Hydrogenization) Patents (Class 438/475)
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Patent number: 12238923Abstract: A contact forming method may include providing a semiconductor substrate including a silicon oxide film to an interior of a chamber, subjecting a surface of the silicon oxide film to plasma nitrification treatment, supplying a source gas including TiCl4 and H2 onto the silicon oxide film subjected to the plasma nitrification treatment, and forming a barrier layer by igniting a plasma using the source gas.Type: GrantFiled: November 30, 2023Date of Patent: February 25, 2025Assignee: Samsung Electronics Co., Ltd.Inventors: Suncheul Kim, Donghyun Lee, Uihyoung Lee
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Patent number: 11871563Abstract: A contact forming method may include providing a semiconductor substrate including a silicon oxide film to an interior of a chamber, subjecting a surface of the silicon oxide film to plasma nitrification treatment, supplying a source gas including TiCl4 and H2 onto the silicon oxide film subjected to the plasma nitrification treatment, and forming a barrier layer by igniting a plasma using the source gas.Type: GrantFiled: January 4, 2022Date of Patent: January 9, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Suncheul Kim, Donghyun Lee, Uihyoung Lee
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Patent number: 10665587Abstract: According to one embodiment, A semiconductor device includes: a first semiconductor layer; and a plurality of first transistors including a plurality of first gate structures provided on the first semiconductor layer, a first channel region provided in the first semiconductor layer and under the first gate structure, and a plurality of first diffusion regions provided in the first semiconductor layer in a manner to sandwich the first channel region.Type: GrantFiled: June 7, 2018Date of Patent: May 26, 2020Assignee: Kabushiki Kaisha ToshibaInventors: Keiji Ikeda, Tsutomu Tezuka
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Patent number: 10522343Abstract: A method for forming a semiconductor device is provided in several embodiments. According to one embodiment, the method includes providing a substrate in a process chamber, flowing a process gas consisting of hydrogen (H2) and optionally a noble gas into the process chamber, forming plasma excited species from the process gas by a microwave plasma source. The method further includes exposing an interface layer on the substrate to the plasma excited species to form a modified interface layer, and depositing a high dielectric constant (high-k) film by atomic layer deposition (ALD) on the modified interface layer. In some embodiments, the modified interface layer has higher electrical mobility than the interface layer, and the high-k film nucleates at a higher rate on the modified interface layer rate than on the interface layer.Type: GrantFiled: March 2, 2015Date of Patent: December 31, 2019Assignee: Tokyo Electron LimitedInventors: Kandabara N. Tapily, Robert D. Clark
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Patent number: 9105512Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device includes a first oxide layer overlying a channel connecting a source and a drain formed in a substrate, a first nitride layer overlying the first oxide layer, a second oxide layer overlying the first nitride layer and a second nitride layer overlying the second oxide layer. A dielectric layer overlies the second nitride layer and a gate layer overlies the dielectric layer. The second nitride layer is oxygen-rich relative to the second nitride layer and includes a majority of the charge traps. Other embodiments are also described.Type: GrantFiled: April 29, 2014Date of Patent: August 11, 2015Assignee: Cypress Semiconductor CorporationInventors: Fredrick B. Jenne, Krishnaswamy Ramkumar
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Publication number: 20150050798Abstract: A method for producing a semiconductor device includes providing a semiconductor substrate having a first conductivity type; implanting protons through a rear surface of the semiconductor substrate of the first conductivity type; and forming a first semiconductor region of the first conductivity type in the semiconductor substrate by performing an annealing process in an annealing furnace in a hydrogen atmosphere having a volume concentration of hydrogen that is equal to or greater than 0.5% and less than 4.65%, the first semiconductor region having a higher impurity concentration than that of the semiconductor substrate after the implantation step. The method reduces crystal defects in the generation of donors during proton implantation and improves the rate of change into a donor.Type: ApplicationFiled: March 14, 2013Publication date: February 19, 2015Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yusuke Kobayashi, Takashi Yoshimura
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Patent number: 8772126Abstract: A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device.Type: GrantFiled: August 10, 2012Date of Patent: July 8, 2014Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Anton Mauder
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Patent number: 8753985Abstract: Molecular layer deposition of silicon carbide is described. A deposition precursor includes a precursor molecule which contains silicon, carbon and hydrogen. Exposure of a surface to the precursor molecule results in self-limited growth of a single layer. Though the growth is self-limited, the thickness deposited during each cycle of molecular layer deposition involves multiple “atomic” layers and so each cycle may deposit thicknesses greater than typically found during atomic layer depositions. Precursor effluents are removed from the substrate processing region and then the surface is irradiated before exposing the layer to the deposition precursor again.Type: GrantFiled: September 27, 2012Date of Patent: June 17, 2014Assignee: Applied Materials, Inc.Inventors: Brian Underwood, Abhijit Basu Mallick, Nitin K. Ingle
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Publication number: 20140065798Abstract: Provided are methods and apparatus for functionalizing a substrate surface used as the channel in a gate stack. Silicon, germanium and silicon germanium substrates surfaces are functionalized with one or more of sulfur and selenium by plasma processing.Type: ApplicationFiled: August 30, 2013Publication date: March 6, 2014Inventors: Khaled Z. Ahmed, Steven Hung, Kaushal K. Singh, Sundar Ramamurthy
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Publication number: 20140051234Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.Type: ApplicationFiled: October 29, 2013Publication date: February 20, 2014Inventors: Gul B. Basim, Scott R. Summerfelt, Ted S. Moise
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Patent number: 8613864Abstract: The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.Type: GrantFiled: August 23, 2012Date of Patent: December 24, 2013Assignee: Micron Technology, Inc.Inventor: Prashant Raghu
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Patent number: 8614140Abstract: There is provided a semiconductor device manufacturing apparatus capable of recovering a damage of a low dielectric insulating film exposed to CO2 plasma to obtain the low dielectric insulating film in a good state, thus improving performance and reliability of a semiconductor device. The semiconductor device manufacturing apparatus includes: an etching processing mechanism for performing an etching process that etches a low dielectric insulating film formed on a substrate; a CO2 plasma processing mechanism for performing a CO2 plasma process that exposes the substrate to CO2 plasma after the etching process; a polarization reducing mechanism for performing a polarization reducing process that reduces polarization in the low dielectric insulating film after the CO2 plasma process; and a transfer mechanism for transferring the substrate.Type: GrantFiled: December 19, 2011Date of Patent: December 24, 2013Assignee: Tokyo Electron LimitedInventors: Ryuichi Asako, Gousuke Shiraishi, Shigeru Tahara
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Publication number: 20130328175Abstract: The present invention relates to a method for the hydrogen passivation of semiconductor layers, wherein the passivation is effected by using an arc plasma source, to the passivated semiconductor layers produced according to the method, and to the use thereof.Type: ApplicationFiled: November 11, 2011Publication date: December 12, 2013Applicant: Evonik Degussa GmbHInventors: Patrik Stenner, Stephan Wieber, Michael Cölle, Matthias Patz, Reinhard Carius, Torsten Bronger
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Patent number: 8603899Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.Type: GrantFiled: October 25, 2012Date of Patent: December 10, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
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Patent number: 8470651Abstract: Provided is a metallic wiring film which is not peeled away even when exposed to a hydrogen plasma. A metallic wiring film is constituted by an adhesion layer containing copper, Ca, and oxygen and a low-resistance metal layer (a layer of a copper alloy or pure copper) having a lower resistance than the adhesion layer. When the adhesion layer is composed of a copper alloy, which contains Ca and oxygen, and a source electrode film and a drain electrode film adhering to an ohmic contact layer are constituted by the adhesion layer, even if the adhesion layer is exposed to the hydrogen plasma, a Cu-containing oxide formed at an interface between the adhesion layer and the ohmic contact layer is not reduced, so that no peeling occurs between the adhesion layer and a silicon layer.Type: GrantFiled: April 21, 2011Date of Patent: June 25, 2013Assignees: Mitsubishi Materials Corporation, Ulvac, Inc.Inventors: Satoru Takasawa, Satoru Ishibashi, Tadashi Masuda
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Patent number: 8414790Abstract: The various embodiments described in the specification provide improved mechanisms of removal of unwanted deposits on the bevel edge to improve process yield. The embodiments provide apparatus and methods of treating the bevel edge of a copper plated substrate to convert the copper at the bevel edge to a copper compound that can be wet etched with a fluid at a high etch selectivity in comparison to copper. In one embodiment, the wet etch of the copper compound at high selectivity to copper allows the removal of the non-volatile copper at substrate bevel edge in a wet etch processing chamber. The plasma treatment at bevel edge allows the copper at bevel edge to be removed at precise spatial control to about 2 mm or below, such as about 1 mm, about 0.5 mm or about 0.25 mm, to the very edge of substrate.Type: GrantFiled: May 5, 2010Date of Patent: April 9, 2013Assignee: Lam Research CorporationInventors: Andrew D. Bailey, III, Yunsang Kim
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Patent number: 8389395Abstract: A method for manufacturing includes the steps of forming a BCB resin region on a semiconductor optical device; processing a surface of the BCB resin region with inductively coupled plasma produced with a high-frequency power supply for supplying ICP power and a high-frequency power supply for supplying bias power, thus forming a silicon oxide film on the surface of the BCB resin region and roughening the surface of the BCB resin region with projections and recesses; and forming an electrode pad on the surface of the BCB resin region in direct contact with the silicon oxide film. The surface roughness of the BCB resin region and the thickness of the silicon oxide film on the surface of the BCB resin region are controlled by adjusting the bias power and the ICP power.Type: GrantFiled: September 2, 2011Date of Patent: March 5, 2013Assignee: Sumitomo Electric Industries, Ltd.Inventor: Yukihiro Tsuji
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Patent number: 8383495Abstract: Semiconductor layer structure and a method for producing a structure are provided, including a substrate made of semiconductor material, on which a layer made of a second semiconductor material is situated, furthermore a region (3) enriched with impurity atoms, which region is situated either in layer (2) or at a specific depth below the interface between layer (2) and substrate (1), additionally a layer (4) within the region (3) enriched with impurity atoms, which layer comprises cavities produced by ion implantation, furthermore at least one epitaxial layer (6) applied to layer (2) and also a defect region (5) comprising dislocations and stacking faults within the layer (4) comprising cavities, the at least one epitaxial layer (6) being largely crack-free, and a residual strain of the at least one epitaxial layer (6) being less than or equal to 1 GPa.Type: GrantFiled: March 2, 2011Date of Patent: February 26, 2013Assignee: Siltronic AGInventors: Brian Murphy, Maik Haeberlen, Joerg Lindner, Bernd Stritzker
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Patent number: 8361873Abstract: It is an object of the present invention is to provide a method of manufacturing an SOI substrate provided with a single-crystal semiconductor layer which can be practically used even when a substrate having a low heat-resistant temperature, such as a glass substrate or the like, is used, and further, to manufacture a semiconductor device with high reliability by using such an SOI substrate. A semiconductor layer which is separated from a semiconductor substrate and bonded to a supporting substrate having an insulating surface is irradiated with electromagnetic waves, and the surface of the semiconductor layer is subjected to polishing treatment. At least part of a region of the semiconductor layer is melted by irradiation with electromagnetic waves, and a crystal defect in the semiconductor layer can be reduced. Further, the surface of the semiconductor layer can be polished and planarized by polishing treatment.Type: GrantFiled: April 19, 2010Date of Patent: January 29, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Ryota Imahayashi, Yoichi Iikubo, Kenichiro Makino, Sho Nagamatsu
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Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator
Patent number: 8361889Abstract: A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer.Type: GrantFiled: July 6, 2010Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Thomas N. Adam, Stephen W. Bedell, Joel P. de Souza, Keith E. Fogel, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi -
Patent number: 8329563Abstract: A device and a device manufacturing process. First, a gettering layer is formed on the bottom surface of a silicon substrate. Gates having a MOS structure are then formed on the principal surface of the silicon substrate, and the gettering layer is removed. According to this manufacturing method, the formation of the gates having a MOS structure is performed such that the gettering layer getters dissolved oxygen present in the silicon substrate. This reduces the concentration of dissolved oxygen in the silicon substrate, resulting in improved device characteristics.Type: GrantFiled: February 24, 2006Date of Patent: December 11, 2012Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tadaharu Minato, Hidekazu Yamamoto
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Patent number: 8324084Abstract: An object is to provide a manufacturing method of a semiconductor substrate provided with a single crystal semiconductor layer with a surface having a high degree of flatness. Another object is to manufacture a semiconductor device with high reliability by using the semiconductor substrate provided with a single crystal semiconductor layer with a high degree of flatness. In a manufacturing process of a semiconductor substrate, a thin embrittled region containing a large crystal defect is formed in a single crystal semiconductor substrate at a predetermined depth by subjecting the single crystal semiconductor substrate to a rare gas ion irradiation step, a laser irradiation step, and a hydrogen ion irradiation step. Then, by performing a separation heating step, a single crystal semiconductor layer that is flatter on a surface side than the embrittled region is transferred to a base substrate.Type: GrantFiled: March 25, 2011Date of Patent: December 4, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Junichi Koezuka
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Patent number: 8313805Abstract: An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which includes an inner electrode mechanically attached to a backing plate by a clamp ring and an outer electrode attached to the backing plate by a series of spaced apart cam locks. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release cam pins extending upward from the upper face of the outer electrode. To compensate for differential thermal expansion, the clamp ring can include expansion joins at spaced locations which allow the clamp ring to absorb thermal stresses.Type: GrantFiled: March 16, 2012Date of Patent: November 20, 2012Assignee: Lam Research CorporationInventors: Babak Kadkhodayan, Rajinder Dhindsa, Anthony de la Llera, Michael C. Kellogg
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Patent number: 8309436Abstract: A method of producing an epitaxial substrate for a solid-state imaging device, comprising: forming a gettering sink by injecting laser beam to a semiconductor substrate through one surface thereof, condensing the laser beam to an arbitrarily selected portion of the semiconductor substrate, thereby causing multi-photon absorption process to occur in the portion, and forming a gettering sink having a modified crystal structure; and epitaxially growing at least two epitaxial layers on the semiconductor substrate in which the gettering sink is formed.Type: GrantFiled: May 28, 2010Date of Patent: November 13, 2012Assignee: Sumco CorporationInventor: Kazunari Kurita
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Patent number: 8304327Abstract: At present, a forming process of a base film through an amorphous silicon film is conducted in respective film forming chambers in order to obtain satisfactory films. When continuous formation of the base film through the amorphous silicon film is performed in a single film forming chamber with the above film formation condition, crystallization is not sufficiently attained in a crystallization process. By forming the amorphous silicon film using silane gas diluted with hydrogen, crystallization is sufficiently attained in the crystallization process even with the continuous formation of the base film through the amorphous silicon film in the single film forming chamber.Type: GrantFiled: February 25, 2010Date of Patent: November 6, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi
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Patent number: 8207046Abstract: To prevent bubbles from occurring along a transfer interface, the present method includes the steps of: forming a peeled layer 10 in a transferred member 6 by implanting a peeled-layer forming substance into the transferred member 6; forming a planar surface in the transferred member 6 by planarizing a surface of the transferred member 6; forming a composite including the transferred member 6 and a glass substrate 2 by directly combining the transferred member 6 via the planar surface with a surface of the glass substrate 2; and peeling a part of the transferred member 6 from the composite along the peeled layer 10 serving as an interface by heat-treating the composite.Type: GrantFiled: October 21, 2008Date of Patent: June 26, 2012Assignee: Sharp Kabushiki KaishaInventors: Michiko Takei, Shin Matsumoto, Yasumori Fukushima, Yutaka Takafuji
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Patent number: 8193075Abstract: Apparatus and methods for repairing silicon dangling bonds resulting from semiconductor processing are disclosed. The silicon dangling bonds can be repaired by introducing hydrogen radicals with substantially no hydrogen ions into the processing chamber to react with the silicon dangling bonds, eliminating them.Type: GrantFiled: April 9, 2010Date of Patent: June 5, 2012Assignee: Applied Materials, Inc.Inventor: Zhi Xu
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Patent number: 8153495Abstract: A thin film transistor (TFT) formed on a substrate includes a polycrystalline film, a gate insulator, a hydrogen-supplying film and a gate electrode. The polycrystalline film is formed on the substrate. Two sides of the polycrystalline film serve as the source and the drain of the semiconductor device, and the central region of the polycrystalline layer serves as the channel. The gate insulator is formed on the polycrystalline film, then the polycrystalline film is ions implanted, and the hydrogen-supplying film is formed on the gate insulator. The gate electrode is formed on the hydrogen-supplying film above the channel. The hydrogen-supplying film supplies hydrogen to the polycrystalline film, especially to the channel, so as to transform the unsaturated bonds into hydrogen bonds in the channel for avoiding the unsaturated bonds to degrade the charge carrier efficiency of the channel.Type: GrantFiled: October 30, 2008Date of Patent: April 10, 2012Assignee: Au Optronics Corp.Inventors: Kuang-Chao Yeh, Wen-Bin Hsu
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Patent number: 8143134Abstract: The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput.Type: GrantFiled: September 28, 2009Date of Patent: March 27, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Takeshi Shichi, Junichi Koezuka, Hideto Ohnuma, Shunpei Yamazaki
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Patent number: 8138064Abstract: A method for producing a silicon film-transferred insulator wafer is disclosed. The method includes a surface activation step of performing a surface activation treatment on at least one of a surface of an insulator wafer and a hydrogen ion-implanted surface of a single crystal silicon wafer into which a hydrogen ion has been implanted to form a hydrogen ion-implanted layer; a bonding step that bonds the hydrogen ion-implanted surface to the surface of the insulator wafer to obtain bonded wafers; a first heating step that heats the bonded wafers; a grinding and/or etching step of grinding and/or etching a surface of a single crystal silicon wafer side of the bonded wafers; a second heating step that heats the bonded wafers; and a detachment step to detach the hydrogen ion-implanted layer by applying a mechanical impact to the hydrogen ion-implanted layer of the bonded wafers thus heated at the second temperature.Type: GrantFiled: October 29, 2009Date of Patent: March 20, 2012Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Makoto Kawai, Kouichi Tanaka, Yuji Tobisaka, Yoshihiro Nojima
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Patent number: 8124502Abstract: A semiconductor device manufacturing method is provided, including: providing a semiconductor substrate, forming on the semiconductor substrate a layer including a semiconductor compound and a dope additive, and thereafter forming an emitter region and gettering impurities by annealing the semiconductor substrate including the layer.Type: GrantFiled: October 23, 2008Date of Patent: February 28, 2012Assignee: Applied Materials, Inc.Inventor: Rafel Ferre i Tomas
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Patent number: 8119461Abstract: By performing a heat treatment on the basis of a hydrogen ambient, exposed silicon-containing surface portions may be reorganized prior to the formation of gate dielectric materials. Hence, the interface quality and the material characteristics of the gate dielectrics may be improved, thereby reducing negative bias temperature instability effects in highly scaled P-channel transistors.Type: GrantFiled: November 1, 2010Date of Patent: February 21, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Martin Trentzsch, Thorsten Kammler, Rolf Stephan
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Patent number: 8101507Abstract: There is provided a semiconductor device manufacturing apparatus and a semiconductor device manufacturing method capable of recovering a damage of a low dielectric insulating film exposed to CO2 plasma to obtain the low dielectric insulating film in a good state, thus improving performance and reliability of a semiconductor device. The semiconductor device manufacturing method includes: an etching process for etching a low dielectric insulating film formed on a substrate; a CO2 plasma process for exposing the substrate to CO2 plasma after the etching process; and a UV process for irradiating UV to the low dielectric insulating film after the CO2 plasma process.Type: GrantFiled: October 16, 2009Date of Patent: January 24, 2012Assignee: Tokyo Electron LimitedInventors: Ryuichi Asako, Gousuke Shiraishi, Shigeru Tahara
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Patent number: 8101501Abstract: To provide a method of manufacturing a semiconductor device, which prevents impurities from entering an SOI substrate. A source gas including one or plural kinds selected from a hydrogen gas, a helium gas, or halogen gas are excited to generate ions, and the ions are added to a bonding substrate to thereby form a fragile layer in the bonding substrate. Then, a region of the bonding substrate that is on and near the surface thereof, i.e., a region ranging from a shallower position than the fragile layer to the surface is removed by etching, polishing, or the like. Next, after attaching the bonding substrate to a base substrate, the bonding substrate is separated at the fragile layer to thereby form a semiconductor film over the base substrate. After forming the semiconductor film over the base substrate, a semiconductor element is formed using the semiconductor film.Type: GrantFiled: September 29, 2008Date of Patent: January 24, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Yoichi Iikubo, Shunpei Yamazaki
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Patent number: 8088670Abstract: When manufacturing a bonded substrate using an insulator substrate as a handle wafer, there is provided a method for manufacturing a bonded substrate which can be readily removed after carried and after mounted by roughening a back surface of the bonded substrate (corresponding to a back surface of the insulator substrate) and additionally whose front surface can be easily identified like a process of a silicon semiconductor wafer in case of the bonded substrate using a transparent insulator substrate as a handle wafer. There is provided a method for manufacturing a bonded substrate in which an insulator substrate is used as a handle wafer and a donor wafer is bonded to a front surface of the insulator substrate, the method comprises at least that a sandblast treatment is performed with respect to a back surface of the insulator substrate.Type: GrantFiled: April 14, 2008Date of Patent: January 3, 2012Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Shoji Akiyama, Yoshihiro Kubota, Atsuo Ito, Kouichi Tanaka, Makoto Kawai, Yuuji Tobisaka
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Patent number: 8062957Abstract: The invention relates to a method for preparing a surface of a semiconductor substrate by oxidizing the surface of the semiconductor substrate to thereby transform the natural oxide into an artificial oxide and then removing the artificial oxide, in particular to obtain an oxide-free substrate surface.Type: GrantFiled: January 23, 2009Date of Patent: November 22, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventor: Radouane Khalid
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Patent number: 8062964Abstract: The present disclosure passivates solar cell defects. Plasma immersion ion implantation (PIII) is used to repair the defects during or after making the solar cell. Hydrogen ion is implanted into absorption layer with different sums of energy to fill gaps of defects or surface recombination centers. Thus, solar cell defects are diminished and carriers are transferred with improved photovoltaic conversion efficiency.Type: GrantFiled: August 9, 2010Date of Patent: November 22, 2011Assignee: Atomic Energy CouncilInventors: Wen-Fa Tsai, Jyong-Fong Liao, Yen-Yu Chen, Chee Wee Liu, Chi-Fong Ai
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Publication number: 20110275195Abstract: A method of treating a semiconductor device wherein there is provided a semiconductor device, the semiconductor device being at least in part chemically bonded to an undesired chemical species. The semiconductor device is subjected to light of a wavelength sufficient to cleave at least some of the chemical bonds between the semiconductor device and the undesired chemical species, and the semiconductor device is exposed to a source of a desired chemical species, such that the semiconductor device becomes at least in part chemically bonded to the desired chemical species.Type: ApplicationFiled: May 6, 2010Publication date: November 10, 2011Inventor: Roy Meade
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Patent number: 8034694Abstract: An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.Type: GrantFiled: March 10, 2008Date of Patent: October 11, 2011Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hideto Ohnuma, Tetsuya Kakehata, Yoichi Iikubo
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Patent number: 8012289Abstract: The invention relates to a method of fabricating a release substrate produced from semiconductor materials, the method comprising creating a reversible connection between two substrate release layers characterized in that the reversible connection is formed by a connecting layer produced using a first material as the basis, the connecting layer further comprising a nanoparticle concentrating zone of a second material disposed to facilitate release of the substrate, the first and second materials being selected to maintain the bonding energy of the reversible connection substantially constant even when the substrate is exposed to heat treatment.Type: GrantFiled: February 25, 2009Date of Patent: September 6, 2011Assignee: S.O.I.Tec Silicon on Insulator TechnologiesInventors: Olivier Rayssac, Pierre Rayssac, legal representative, Gisèle Rayssac, legal representative, Takeshi Akatsu
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Patent number: 7972941Abstract: A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.Type: GrantFiled: July 1, 2008Date of Patent: July 5, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Won Hong, Gil-Heyun Choi, Jong-Myeong Lee, Geum-Jung Seong
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Patent number: 7951692Abstract: There is provided a method for suppressing the occurrence of defects such as voids or blisters even in the laminated wafer having an oxide film of a thickness thinner than the conventional one, wherein hydrogen ions are implanted into a wafer for active layer having an oxide film of not more than 50 nm in thickness to form a hydrogen ion implanted layer, and ions other than hydrogen are implanted up to a position that a depth from the surface side the hydrogen ion implantation is shallower than the hydrogen ion implanted layer, and the wafer for active layer is laminated onto a wafer for support substrate through the oxide film, and then the wafer for active layer is exfoliated at the hydrogen ion implanted layer.Type: GrantFiled: November 13, 2008Date of Patent: May 31, 2011Assignee: Sumco CorporationInventors: Satoshi Murakami, Nobuyuki Morimoto, Hideki Nishihata, Akihiko Endo
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Patent number: 7935613Abstract: A silicon-on-insulator wafer (10). The SOI wafer (10) comprises a top silicon layer (6), a silicon substrate (4), and an oxide insulator layer (2) disposed across the wafer (10) and between the silicon substrate (4) and the top silicon layer (6). The oxide insulator layer (2) has at least one of a contoured top surface (8a, 8b, 8c, 8d, 8e) and a contoured bottom surface (12e). Also provided are processes for manufacturing such a SOI wafer (10).Type: GrantFiled: December 16, 2003Date of Patent: May 3, 2011Assignee: International Business Machines CorporationInventor: Levent Gulari
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Publication number: 20110053351Abstract: The present disclosure passivates solar cell defects. Plasma immersion ion implantation (PIII) is used to repair the defects during or after making the solar cell. Hydrogen ion is implanted into absorption layer with different sums of energy to fill gaps of defects or surface recombination centers. Thus, solar cell defects are diminished and carriers are transferred with improved photovoltaic conversion efficiency.Type: ApplicationFiled: August 9, 2010Publication date: March 3, 2011Applicant: ATOMIC ENERGY COUNCIL-INSTITUTE OF NUCLEAR ENERGY RESEARCHInventors: Wen-Fa Tsai, Jyong-Fong Liao, Yen-Yu Chen, Chee Wee Liu, Chi-Fong Ai
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Patent number: 7897489Abstract: A method of selectively attaching a capping agent to an H-passivated Si or Ge surface is disclosed. The method includes providing the H-passivated Si or Ge surface, the H-passivated Si or Ge surface including a set of covalently bonded Si or Ge atoms and a set of surface substitutional atoms, wherein the set of surface substitutional atoms includes at least one of boron atoms, aluminum atoms, gallium atoms, indium atoms, tin atoms, lead atoms, phosphorus atoms, arsenic atoms, sulfur atoms, and bismuth atoms. The method also includes exposing the set of surface functional atoms to a set of capping agents, each capping agent of the set of capping agents having a set of functional groups bonded to a pair of carbon atoms, wherein the pair of carbon atoms includes at least one pi orbital bond, and further wherein a covalent bond is formed between at least some surface substitutional atoms of the set of surface substitutional atoms and at least some capping agents of the set of capping agents.Type: GrantFiled: June 17, 2008Date of Patent: March 1, 2011Assignee: Innovalight, Inc.Inventor: Elena Rogojina
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Patent number: 7892934Abstract: On the side of a surface (the bonding surface side) of a single crystal Si substrate, a uniform ion implantation layer is formed at a prescribed depth (L) in the vicinity of the surface. The surface of the single crystal Si substrate and a surface of a transparent insulating substrate as bonding surfaces are brought into close contact with each other, and bonding is performed by heating the substrates in this state at a temperature of 350° C. or below. After this bonding process, an Si—Si bond in the ion implantation layer is broken by applying impact from the outside, and a single crystal silicon thin film is mechanically peeled along a crystal surface at a position equivalent to the prescribed depth (L) in the vicinity of the surface of the single crystal Si substrate.Type: GrantFiled: November 1, 2006Date of Patent: February 22, 2011Assignee: Shin-Etsu Chemical Co., Ltd.Inventors: Makoto Kawai, Yoshihiro Kubota, Atsuo Ito, Koichi Tanaka, Yuuji Tobisaka, Shoji Akiyama
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Publication number: 20110008950Abstract: Apparatus and methods for repairing silicon dangling bonds resulting from semiconductor processing are disclosed. The silicon dangling bonds can be repaired by introducing hydrogen radicals with substantially no hydrogen ions into the processing chamber to react with the silicon dangling bonds, eliminating them.Type: ApplicationFiled: April 9, 2010Publication date: January 13, 2011Applicant: Applied Materials, Inc.Inventor: Zhi Xu
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Method and system for passivation of defects in mercury cadmium telluride based optoelectric devices
Publication number: 20100327276Abstract: Apparatus and method to improve the operating parameters of HgCdTe-based optoelectric devices by the addition of hydrogen to passivate dislocation defects. A chamber and a UV light source are provided. The UV light source is configured to provide UV radiation within the chamber. The optoelectric device, which may comprise a HgCdTe semiconductor, is placed into the chamber and may be held in position by a sample holder. Hydrogen gas is introduced into the chamber. The material is irradiated within the chamber by the UV light source with the device and hydrogen gas present within the chamber to cause absorption of the hydrogen into the material.Type: ApplicationFiled: July 7, 2010Publication date: December 30, 2010Applicant: Amethyst Research, IncInventors: Orin W. Holland, Terry D. Golding, John H. Dinan, Ronald Paul Hellmer -
Patent number: 7838400Abstract: A method of manufacturing a solar cell is provided. One surface of a semiconductor substrate is doped with a n-type dopant. The substrate is then subjected to a thermal oxidation process to form an oxide layer on one or both surfaces of the substrate. The thermal process also diffuses the dopant into the substrate, smoothing the concentration profile. The smoothed concentration gradient enables the oxide layer to act as a passivating layer. Anti-reflective coatings may be applied over the oxide layers, and a reflective layer may be applied on the surface opposite the doped surface to complete the solar cell.Type: GrantFiled: July 17, 2008Date of Patent: November 23, 2010Assignee: Applied Materials, Inc.Inventor: Peter Borden
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Patent number: 7833882Abstract: A method of producing a semiconductor device, including: a first plasma processing step of processing a surface of a resin layer laid on a semiconductor element and containing silicon, with a first plasma generated from a gas containing oxygen and fluorine, thereby forming an oxide film; and an electrode pad forming step of forming an electrode pad of a metal on the oxide film.Type: GrantFiled: January 10, 2007Date of Patent: November 16, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yukihiro Tsuji, Toshio Nomaguchi