By Implanting Or Irradiating Patents (Class 438/473)
  • Patent number: 10490401
    Abstract: Methods for fabricating a graphene nanoribbon array in accordance with several embodiments of the present invention can include the steps of depositing PMMA dots on a substrate in an m×n grid, to selectively seed graphene flakes on the substrate by controlling the growth of the graphene flakes on the substrate during the graphene deposition. The methods can further include the steps of masking the graphene flake edges with an insulator layer, at a very low deposition time or at a lower precursor concentration, to ensure there are not enough insulator molecules to form a complete layer over the flakes, but only enough insulator to form around the flakes edges. Once the graphene flake edges are masked, the bulk graphene can be etched, and the masking insulator can be removed to expose the resulting graphene nanoribbon.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: November 26, 2019
    Assignee: United States of America as represented by Secretary of the Navy
    Inventor: Mitchell B. Lerner
  • Patent number: 10350710
    Abstract: A laser irradiation method sets scan lines in an x direction in parallel, and in a y direction to be separate by an inter-scan-line distance Py corresponding to laser irradiation areas of a processing target object, orients a length direction of a linear laser spot with length Wy and width Wx in the y direction, and irradiates target object with the laser spot in each of irradiation positions arranged at width direction intervals ? while moving the laser spot relative to the target object along the scan lines. The method includes determining the inter-scan-line distance Py, the width direction interval ?, and a position shift quantity ?x (where, 0<?x<?) so that the irradiation positions on adjacent scan lines are shifted in the x direction by the position shift quantity ?x and a cumulative value of the applied laser intensity is substantially equalized.
    Type: Grant
    Filed: April 8, 2015
    Date of Patent: July 16, 2019
    Assignee: THE JAPAN STEEL WORKS, LTD.
    Inventors: Yasuhiro Yamashita, Ryosuke Sato, Toshio Inami
  • Patent number: 9991122
    Abstract: A method of forming a semiconductor device structure comprises forming at least one 2D material over a substrate. The at least one 2D material is treated with at least one laser beam having a frequency of electromagnetic radiation corresponding to a resonant frequency of crystalline defects within the at least one 2D material to selectively energize and remove the crystalline defects from the at least one 2D material. Additional methods of forming a semiconductor device structure, and related semiconductor device structures, semiconductor devices, and electronic systems are also described.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: June 5, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Roy E. Meade, Sumeet C. Pandey
  • Patent number: 9396947
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: July 19, 2016
    Assignee: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph M. Benedetto
  • Patent number: 9378955
    Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: June 28, 2016
    Assignee: Aeroflex Colorado Springs Inc.
    Inventors: David B. Kerwin, Joseph M. Benedetto
  • Patent number: 9281197
    Abstract: A semiconductor wafer is set in a laser irradiation apparatus, and laser beam irradiation is performed while the semiconductor wafer is moved. At this time, a laser beam emitted from a laser generating apparatus is condensed by a condensing lens so that the condensing point (focal point) is positioned at a depth of several tens of?m or so from one surface of the semiconductor wafer. Thereby, the crystal structure of the semiconductor wafer in the position having such a depth is modified, and a gettering sink is formed.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: March 8, 2016
    Assignee: SUMCO CORPORATION
    Inventor: Kazunari Kurita
  • Patent number: 9024414
    Abstract: A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: May 5, 2015
    Assignee: SK Hynix Inc.
    Inventor: Jae Bum Kim
  • Patent number: 8999826
    Abstract: Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Schmidt, Josef Bauer
  • Patent number: 8993461
    Abstract: A method for curing defects associated with the implantation of atomic species into a semiconductor layer transferred onto a receiver substrate, wherein the semiconductor layer is thermally insulated from the receiver substrate by a low thermal conductivity layer having thermal conductivity that is lower than that of the transferred semiconductor layer. The method includes applying a selective electromagnetic irradiation to the semiconductor layer to heat that layer to a temperature lower than its temperature of fusion to cure defects without causing an increase in the temperature of the receiver substrate beyond 500° C.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 31, 2015
    Assignee: Soitec
    Inventors: Ionut Radu, Christophe Gourdel, Christelle Vetizou
  • Patent number: 8993415
    Abstract: In a method, a gate dielectric film is formed on a semiconductor substrate. A gate electrode is formed on the gate dielectric film. Impurities of a first conduction-type are introduced into a drain-layer formation region. The impurities of the first conduction-type in the drain-layer formation region are activated by performing heat treatment. Single crystals of the semiconductor substrate in a source-layer formation region are amorphized by introducing inert impurities into the source-layer formation region. Impurities of a second conduction-type is introduced into the source-layer formation region. At least an amorphous semiconductor in the source-layer formation region is brought into a single crystal semiconductor and the impurities of the second conduction-type in the source-layer formation region is activated by irradiating the semiconductor substrate with microwaves.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaka Miyano, Toshitaka Miyata
  • Patent number: 8980728
    Abstract: A method of manufacturing a semiconductor apparatus is disclosed. A first-type doped layer, a second-type doped layer, and an internal electrical connection layer are formed. The internal electrical connection layer is deposited and electrically coupled between the first-type doped layer and the second-type doped layer. In one embodiment, the internal electrical connection layer is formed by using a group IV based precursor and nitrogen based precursor. In another embodiment, the internal electrical connection layer is formed by a mixture comprising a carbon-contained doping source, and the internal electrical connection layer has a carbon concentration greater than 1017 atoms/cm3. In a further embodiment, the internal electrical connection layer is formed at a temperature lower than those of the first-type doped layer and the second-type doped layer.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: March 17, 2015
    Assignee: Phostek, Inc.
    Inventors: Yen-Chang Hsieh, Jinn Kong Sheu, Heng Liu, Chun-Chao Li, Ya-Hsuan Shih, Chia-Nan Chen
  • Patent number: 8975164
    Abstract: The present invention provides a method of manufacturing a semiconductor device. The method at least comprises the following steps. First, the semiconductor device, which comprises a gate, a gate dielectric layer, an active layer, a source and a drain, is manufactured. However, the semiconductor device has a plurality of defects, and the active layer is a metal oxide thin film. After annealing the semiconductor device, it will be transferred into a chamber. A final step of injecting a supercritical fluid carried with a co-solvent into the chamber is then performed to modify the abovementioned defects.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: March 10, 2015
    Assignee: National Chiao Tung University
    Inventors: Po-Tsun Liu, Wei-Ya Wang, Li-Feng Teng
  • Patent number: 8936969
    Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die separated by a non-active region. The semiconductor die can be circular or polygonal with three or more sides. A plurality of bumps is formed over the semiconductor die. A portion of semiconductor wafer is removed to thin the semiconductor wafer. A wafer ring is mounted to mounting tape. The semiconductor wafer is mounted to the mounting tape within the wafer ring. The mounting tape includes translucent or transparent material. A penetrable layer is applied over the bumps formed over the semiconductor wafer. An irradiated energy from a laser is applied through the mounting tape to the non-active region to form a modified region within the non-active region. The semiconductor wafer is singulated along the modified region to separate the semiconductor die.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Hunteak Lee, Daewook Yang, Yeongbeom Ko
  • Publication number: 20150017785
    Abstract: A method of forming a salicide block with reduced defects is disclosed, the method including performing an ultraviolet cure process on a silicon nitride layer deposited in a previous step. High-energy ultraviolet light used in the ultraviolet cure process breaks the hydrogen-containing chemical bonds such as silicon-hydrogen and nitrogen-hydrogen in the silicon nitride layer, and the dissociated hydrogen forms molecular hydrogen which is thereafter evacuated away by a vacuuming apparatus. In this way, the hydrogen content in the silicon nitride layer can be effectively decreased and the reaction between hydrogen in the silicon nitride layer and photoresist subsequently coated thereon can hence be reduced. As a result, a salicide block with reduced defects can be obtained, thus improving process reliability and product yield.
    Type: Application
    Filed: November 15, 2013
    Publication date: January 15, 2015
    Applicant: Shanghai Huali Microelectronics Corporation
    Inventors: Meimei Gu, Chien Wei Chen, Yijun Yi, Hsu Sheng Chang
  • Publication number: 20150008478
    Abstract: A manufacturing method of a semiconductor device includes applying at least one of a particle ray and a radial ray to a surface of a semiconductor substrate on which a transistor including a gate insulation film and a gate electrode has been formed adjacent to the surface, and annealing the semiconductor substrate for recovering a crystal defect contained in the gate insulation film and the gate electrode, after the applying. Further, the manufacturing method includes pre-annealing for reducing a content of a hydrogen molecule and a water molecule contained in the gate insulation film and the gate electrode to a predetermined concentration, before the applying. In the semiconductor device manufactured by this method, a concentration of thermally stable defect existing in the gate insulation film is reduced to a predetermined concentration.
    Type: Application
    Filed: January 22, 2013
    Publication date: January 8, 2015
    Inventors: Weitao Cheng, Shinji Amano, Yoshifumi Okabe, Tomofusa Shiga
  • Publication number: 20140374882
    Abstract: A semiconductor device includes a semiconductor portion with one or more impurity zones of the same conductivity type. A first electrode structure is electrically connected to the one or more impurity zones in a cell area of the semiconductor portion. At least in an edge area surrounding the cell area a recombination center density in the semiconductor portion is higher than in an active portion of the cell area.
    Type: Application
    Filed: June 21, 2013
    Publication date: December 25, 2014
    Inventors: Ralf Siemieniec, Hans-Joachim Schulze, Stefan Gamerith, Hans Weber
  • Patent number: 8895407
    Abstract: A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: November 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Akihisa Shimomura, Tatsuya Mizoi, Eiji Higa, Yoji Nagano
  • Patent number: 8865571
    Abstract: A method for manipulating dislocations from a semiconductor device includes directing a light-emitting beam locally onto a surface portion of a semiconductor body that includes active regions of the semiconductor device and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam. Manipulating the plurality of dislocations includes directly scanning the plurality of dislocations with the light-emitting beam to manipulate a location of each of the plurality of dislocations on the surface portion of the semiconductor body by adjusting a temperature of the surface portion of the semiconductor body corresponding to the plurality of dislocations and adjusting a scan speed of the a light-emitting beam.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chung Woh Lai, Xiao Hu Liu, Anita Madan, Klaus W. Schwarz, J. Campbell Scott
  • Patent number: 8865572
    Abstract: A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a plurality of dislocations, the moveable laser being characterized as having a scan speed, the moveable laser manipulates the plurality of dislocations on the surface portion of the semiconductor body by adjusting the temperature and the scan speed of the laser beam.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chung Woh Lai, Xiao Hu Liu, Anita Madan, Klaus W. Schwarz, J. Campbell Scott
  • Patent number: 8866147
    Abstract: A semiconductor structure includes a III-nitride substrate and a drift region coupled to the III-nitride substrate along a growth direction. The semiconductor substrate also includes a channel region coupled to the drift region. The channel region is defined by a channel sidewall disposed substantially along the growth direction. The semiconductor substrate further includes a gate region disposed laterally with respect to the channel region.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: October 21, 2014
    Assignee: Avogy, Inc.
    Inventors: Richard J. Brown, Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, David P. Bour
  • Patent number: 8852997
    Abstract: A method for purifying an n-type ZnO and/or ZnMgO substrate to reduce or eliminate the residual extrinsic impurities including introducing a reactive species having strong chemical affinity for at least one of the residual extrinsic impurities, and/or being capable of creating crystalline defects, is introduced in at least one region of the substrate, the reactive species being P, and whereby at least one getter region capable of trapping the said residual extrinsic impurities and/or in which the residual extrinsic impurities are trapped is created in the substrate; then annealing the substrate to cause diffusion of the residual extrinsic impurities towards the getter region and/or to outside the getter region. A method for preparing a p-doped ZnO and/or ZnMgO substrate comprising purifying an n-type ZnO and/or ZnMgO substrate using the above purification method in which one or more reactive species are used not limited to phosphorus alone.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: October 7, 2014
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Isabelle Bisotto, Guy Feuillet
  • Publication number: 20140273404
    Abstract: In some embodiments, methods are described that allow the processing of a substrate using microwave-based degas systems. The methods allow process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be investigated. In some embodiments, apparatus are described that allow the investigation of process variables used in microwave-based degas systems to remove adsorbed species from the surface of a substrate. The apparatus allow process variables such as power, dwell time, frequency, backside cooling gas usage, backside cooling gas flow rate, and the like to be investigated.
    Type: Application
    Filed: November 27, 2013
    Publication date: September 18, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Kent Riley Child, Minh Huu Le
  • Publication number: 20140264757
    Abstract: Embodiments of the present invention provide metal structures for transporting or gettering materials disposed on or within a semiconductor substrate. A structure for transporting a material disposed on or within a semiconductor substrate may include a metal structure disposed within the semiconductor substrate and at a spaced distance from the material. The metal structure is configured to transport the material through the semiconductor substrate and to concentrate the material at the metal structure. The material may include a contaminant disposed within the semiconductor substrate, e.g., that originates from electronic circuitry on the substrate.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: The Aerospace Corporation
    Inventors: Nathan Presser, David P. Taylor
  • Publication number: 20140273405
    Abstract: A method for reducing light point defects of a semiconductor-on-insulator structure and a method for reducing the surface roughness of a semiconductor-on-insulator structure are disclosed. The methods can include a combination of thermally annealing the structure followed by a non-contact smoothing process.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Inventors: Qingmin Liu, Jeffrey L. Libbert
  • Patent number: 8835284
    Abstract: Annealed wafers having reduced residual voids after annealing and reduced deterioration of TDDB characteristics of an oxide film formed on the annealed wafer, while extending the range of nitrogen concentration contained in a silicon single crystal, are prepared by a method wherein crystal pulling conditions are controlled such that a ratio V/G between a crystal pulling rate V and an average axial temperature gradient G is ?0.9×(V/G)crit and ?2.5×(V/G)crit, and hydrogen partial pressure is ?3 Pa and ?40 Pa. The silicon single crystal has a nitrogen concentration of >5×1014 atoms/cm3 and ?6×1015atoms/cm3, a carbon concentration of ?1×1015 atoms/cm3 and ?9×1015 atoms/cm3, and heat treatment is performed in a noble gas atmosphere having an impurity concentration of ?5 ppma, or in a non-oxidizing atmosphere.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: September 16, 2014
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Masamichi Ohkubo
  • Patent number: 8815708
    Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer of the SiC crystal layer to introduce carbon interstitials into the surface layer, and (b) growing the SiC layer upward from the edge face of the surface layer into which the carbon interstitials have been introduced, and diffusing out the carbon interstitials that have been introduced into the surface layer from the surface layer into the grown layer and combining the carbon interstitials and point defects to make the electrically active point defects in the grown layer inactive.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: August 26, 2014
    Assignee: Central Research Institute of Electric Power Industry
    Inventors: Hidekazu Tsuchida, Liutauras Storasta
  • Patent number: 8802457
    Abstract: A method includes performing a grinding to a backside of a semiconductor substrate, wherein a remaining portion of the semiconductor substrate has a back surface. A treatment is then performed on the back surface using a method selected from the group consisting essentially of a dry treatment and a plasma treatment. Process gases that are used in the treatment include oxygen (O2). The plasma treatment is performed without vertical bias in a direction perpendicular to the back surface.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: August 12, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Lai, Cheng-Ta Wu, Kai-Chun Hsu, Yeur-Luen Tu, Ching-Chun Wang, Chia-Shiung Tsai
  • Patent number: 8796116
    Abstract: Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: August 5, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Alexis Grabbe, Larry Flannery
  • Publication number: 20140204967
    Abstract: A thermal shunt is to transfer heat from a sidewall of a device to a silicon substrate. The device is associated with a Silicon-On-Insulator (SOI) including a buried oxide layer. The thermal shunt extends through the buried oxide layer to the silicon substrate.
    Type: Application
    Filed: August 31, 2011
    Publication date: July 24, 2014
    Inventor: Di Liang
  • Publication number: 20140199822
    Abstract: A method of forming a semiconductor device structure. The method comprises forming an insulative material on a semiconductive material, and microwave annealing at least an interface between the insulative material and the semiconductive material. Additional methods of forming a semiconductor device structure, and related semiconductor device structures and a semiconductor device are also described.
    Type: Application
    Filed: January 15, 2013
    Publication date: July 17, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Kunal Shrotri
  • Publication number: 20140193964
    Abstract: The present invention provides a method of manufacturing a semiconductor device. The method at least comprises the following steps. First, the semiconductor device, which comprises a gate, a gate dielectric layer, an active layer, a source and a drain, is manufactured. However, the semiconductor device has a plurality of defects, and the active layer is a metal oxide thin film. After annealing the semiconductor device, it will be transferred into a chamber. A final step of injecting a supercritical fluid carried with a co-solvent into the chamber is then performed to modify the abovementioned defects.
    Type: Application
    Filed: May 30, 2013
    Publication date: July 10, 2014
    Applicant: National Chiao Tung University
    Inventors: Po-Tsun LIU, Wei-Ya WANG, Li-Feng TENG
  • Patent number: 8772129
    Abstract: A manufacturing method of an SOI substrate which possesses a base substrate having low heat resistance and a very thin semiconductor layer having high planarity is demonstrated. The method includes: implanting hydrogen ions into a semiconductor substrate to form an ion implantation layer; bonding the semiconductor substrate and a base substrate such as a glass substrate, placing a bonding layer therebetween; heating the substrates bonded to each other to separate the semiconductor substrate from the base substrate, leaving a thin semiconductor layer over the base substrate; irradiating the surface of the thin semiconductor layer with laser light to improve the planarity and recover the crystallinity of the thin semiconductor layer; and thinning the thin semiconductor layer. This method allows the formation of an SOI substrate which has a single-crystalline semiconductor layer with a thickness of 100 nm or less over a base substrate.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: July 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Akihisa Shimomura, Tatsuya Mizoi, Eiji Higa, Yoji Nagano
  • Publication number: 20140187021
    Abstract: This invention relates to a method of healing defects at junctions of a semiconductor device, which includes growing a p-Ge layer on a substrate, performing ion implantation on the p-Ge layer to form an n+ Ge region or performing in-situ doping on the p-Ge layer and then etching to form an n+ Ge region or depositing an oxide film on the p-Ge layer and performing patterning, etching and in-situ doping to form an n+ Ge layer, forming a capping oxide film, performing annealing at 600˜700° C. for 1˜3 hr, and depositing an electrode, and in which annealing enables Ge defects at n+/p junctions to be healed and the depth of junctions to be comparatively reduced, thus minimizing leakage current, thereby improving properties of the semiconductor device and achieving high integration and fineness of the semiconductor device.
    Type: Application
    Filed: November 21, 2013
    Publication date: July 3, 2014
    Applicant: Korea Advanced Nano Fab Center
    Inventors: Won Kyu Park, Jong Gon Heo, Dong Hwan Jun, Jin Hong Park, Jae Woo Shim
  • Patent number: 8759196
    Abstract: A method for preparing a substrate for detaching a layer by irradiation of the substrate with a light flux for heating a buried region of the substrate and bringing about decomposition of the material of that region to detach the detachment layer. The method includes fabricating an intermediate substrate including a first buried layer, and a second covering layer that covers all or part of the first layer, with the covering layer being substantially transparent to the light flux and with the buried layer formed by implantation of particles into the substrate, followed by absorbing the flux, and selectively and adiabatically irradiating a treated region of the buried layer until at least partial decomposition of the material constituting it ensues.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: June 24, 2014
    Assignee: Soitec
    Inventor: Michel Bruel
  • Publication number: 20140170837
    Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 19, 2014
    Applicant: IMEC
    Inventors: Benjamin Vincent, Geert Eneman
  • Publication number: 20140154872
    Abstract: A method for generating patterned strained regions in a semiconductor device is provided. The method includes directing a light-emitting beam locally onto a surface portion of a semiconductor body; and manipulating a plurality of dislocations located proximate to the surface portion of the semiconductor body utilizing the light-emitting beam, the light-emitting beam being characterized as having a scan speed, so as to produce the patterned strained regions.
    Type: Application
    Filed: February 7, 2014
    Publication date: June 5, 2014
    Applicant: International Business Machines Corporation
    Inventors: Chung Woh Lai, Xiao Hu Liu, Anita Madan, Klaus W. Schwarz, J. Campbell Scott
  • Publication number: 20140154873
    Abstract: A system for manipulating dislocations on semiconductor devices, includes a moveable laser configured to generate a laser beam locally on a surface portion of the semiconductor body having a plurality of dislocations, the moveable laser being characterized as having a scan speed, the moveable laser manipulates the plurality of dislocations on the surface portion of the semiconductor body by adjusting the temperature and the scan speed of the laser beam.
    Type: Application
    Filed: February 7, 2014
    Publication date: June 5, 2014
    Applicant: International Business Machines Corporation
    Inventors: Chung Woh Lai, Xiao Hu Liu, Anita Madan, Klaus W. Schwarz, J. Campbell Scott
  • Patent number: 8741740
    Abstract: An SOI substrate is manufactured by forming an embrittled layer in a bond substrate by increasing the dose of hydrogen ions in the formation of the embrittled layer to a value more than the dose of hydrogen ions of the lower limit for separation of the bond substrate, separating the bond substrate attached to the base substrate, forming an SOI substrate in which a single crystal semiconductor film is formed over the base substrate, and irradiating a surface of the single crystal semiconductor film with laser light.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: June 3, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Hajime Tokunaga
  • Patent number: 8697503
    Abstract: A method of manufacturing a thin film electronic device includes applying a plastic coating to a rigid carrier substrate using a wet casting process, the plastic coating forming a plastic substrate and include a transparent plastic material doped with a UV absorbing additive. Thin film electronic elements are formed over the plastic substrate, and the rigid carrier substrate is released from the plastic substrate. This method forms transparent substrate materials suitable for a laser release process, through doping of the plastic material of the substrate with a UV absorber. This UV absorber absorbs in the wavelength of the lift-off laser (for example 308-351 nm, or 355 nm) with a very high absorption.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: April 15, 2014
    Assignee: Koninklijke Philips N.V.
    Inventors: Eliav Itzhak Haskal, David James McCulloch, Dirk Jan Broer
  • Patent number: 8697555
    Abstract: The invention offers a method of producing a semiconductor device that can suppress the worsening of the property due to surface roughening of a wafer by sufficiently suppressing the surface roughening of the wafer in the heat treatment step and a semiconductor device in which the worsening of the property caused by the surface roughening is suppressed. The method of producing a MOSFET as a semiconductor device is provided with a step of preparing a wafer 3 made of silicon carbide and an activation annealing step that performs activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in an atmosphere containing a vapor of silicon carbide generated from the SiC piece 61, which is a generating source other than the wafer 3.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: April 15, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Fujikawa, Shin Harada, Yasuo Namikawa, Takeyoshi Masuda
  • Publication number: 20140080289
    Abstract: Disclosed herein is a method of forming a gettering layer for capturing metallic ions on the back side of a semiconductor wafer formed with devices on the face side thereof. The method includes irradiating the back-side surface of the semiconductor wafer with a pulsed laser beam having a pulse width corresponding to a thermal diffusion length of 10 to 230 nm, to thereby form the gettering layer.
    Type: Application
    Filed: September 17, 2013
    Publication date: March 20, 2014
    Applicant: DISCO CORPORATION
    Inventors: Hiroshi Morikazu, Nao Hattori
  • Patent number: 8674327
    Abstract: Systems and methods for uniformly implanting materials on substrates using directed magnetic fields are provided. One such system includes a chamber configured to receive a preselected material and to enclose a first substrate, first and second rotating assemblies configured to facilitate an implantation of the preselected material onto first and second surfaces of the first substrate and including first and second rotating magnet sub-assemblies configured to direct magnetic fields onto the first and second surfaces, and an RF energizer configured to apply RF energy to the first substrate, where the first magnetic field and the second magnetic field combine to form a resultant magnetic field that is substantially parallel along the first surface, and where the implantation of the preselected material onto the first substrate occurs based on a combination of the RF energy and the resultant magnetic field.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: March 18, 2014
    Assignee: WD Media, LLC
    Inventors: Chin Yim Poon, Yew Ming Chiong, Paul C. Dorsey, Tatsuru Tanaka
  • Patent number: 8658516
    Abstract: An object of the present invention is to provide a method of producing a silicon wafer and a method of producing an epitaxial wafer, which enable easily forming a gettering site in a relatively short period of time and effectively suppressing occurrence of dislocation induced by internal stresses. Specifically, the present invention provides a method of producing a silicon wafer, comprising: irradiating a first laser beam having a relatively long wavelength and a second laser beam having a relatively short wavelength onto a portion of a silicon wafer located at a predetermined depth measured from a surface of the silicon wafer, wherein the first laser beam is concentrated at a portion located at a predetermined depth of the wafer to form a process-affected layer for gettering heavy metals thereat, the second laser beam is concentrated at a beam-concentration portion in the vicinity of the surface of the wafer to melt the beam-concentration portion, the beam-concentration portion is then recrystallized.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: February 25, 2014
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita
  • Patent number: 8642449
    Abstract: A silicon wafer which has DZ layers formed on both sides thereof by heat treatment in an atmosphere of reducing gas (such as hydrogen) or rare gas (such as argon) with a specific temperature profile for heating, holding, and cooling, and which also has a gettering site of BMD in the bulk inside the DZ layer. A silicon wafer which has a silicon epitaxial layer formed on one side thereof. The DZ layer and the silicon epitaxial layer contain dissolved oxygen introduced into their surface parts, with the concentration and distribution of dissolved oxygen properly controlled. Introduction of oxygen into the surface part is accomplished by heat treatment and ensuing rapid cooling in an atmosphere of oxygen-containing gas.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: February 4, 2014
    Assignee: Globalwafers Japan Co., Ltd.
    Inventors: Takashi Watanabe, Ryuji Takeda
  • Publication number: 20140024200
    Abstract: A film deposition apparatus includes a turntable to rotate a substrate thereon, a process gas supply part to supply a process gas to form a thin film on the substrate, a heating part to heat the substrate up to a predetermined film deposition temperature to form a thin film, a plasma treatment part to treat the thin film for modification, a heat lamp provided above the turntable and configured to heat the substrate up to a temperature higher than the predetermined film deposition temperature by irradiating the substrate with light in an adsorption wavelength range of the substrate, and a control part to output a control signal so as to repeat a step of depositing the thin film and a step of modifying the thin film by the plasma, and then to stop supplying the process gas and to heat the substrate by the heat lamp.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 23, 2014
    Inventors: Hitoshi KATO, Shigehiro Miura
  • Patent number: 8629044
    Abstract: An object of the present invention is to provide a method of producing a silicon wafer and a method of producing an epitaxial wafer, which enable easily forming a gettering site in a relatively short period of time and effectively suppressing occurrence of dislocation induced by internal stresses. Specifically, the present invention provides a method of producing a silicon wafer, comprising: irradiating a first laser beam having a relatively long wavelength and a second laser beam having a relatively short wavelength onto a portion of a silicon wafer located at a predetermined depth measured from a surface of the silicon wafer, wherein the first laser beam is concentrated at a portion located at a predetermined depth of the wafer to form a process-affected layer for gettering heavy metals thereat, the second laser beam is concentrated at a beam-concentration portion in the vicinity of the surface of the wafer to melt the beam-concentration portion, the beam-concentration portion is then recrystallized.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: January 14, 2014
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita
  • Publication number: 20140001605
    Abstract: A method includes: a backside-oxidation-film-formation step in which an oxidation film is formed on a backside of a silicon wafer; a backside-oxidation-film-removal step in which the oxidation film provided at an outer periphery of the silicon wafer is removed; an argon-annealing step in which the silicon wafer after the backside-oxidation-film-removal step is subjected to a heat treatment in an argon gas atmosphere at a temperature in a range from 1200 to 1220 degrees C. for 60 minutes or more and 120 minutes or less; and an epitaxial-film-formation step in which an epitaxial film is formed on a surface of the silicon wafer after the argon-annealing step.
    Type: Application
    Filed: June 24, 2013
    Publication date: January 2, 2014
    Inventors: Tadashi Kawashima, Naoya Nonaka, Masayuki Shinagawa, Gou Uesono
  • Patent number: 8609461
    Abstract: Various embodiments provide methods for forming a diamond heat spreader and integrating the diamond heat spreader with a heat source without generating voids at the interface. In one embodiment, a semiconductor layer can be epitaxially formed on a diamond substrate having a desirably low surface root mean square (RMS) roughness. The semiconductor epi-layer can be used as an interface layer for bonding the diamond substrate to the heat source to provide efficient heat spreading.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: December 17, 2013
    Assignee: STC.UNM
    Inventors: Ganesh Balakrishnan, Jerome V. Moloney, Victor Hasson
  • Patent number: 8569149
    Abstract: A method of treating a semiconductor device wherein there is provided a semiconductor device, the semiconductor device being at least in part chemically bonded to an undesired chemical species. The semiconductor device is subjected to light of a wavelength sufficient to cleave at least some of the chemical bonds between the semiconductor device and the undesired chemical species, and the semiconductor device is exposed to a source of a desired chemical species, such that the semiconductor device becomes at least in part chemically bonded to the desired chemical species.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: October 29, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Roy Meade
  • Patent number: RE45238
    Abstract: A silicon wafer in which both occurrences of slip dislocation and warpage are suppressed in device manufacturing processes is a silicon wafer having BMDs having an octahedral shape, wherein BMDs located at a position below the silicon wafer surface to a depth of 20 ?m and having a diagonal length of 200 nm or more are present at a concentration of ?2×109/cm3, and BMDs located at a position below a depth ?50 ?m have a diagonal length of ?10 nm to ?50 nm and a concentration of ?1×1012/cm3.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: November 11, 2014
    Assignee: Siltronic AG
    Inventors: Masayuki Fukuda, Katsuhiko Nakai