By Vapor Phase Surface Reaction Patents (Class 438/477)
  • Patent number: 9887096
    Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch created from a remote plasma etch. The remote plasma excites a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor. Reactants thereby produced etch the patterned heterogeneous structures to remove two separate regions of differing silicon oxide at different etch rates. The methods may be used to remove low density silicon oxide while removing less high density silicon oxide.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: February 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Seung H. Park, Yunyu Wang, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle
  • Patent number: 9029244
    Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: May 12, 2015
    Assignees: Samsung Electronics Co., Ltd., Genitech, Inc.
    Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
  • Publication number: 20150125987
    Abstract: A method for chemically cleaning and passivating a chalcogenide layer is provided, wherein the method comprises bringing the chalcogenide layer into contact with an ammonium sulfide containing ambient, such as an ammonium sulfide liquid solution or an ammonium sulfide containing vapor. Further, a method for fabricating photovoltaic cells with a chalcogenide absorber layer is provided, wherein the method comprises: providing a chalcogenide semiconductor layer on a substrate; bringing the chalcogenide semiconductor layer into contact with an ammonium sulfide containing ambient, thereby removing impurities and passivating the chalcogenide semiconductor layer; and afterwards providing a buffer layer on the chalcogenide semiconductor layer.
    Type: Application
    Filed: September 29, 2014
    Publication date: May 7, 2015
    Inventors: Marie Buffiere, Marc Meuris, Guy Brammertz
  • Patent number: 8999864
    Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: April 7, 2015
    Assignee: Global Wafers Japan Co., Ltd.
    Inventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
  • Patent number: 8895410
    Abstract: A cause of deteriorating the hydrogen termination on the surface of a wafer is found to be water adsorbed on the surface. By exposing the wafer to an inert gas atmosphere containing an H2 gas so as to suppress the oxidation reaction due to the water, it is possible to improve the hydrogen termination on the wafer surface.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: November 25, 2014
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Hiroshi Akahori
  • Patent number: 8759198
    Abstract: A method for fabricating an integrated circuit (IC) includes initial oxidizing of a semiconductor surface of a substrate. The substrate is heated after the initial oxidizing using a plurality of furnace processing steps which each include a peak processing temperature between 800° C. and 1300° C. The furnace processing steps include at least one accelerated processing step having an accelerated ramp portion in a temperature range between 800° C. and 1250° C. providing an accelerated ramp-up rate and/or an |accelerated ramp-down rate| of at least (?) 5.5° C./min.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: June 24, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Bradley David Sucher, Rick L. Wise
  • Publication number: 20140120700
    Abstract: Methods for plasma treatment of films to remove impurities are disclosed herein. Methods for removing impurities can include positioning a substrate with a barrier layer in a processing chamber, the barrier layer comprising a barrier metal and one or more impurities, maintaining the substrate at a bias, creating a plasma comprising a treatment gas, the treatment gas comprising an inert gas, delivering the treatment gas to the substrate to reduce the ratio of one or more impurities in the barrier layer, and reacting a deposition gas comprising a metal halide and hydrogen-containing gas to deposit a bulk metal layer on the barrier layer. The methods can further include the use of diborane to create selective nucleation in features over surface regions of the substrate.
    Type: Application
    Filed: October 31, 2013
    Publication date: May 1, 2014
    Inventors: Benjamin C. WANG, Joshua COLLINS, Michael JACKSON, Avgerinos V. GELATOS, Amit KHANDELWAL
  • Patent number: 8697547
    Abstract: A method for manufacturing a silicon epitaxial wafer, including vapor-phase growing a silicon single crystal thin film on a silicon single crystal substrate in a hydrogen atmosphere while supplying a source gas; and cooling a silicon epitaxial wafer having the formed silicon single crystal thin film by calculating a temperature at which a standard value or a process average value of concentration of an evaluation target impurity present in the silicon single crystal thin film coincides with solubility limit concentration of the evaluation target impurity and setting a cooling rate of the silicon epitaxial wafer after the film formation to be less than 20° C./sec in a temperature range of at least plus or minus 50° C. from the calculated temperature.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: April 15, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Tomosuke Yoshida
  • Patent number: 8685840
    Abstract: An in-situ gettering method for removing impurities from the surface and interior of a upgraded metallurgical grade silicon wafer is continuously conducted in a reaction chamber. Chloride gas is mixed with carrier gas. The gaseous mixture is used to clean the surface of the silicon wafer. Then, the gaseous mixture is used to form a porous structure on the surface of the silicon wafer before hot annealing is executed. Finally, the gaseous mixture is used to execute hot etching on the surface of the silicon wafer and remove the porous structure from the surface of the silicon wafer. As the chloride gas is used to clean the surface of the silicon wafer and form the porous structure on the surface of the silicon wafer, external gettering is improved. Moreover, interstitial-type metal impurities are effectively removed from the interior of the silicon wafer.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: April 1, 2014
    Assignee: Institute of Nuclear Energy Research, Atomic Energy Council
    Inventors: Jin-Jang Jheng, Tsun-Neng Yang, Chin-Chen Chiang
  • Publication number: 20140065799
    Abstract: Methods for improving contact resistance, for example, to a semiconductor region such as a source or a drain region, are disclosed. The methods can include exposing the substrate to an activated hydrogen species to remove contaminant layers such as native oxide layers followed by exposing the substrate to plasma activated dopant species to passivate the surface. The methods can further include depositing a layer on a substrate, wherein the layer can include a first element to form a silicide with the substrate and a second element to lower a contact resistance between the silicide and the substrate. The second element can include a dopant, which can enhance trap assisted tunneling or lower the Schottky barrier height between the silicide layer and the substrate. The cleaning, passivation, and deposition steps are performed in-situ without breaking vacuum.
    Type: Application
    Filed: November 13, 2013
    Publication date: March 6, 2014
    Applicant: Intermolecular, Inc.
    Inventor: Khaled Ahmed
  • Publication number: 20140054609
    Abstract: Large high-quality epitaxial wafers are disclosed. Embodiments of the invention provide silicon carbide epitaxial wafers with low basal plane dislocation (BPD) densities. In some embodiments, these wafers are of the 4H polytype. These wafers can be at least about 100 mm in diameter and have an epitaxial layer from about 1 micron to about 300 microns thick. In some embodiments the wafers include an epitaxial stack with a buffer layer and a drift layer and the (BPD) density in the drift layer is less than about 2 cm?2. A wafer according to embodiments of the invention can be made by placing an SiC substrate wafer in a reactor and using a facile step flow to cause a majority of ad-atoms to be coincident with an edge or kink of an atomic step on a surface of the SiC substrate wafer.
    Type: Application
    Filed: March 5, 2013
    Publication date: February 27, 2014
    Applicant: Cree, Inc.
    Inventors: Albert Augustus Burk, Michael O'Loughlin
  • Patent number: 8569149
    Abstract: A method of treating a semiconductor device wherein there is provided a semiconductor device, the semiconductor device being at least in part chemically bonded to an undesired chemical species. The semiconductor device is subjected to light of a wavelength sufficient to cleave at least some of the chemical bonds between the semiconductor device and the undesired chemical species, and the semiconductor device is exposed to a source of a desired chemical species, such that the semiconductor device becomes at least in part chemically bonded to the desired chemical species.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: October 29, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Roy Meade
  • Patent number: 8569175
    Abstract: The invention relates to a method for dry chemical treatment of substrates selected from the group comprising silicon, ceramic, glass, and quartz glass, in which the substrate is treated in a heated reaction chamber with a gas which contains hydrogen chloride as etching agent, and also to a substrate which can be produced in this way. The invention likewise relates to uses of the previously mentioned method.
    Type: Grant
    Filed: December 6, 2006
    Date of Patent: October 29, 2013
    Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V.
    Inventors: Stefan Reber, Gerhard Willeke
  • Publication number: 20130209781
    Abstract: Methods of fabricating dimensional silica-based substrates or structures comprising a porous silicon layers are contemplated. According to one embodiment, oxygen is extracted from the atomic elemental composition of a silica glass substrate by reacting a metallic gas with the substrate in a heated inert atmosphere to form a metal-oxygen complex along a surface of the substrate. The metal-oxygen complex is removed from the surface of the silica glass substrate to yield a crystalline porous silicon surface portion and one or more additional layers are formed over the crystalline porous silicon surface portion of the silica glass substrate to yield a dimensional silica-based substrate or structure comprising the porous silicon layer. Embodiments are also contemplated where the substrate is glass-based, but is not necessarily a silica-based glass substrate. Additional embodiments are disclosed and claimed.
    Type: Application
    Filed: March 20, 2013
    Publication date: August 15, 2013
    Inventors: Robert Alan Bellman, Nicholas Francis Borrelli, David Alan Deneka, Shawn Michael O'Malley, Vitor Marino Schneider
  • Patent number: 8486813
    Abstract: A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 ?m to approximately 80 ?m from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: July 16, 2013
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jung-Goo Park
  • Patent number: 8470692
    Abstract: The present invention discloses a method and a device for preparing a compound semiconductor film. The method comprises the steps of: providing a substrate above at least an evaporation source in a vacuum condition; heating a source material contained in the evaporation source so that the source material is vapor-deposited on the substrate; and taking out the substrate under protection of an inert gas. The substrate may be rotated around an axis of a plane where the evaporation source is positioned, and the substrate is tilted by a predetermined angle with respect to the plane. The compound semi-conductive film thus prepared has a uniform thickness with a larger area. The method provides a simplified process and enhanced efficiency.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: June 25, 2013
    Assignee: Byd Co., Ltd.
    Inventors: Beijun Zhong, Wenyu Cao, Yong Zhou, Zhanfeng Jiang
  • Publication number: 20130149843
    Abstract: An in-situ gettering method for removing impurities from the surface and interior of a upgraded metallurgical grade silicon wafer is continuously conducted in a reaction chamber. Chloride gas is mixed with carrier gas. The gaseous mixture is used to clean the surface of the silicon wafer. Then, the gaseous mixture is used to form a porous structure on the surface of the silicon wafer before hot annealing is executed. Finally, the gaseous mixture is used to execute hot etching on the surface of the silicon wafer and remove the porous structure from the surface of the silicon wafer. As the chloride gas is used to clean the surface of the silicon wafer and form the porous structure on the surface of the silicon wafer, external gettering is improved. Moreover, interstitial-type metal impurities are effectively removed from the interior of the silicon wafer.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 13, 2013
    Applicant: ATOMIC ENERGY COUNCIL-INSTITUTE OF NUCLEAR ENERGY RESEARCH
    Inventors: Jin-Jang Jheng, Tsun-Neng Yang, Chin-Chen Chiang
  • Patent number: 8436447
    Abstract: In a first aspect, a memory cell is provided, the memory cell including: (a) a first conducting layer formed above a substrate; (b) a second conducting layer formed above the first conducting layer; (c) a structure formed between the first and second conducting layers, wherein the structure includes a sidewall that defines an opening extending between the first and second conducting layers, and wherein the structure is comprised of a material that facilitates selective, directional growth of carbon nano-tubes; and (d) a carbon-based switching layer that includes carbon nano-tubes formed on the sidewall of the structure. Numerous other aspects are provided.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: May 7, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Pankaj Kalra, Raghuveer S. Makala
  • Patent number: 8414790
    Abstract: The various embodiments described in the specification provide improved mechanisms of removal of unwanted deposits on the bevel edge to improve process yield. The embodiments provide apparatus and methods of treating the bevel edge of a copper plated substrate to convert the copper at the bevel edge to a copper compound that can be wet etched with a fluid at a high etch selectivity in comparison to copper. In one embodiment, the wet etch of the copper compound at high selectivity to copper allows the removal of the non-volatile copper at substrate bevel edge in a wet etch processing chamber. The plasma treatment at bevel edge allows the copper at bevel edge to be removed at precise spatial control to about 2 mm or below, such as about 1 mm, about 0.5 mm or about 0.25 mm, to the very edge of substrate.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: April 9, 2013
    Assignee: Lam Research Corporation
    Inventors: Andrew D. Bailey, III, Yunsang Kim
  • Patent number: 8389313
    Abstract: The present invention provides a deposition method of a multilayered structure composed of a III group nitride compound semiconductor having good crystallinity on a substrate. The multilayered structure comprises at least a buffer layer and an underlying layer from the substrate side, and the buffer layer and the underlying layer are formed by a sputtering method. A deposition temperature of the buffer layer is adjusted to a temperature lower than a deposition temperature of the underlying layer, or the thickness of the buffer layer is adjusted to 5 nm to 500 nm. Furthermore, the multilayered structure comprises at least an underlying layer and a light-emissive layer from the substrate side and the underlying layer is formed by a sputtering method, and the method comprises the step of forming the light-emissive layer by a metal-organic chemical vapor deposition (MOCVD method).
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: March 5, 2013
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Hisayuki Miki, Kenzo Hanawa, Yasumasa Sasaki
  • Publication number: 20130040438
    Abstract: A method of depositing an epitaxial layer that includes chemically cleaning the deposition surface of a semiconductor substrate and treating the deposition surface of the semiconductor substrate with a hydrogen containing gas at a pre-bake temperature. The hydrogen containing gas treatment may be conducted in an epitaxial deposition chamber. The hydrogen containing gas removes oxygen-containing material from the deposition surface of the semiconductor substrate. The deposition surface of the semiconductor substrate may then be treated with a gas flow comprised of at least one of hydrochloric acid (HCl), germane (GeH4), and dichlorosilane (H2SiCl2) that is introduced to the epitaxial deposition chamber as temperature is decreased from the pre-bake temperature to an epitaxial deposition temperature. At least one source gas may be applied to the deposition surface for epitaxial deposition of a material layer.
    Type: Application
    Filed: August 9, 2011
    Publication date: February 14, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Hong He, Alexander Reznicek, Devendra K. Sadana, Paul D. Brabant, Keith Chung, Manabu Shinriki
  • Publication number: 20130017672
    Abstract: A plasma treatment method includes: creating a plasma from a mixed gas containing carbon and nitrogen to generate CN active species, and treating a surface of a semiconductor substrate with the CN active species.
    Type: Application
    Filed: July 7, 2012
    Publication date: January 17, 2013
    Applicant: SONY CORPORATION
    Inventors: Nobuyuki Kuboi, Masanaga Fukusawa
  • Publication number: 20120306054
    Abstract: A method of forming a doped semiconductor layer on a substrate is provided. A foundation layer having a crystal structure compatible with a thermodynamically favored crystal structure of the doped semiconductor layer is formed on the substrate and annealed, or surface annealed, to substantially crystallize the surface of the foundation layer. The doped semiconductor layer is formed on the foundation layer. Each layer may be formed by vapor deposition processes such as CVD. The foundation layer may be germanium and the doped semiconductor layer may be phosphorus doped germanium.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 6, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Yi-Chiau Huang, Errol Antonio C. Sanchez, Xianzhi Tao
  • Patent number: 8309407
    Abstract: Methods in accordance with aspects of this invention form microelectronic structures in accordance with other aspects of this invention, such as non-volatile memories, that include (1) a layerstack having a pattern including sidewalls, the layerstack comprising a resistivity-switchable layer disposed above and in contact with a bottom electrode, and a top electrode disposed above and in contact with the resistivity-switchable layer; and (2) a dielectric sidewall liner in contact with the sidewalls of the layerstack; wherein the resistivity-switchable layer includes a carbon-based material, and the dielectric sidewall liner includes an oxygen-poor dielectric material. Numerous additional aspects are provided.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: November 13, 2012
    Assignee: SanDisk 3D LLC
    Inventor: April D. Schricker
  • Patent number: 8309436
    Abstract: A method of producing an epitaxial substrate for a solid-state imaging device, comprising: forming a gettering sink by injecting laser beam to a semiconductor substrate through one surface thereof, condensing the laser beam to an arbitrarily selected portion of the semiconductor substrate, thereby causing multi-photon absorption process to occur in the portion, and forming a gettering sink having a modified crystal structure; and epitaxially growing at least two epitaxial layers on the semiconductor substrate in which the gettering sink is formed.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: November 13, 2012
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita
  • Patent number: 8207048
    Abstract: Method for producing nanostructures comprising: a step of providing a substrate (100) having a buried barrier layer (2) and above said barrier layer (2) a crystalline film (5) provided with a network of crystalline defects and/or stress fields (12) in a crystalline zone (13), one or several steps of attacking the substrate (100), of which a preferential attack either of the crystalline defects and/or the stress fields, or the crystalline zone (13) between the crystalline defects and/or the stress fields, said attack steps enabling the barrier layer (2) to be laid bared locally and protrusions (7) to be formed on a nanometric scale, separated from each other by hollows (7.1) having a base located in the barrier layer, the protrusions leading to nanostructures (7, 8).
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: June 26, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Franck Fournel, Hubert Moriceau, Chrystel Deguet
  • Patent number: 8168518
    Abstract: A gate insulating film (13) is formed on a substrate (1) so as to cover a gate electrode (11), and an amorphous silicon film (semiconductor thin film) (15) is further formed. A light absorption layer (19) is formed thereon through a buffer layer (17). Energy lines Lh are applied to the light absorption layer (19) from a continuous-wave laser such as a semiconductor laser. This oxidizes only a surface side of the light absorption layer Lh and produces a beautiful crystalline silicon film (15a) obtained by crystallizing the amorphous silicon film (15) using heat generated by thermal conversion of the energy lines Lh at the light absorption layer (19) and heat of the oxidation reaction. This provides a method for crystallizing a thin film with good controllability at low costs achieved with simpler process.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: May 1, 2012
    Assignee: Sony Corporation
    Inventors: Nobuhiko Umezu, Koichi Tsukihara, Goh Matsunobu, Yoshio Inagaki, Koichi Tatsuki, Shin Hotta, Katsuya Shirai
  • Publication number: 20120052656
    Abstract: Methods of fabricating dimensional silica-based substrates or structures comprising a porous silicon layers are contemplated. According to one embodiment, oxygen is extracted from the atomic elemental composition of a silica glass substrate by reacting a metallic gas with the substrate in a heated inert atmosphere to form a metal-oxygen complex along a surface of the substrate. The metal-oxygen complex is removed from the surface of the silica glass substrate to yield a crystalline porous silicon surface portion and one or more additional layers are formed over the crystalline porous silicon surface portion of the silica glass substrate to yield a dimensional silica-based substrate or structure comprising the porous silicon layer. Embodiments are also contemplated where the substrate is glass-based, but is not necessarily a silica-based glass substrate. Additional embodiments are disclosed and claimed.
    Type: Application
    Filed: May 4, 2011
    Publication date: March 1, 2012
    Inventors: Robert A. Bellman, Nicholas F. Borrelli, David A. Deneka, Shawn M. O'Malley, Vitor M. Schneider
  • Patent number: 8124502
    Abstract: A semiconductor device manufacturing method is provided, including: providing a semiconductor substrate, forming on the semiconductor substrate a layer including a semiconductor compound and a dope additive, and thereafter forming an emitter region and gettering impurities by annealing the semiconductor substrate including the layer.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: February 28, 2012
    Assignee: Applied Materials, Inc.
    Inventor: Rafel Ferre i Tomas
  • Patent number: 8120155
    Abstract: A MEMS device is packaged in a process which hydrogen (H) deuterium (D) for reduced stiction. H is exchanged with D by exposing the MEMS device with a deuterium source, such as deuterium gas or heavy water vapor, optionally with the assistance of a direct or downstream plasma.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: February 21, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Earl V. Atnip, Simon Joshua Jacobs
  • Patent number: 8048770
    Abstract: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: November 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo Eguchi, Yohei Monma, Atsuhiro Tani, Misako Hirosue, Kenichi Hashimoto, Yasuharu Hosaka
  • Patent number: 8043936
    Abstract: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: October 25, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo Eguchi, Yohei Monma, Atsuhiro Tani, Misako Hirosue, Kenichi Hashimoto, Yasuharu Hosaka
  • Publication number: 20110256691
    Abstract: A method and apparatus for removing excess dopant from a doped substrate is provided. In one embodiment, a substrate is doped by surfaced deposition of dopant followed by formation of a capping layer and thermal diffusion drive-in. A reactive etchant mixture is provided to the process chamber, with optional plasma, to etch away the capping layer and form volatile compounds by reacting with excess dopant. In another embodiment, a substrate is doped by energetic implantation of dopant. A reactive gas mixture is provided to the process chamber, with optional plasma, to remove excess dopant adsorbed on the surface and high-concentration dopant near the surface by reacting with the dopant to form volatile compounds. The reactive gas mixture may be provided during thermal treatment, or it may be provided before or after at temperatures different from the thermal treatment temperature. The volatile compounds are removed.
    Type: Application
    Filed: June 24, 2011
    Publication date: October 20, 2011
    Inventors: Kartik Ramaswamy, Kenneth S. Collins, Biagio Gallo, Hiroji Hanawa, Majeed A. Foad, Martin A. Hilkene, Kartik Santhanam, Matthew D. Scotney-Castle
  • Patent number: 7977216
    Abstract: Provided is a silicon wafer including: a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer; and a bulk area formed between the first denuded zone and a backside of the silicon wafer, wherein the first denuded zone is formed with a depth ranging from approximately 20 um to approximately 80 um from the top surface, and wherein a concentration of oxygen in the bulk area is uniformly distributed within a variation of 10% over the bulk area.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: July 12, 2011
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jung-Goo Park
  • Publication number: 20110127660
    Abstract: Embodiments of the invention provide an electronic device which may include an interior compartment housing at least one electronic component that may be reactive to target impurities. The electronic component may include at least a cathode and an anode. A purifier material may be interspersed within a conducting polymer layer between the cathode and the anode. The purifier material may decrease target impurities within the interior compartment of the electronic device from a first level to a second level.
    Type: Application
    Filed: February 9, 2011
    Publication date: June 2, 2011
    Applicant: Matheson Tri-Gas
    Inventors: Robert Torres, JR., Tadaharu Watanabe, Joseph V. Vininski
  • Patent number: 7939432
    Abstract: A method of improving the intrinsic gettering ability of a wafer is described. A first annealing step is performed to the wafer at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. A second annealing step is performed to the wafer, at a second temperature higher than the first temperature, in the atmosphere.
    Type: Grant
    Filed: December 15, 2008
    Date of Patent: May 10, 2011
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chun-Ling Chiang, Jung-Yu Hsieh, Ling-Wu Yang
  • Patent number: 7867923
    Abstract: A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a remote plasma system located outside the deposition chamber. Moreover, the method includes introducing the radical nitrogen precursor to the deposition chamber, wherein the radical nitrogen and silicon-containing precursors react and deposit the silicon and nitrogen containing film on the substrate. Furthermore, the method includes annealing the silicon and nitrogen containing film in a steam environment to form a silicon oxide film, wherein the steam environment includes water and acidic vapor.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: January 11, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Srinivas D. Nemani, Ellie Yieh
  • Patent number: 7776723
    Abstract: In an example embodiment of the method of manufacturing an epitaxial semiconductor substrate, a gettering layer is grown over a semiconductor substrate. An epitaxial layer may then be formed over the gettering layer, and a semiconductor device may be formed on the epitaxial layer.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: August 17, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Lee, DongSuk Shin, Tetsuji Ueno, Seung-Hwan Lee, Hwa-Sung Rhee
  • Publication number: 20100173477
    Abstract: A cause of deteriorating the hydrogen termination on the surface of a wafer is found to be water adsorbed on the surface. By exposing the wafer to an inert gas atmosphere containing an H2 gas so as to suppress the oxidation reaction due to the water, it is possible to improve the hydrogen termination on the wafer surface.
    Type: Application
    Filed: September 13, 2005
    Publication date: July 8, 2010
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Hiroshi Akahori
  • Patent number: 7745305
    Abstract: A method of removing a portion of an oxide layer includes forming first byproducts by reacting a reaction gas with the oxide layer, the reaction gas including fluorine and nitrogen, reacting the reaction gas with the first byproducts to form second byproducts, and removing the second byproducts.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: June 29, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Heon Lee, Kyu-Tae Na, Ju-Wan Kim, Taek-Jung Kim
  • Publication number: 20100151657
    Abstract: A method of improving the intrinsic gettering ability of a wafer is described. A first annealing step is performed to the wafer at a first temperature in an atmosphere containing at least one of oxygen gas and nitrogen gas. A second annealing step is performed to the wafer, at a second temperature higher than the first temperature, in the atmosphere.
    Type: Application
    Filed: December 15, 2008
    Publication date: June 17, 2010
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chun-Ling Chiang, Jung-Yu Hsieh, Ling-Wu Yang
  • Patent number: 7737005
    Abstract: A cleaning process is performed on the surface of a nickel silicide film serving as an underlayer. Then, a Ti film is formed to have a film thickness of not less than 2 nm but less than 10 nm by CVD using a Ti compound gas. Then, the Ti film is nitrided. Then, a TiN film is formed on the Ti film thus nitrided, by CVD using a Ti compound gas and a gas containing N and H.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: June 15, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Kunihiro Tada, Kensaku Narushima, Satoshi Wakabayashi
  • Patent number: 7670931
    Abstract: Methods for fabricating semiconductor structures with backside stress layers are provided. In one exemplary embodiment, the method comprises the steps of providing a semiconductor device formed on and within a front surface of a semiconductor substrate. The semiconductor device comprises a channel region. A plurality of dielectric layers is formed overlying the semiconductor device. The plurality of dielectric layers comprises conductive connections that are in electrical communication with the semiconductor device. A backside stress layer is formed on a back surface of the semiconductor substrate. The backside stress layer is configured to apply to the channel region of the semiconductor device a uniaxial compressive or tensile stress that, with stresses applied by the plurality of dielectric layers, results in an overall stress exerted on the channel region to achieve a predetermined overall strain of the channel region.
    Type: Grant
    Filed: May 15, 2007
    Date of Patent: March 2, 2010
    Assignee: Novellus Systems, Inc.
    Inventor: Roey Shaviv
  • Publication number: 20100035409
    Abstract: A method for improving the minority lifetime of silicon containing wafer having metallic contaminants therein is described incorporating annealing at 1200° C. or greater and providing a gaseous ambient of oxygen, an inert gas and a chlorine containing gas such as HCl.
    Type: Application
    Filed: August 5, 2008
    Publication date: February 11, 2010
    Inventors: Joel P De Souza, Harold John Hovel, Daniel A. Inns, Devendra K. Sadana, Ghavam G. Shahidi
  • Patent number: 7611971
    Abstract: A method of reducing the amount of halogenated materials in a halogen-containing environment. The method comprises introducing an aluminum compound into the halogen-containing environment, reacting the aluminum compound with the halogenated material to form a gaseous reaction product, and removing the gaseous reaction product from the environment. The aluminum compound may be a trialkylaluminum compound, an alane, an alkylaluminum hydride, an alkylaluminum halide, an alkylaluminum sesquihalide, or an aluminum sesquihalide. The aluminum compound may alternatively form a solid aluminum product, which is deposited on a surface associated with the halogen-containing environment or onto a semiconductor disposed therewithin. The halogenated material is incorporated into the solid aluminum product, forming an inert film within which the halogenated material is trapped.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: November 3, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Demetrius Sarigiannis, Cem Basceri, Christopher W. Hill, Garo J. Derderian
  • Patent number: 7611579
    Abstract: A system for synthesizing nanostructures using chemical vapor deposition (CVD) is provided. The system includes a housing, a porous substrate within the housing, and on a downstream surface of the substrate, a plurality of catalyst particles from which nanostructures can be synthesized upon interaction with a reaction gas moving through the porous substrate. Electrodes may be provided to generate an electric field to support the nanostructures during growth. A method for synthesizing extended length nanostructures is also provided. The nanostructures are useful as heat conductors, heat sinks, windings for electric motors, solenoid, transformers, for making fabric, protective armor, as well as other applications.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: November 3, 2009
    Assignee: Nanocomp Technologies, Inc.
    Inventors: David Lashmore, Joseph J. Brown, Robert C. Dean, Jr., Peter L. Antoinette
  • Patent number: 7582540
    Abstract: This method for manufacturing an SOI wafer includes: a step of forming insulating films in a front surface and a mirror-polished rear surface of an active layer wafer; a step of removing the insulating film in the front surface of the active layer wafer; a step of subjecting the active layer wafer to a rapid thermal annealing process; a step of bonding the active layer wafer and a support wafer with the insulating film formed in the rear surface therebetween so as to form a bonded wafer; a step of subjecting the bonded wafer to a heat treatment for bonding enhancement which enhances a bonding strength between the active layer wafer and the support wafer; and a step of thinning the active layer wafer in the bonded wafer so as to form an SOI layer.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: September 1, 2009
    Assignee: Sumco Corporation
    Inventors: Takaaki Shiota, Yasuhiro Oura
  • Publication number: 20090214798
    Abstract: Embodiments of the present invention provide apparatus and method for front side protection while processing side and backside of a substrate. One embodiment of the present invention provides a showerhead configured to provide a purge gas to a front side of a substrate during a backside etch processing. The showerhead comprises a body configured to be disposed over the front side of the substrate. The body has a process surface configured to face the front side of the substrate. The process surface has an outer circular region, a central region, a middle region between the outer central region and the central region. The first plurality of holes are distributed in the outer circular region and configured to direct the purge gas towards an edge area of the front side of the substrate. No gas delivery hole is distributed within a substantial portion of the middle region.
    Type: Application
    Filed: February 27, 2008
    Publication date: August 27, 2009
    Inventors: IMAD YOUSIF, Ying Rui, Nancy Fung, Martin Jeffrey Salinas, Ajit Balakrishna, Anchel Sheyner, Shahid Rauf, Walter R. Merry
  • Patent number: 7566631
    Abstract: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: July 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Kathryn Wilder Guarini, Erin C. Jones, Antonio F. Saavedra, Jr., Leathen Shi, Dinkar V. Singh
  • Publication number: 20090162996
    Abstract: A method and apparatus for removing excess dopant from a doped substrate is provided. In one embodiment, a substrate is doped by surfaced deposition of dopant followed by formation of a capping layer and thermal diffusion drive-in. A reactive etchant mixture is provided to the process chamber, with optional plasma, to etch away the capping layer and form volatile compounds by reacting with excess dopant. In another embodiment, a substrate is doped by energetic implantation of dopant. A reactive gas mixture is provided to the process chamber, with optional plasma, to remove excess dopant adsorbed on the surface and high-concentration dopant near the surface by reacting with the dopant to form volatile compounds. The reactive gas mixture may be provided during thermal treatment, or it may be provided before or after at temperatures different from the thermal treatment temperature. The volatile compounds are removed.
    Type: Application
    Filed: December 21, 2007
    Publication date: June 25, 2009
    Inventors: Kartik Ramaswamy, Kenneth S. Collins, Biagio Gallo, Hiroji Hanawa, Majeed A. Foad, Martin A. Hilkene, Kartik Santhanam, Matthew D. Scotney-Castle