Abstract: Embodiments of the present invention provide apparatus and method for front side protection while processing side and backside of a substrate. One embodiment of the present invention provides a showerhead configured to provide a purge gas to a front side of a substrate during a backside etch processing. The showerhead comprises a body configured to be disposed over the front side of the substrate. The body has a process surface configured to face the front side of the substrate. The process surface has an outer circular region, a central region, a middle region between the outer central region and the central region. The first plurality of holes are distributed in the outer circular region and configured to direct the purge gas towards an edge area of the front side of the substrate. No gas delivery hole is distributed within a substantial portion of the middle region.

Abstract: Described is a wet chemical surface treatment involving NH4OH that enables extremely strong direct bonding of two wafer such as semiconductors (e.g., Si) to insulators (e.g., SiO2) at low temperatures (less than or equal to 400° C.). Surface energies as high as ˜4835±675 mJ/m2 of the bonded interface have been achieved using some of these surface treatments. This value is comparable to the values reported for significantly higher processing temperatures (less than 1000° C.). Void free bonding interfaces with excellent yield and surface energies of ˜2500 mJ/m2 have also be achieved herein.

Abstract: A method and apparatus for removing excess dopant from a doped substrate is provided. In one embodiment, a substrate is doped by surfaced deposition of dopant followed by formation of a capping layer and thermal diffusion drive-in. A reactive etchant mixture is provided to the process chamber, with optional plasma, to etch away the capping layer and form volatile compounds by reacting with excess dopant. In another embodiment, a substrate is doped by energetic implantation of dopant. A reactive gas mixture is provided to the process chamber, with optional plasma, to remove excess dopant adsorbed on the surface and high-concentration dopant near the surface by reacting with the dopant to form volatile compounds. The reactive gas mixture may be provided during thermal treatment, or it may be provided before or after at temperatures different from the thermal treatment temperature. The volatile compounds are removed.

Abstract: An epitaxial wafer comprises a silicon substrate, a gettering epitaxial film formed thereon and containing silicon and carbon, and a main silicon epitaxial film formed on the gettering epitaxial film, in which the gettering epitaxial film has a given carbon atom concentration and carbon atoms are existent between its silicon lattices.

Abstract: A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a remote plasma system located outside the deposition chamber. Moreover, the method includes introducing the radical nitrogen precursor to the deposition chamber, wherein the radical nitrogen and silicon-containing precursors react and deposit the silicon and nitrogen containing film on the substrate. Furthermore, the method includes annealing the silicon and nitrogen containing film in a steam environment to form a silicon oxide film, wherein the steam environment includes water and acidic vapor.

Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.

Abstract: Method for producing a metal silicon (oxy)nitride by introducing a carbon-free silicon source (for example, (SiH3)3N), a metal precursor with the general formula MXn (for example, Hf(NEt2)4), and an oxidizing agent (for example, O2) into a CVD chamber and reacting same at the surface of a substrate. MsiN, MSIo and/or MSiON films may be obtained. These films are useful are useful as high k dielectrics films.

Abstract: There is provided a method of fabricating a wafer, comprising depositing semiconductor material into a recess in a setter, moving the setter through a heating/cooling region to subject the semiconductor material to a temperature profile, and removing a wafer from the recess. The size and shape of the wafer are substantially equal to the size of the wafer when it is used. As a result, the wafer can be fabricated in any desired shape and with any of a variety of surface structural features and/or internal structural features. The temperature profile can be closely controlled, enabling production of wafers having structural features not previously obtainable. There are also provided wafers formed by such methods and setters for use in such methods.

Abstract: Apparatus and methods that minimize surface defect development in silicon wafers during thermal processing at relatively high temperatures at which silicon wafers are annealed and at less extreme temperature, or for other purposes. The apparatus and methods have utility to horizontally-disposed furnaces for silicon wafers and to vertically-oriented furnaces in which larger wafers can be thermally processed. A selectively-sealable process tube encloses silicon wafers during heating of the silicon wafers to a predetermined temperature, and a heating atmosphere supply system induces through the process tube a positive flow of a process gas, such as hydrogen or argon, that is non-reactive with solid silicon at the predetermined temperature. A process tube outlet vents gas from the process tube, and an impurity sensor in the process tube outlet detects oxygen and moisture in the vented gas to verify the purity of the atmosphere surrounding the wafers during thermal processing.

Abstract: A substrate processing apparatus has a processing space provided with a holding stand for holding a substrate to be processed. A hydrogen catalyzing member is arranged in the processing space to face the substrate and for decomposing hydrogen molecules into hydrogen radicals H*. A gas feeding port is arranged in the processing space on an opposite side of the hydrogen catalyzing member to the substrate for feeding a processing gas including at least hydrogen gas. An interval between the hydrogen catalyzing member and the substrate on the holding stand is set less than the distance that the hydrogen radicals H* can reach.

Abstract: In one embodiment, a method of forming a semiconductor device with trench charge compensation structures includes exposing the trench sidewalls to a reduced temperature hydrogen desorption process to enhance the formation of monocrystalline semiconductor layers.

Abstract: In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer.

Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.

Abstract: Nitrogen doped titanium oxide coatings on a hot glass substrate are prepared by providing a uniform vaporized reactant mixture containing a titanium compound, a nitrogen compound and an oxygen-containing compound, and delivering the reactant mixture to the surface of a ribbon of hot glass, where the compounds react to form a nitrogen doped titanium oxide coating. The nitrogen doped titanium oxide coatings deposited in accordance with the invention demonstrate an increase in visible light absorption.

Abstract: A method by which a silicon wafer is prevented from increasing boron concentration near the surface and difference in the boron concentration does not arise between the surface of the annealed wafer and the silicon bulk to eliminate boron contamination in the silicon wafer caused by an annealing treatment is provided. The method includes, when annealing a silicon wafer having a surface on which a native oxide film has formed and boron of environmental origin or from chemical treatment prior to annealing has deposited, steps of carrying out temperature heat-up in a mixed gas atmosphere having a mixing ratio of hydrogen gas to inert gas of 5% to 100% so as to remove the boron-containing native oxide film, followed by annealing in an inert gas atmosphere.

Abstract: A method for making a semiconductor device is described. That method includes forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.

Abstract: A glass bottle containing a sample of an organic material to be purified is located at a position surrounded by a heater near one end in an outer glass tube. An inner glass tube for catching organic crystals obtained by recrystallization is located at a position near the other end in the outer glass tube. When the sample of the organic material is sublimed and purified, the inside of the outer glass tube is kept in a higher vacuum state (lower pressure) than 200 Pa by a vacuum pump. The sample inside the outer glass tube is heated by the heater, to sublime organic molecules of the sample contained in the glass bottle. The outer glass tube is provided with a temperature gradient, so that organic molecule vapor is cooled near the other end in the outer glass tube, and is recrystallized inside the inner glass tube.

Abstract: A semiconductor substrate having a front surface and a backside is prepared. A first silicon oxide layer is formed on the front surface of the semiconductor substrate and, simultaneously, forming a second silicon oxide layer on the backside of the semiconductor substrate. A first silicon nitride layer is formed on the front surface of the semiconductor substrate and, simultaneously, forming a second silicon nitride layer on the backside of the semiconductor substrate. Lithographic and etching process is performed, using the first silicon nitride layer as an etching hard mask, to etch a trench into the front surface of the semiconductor substrate. The trench is then filled with insulating material. Using the insulating material as an etching hard mask, the second silicon nitride layer on the backside of the semiconductor substrate is etched away. A densification process is then performed to densify the insulating material.

Abstract: Methods of de-fluorinating a wafer surface after damascene processing and prior to photoresist removal are disclosed, as is a related structure. In one embodiment, the method places the wafer surface in a chamber and exposes the wafer surface to a plasma from a source gas including at least one of nitrogen (N2) and/or hydrogen (H2) at a low power density or ion density. The exposing step removes the chemisorbed and physisorbed fluorine residue present on the wafer surface (and chamber), and improves ultra low dielectric (ULK) interconnect structure robustness and integrity. The exposing step is operative due to the efficacy of hydrogen and nitrogen radicals at removing fluorine-based species and also due to the presence of a minimal amount of ion energy in the plasma. The low power density nitrogen and/or hydrogen-containing plasma process enables negligible ash/adhesion promoter interaction and reduces integration complexity during dual damascene processing of low-k OSG-based materials.

Abstract: The active region of a long-wavelength light emitting device is made by providing an organometallic vapor phase epitaxy (OMVPE) reactor, placing a substrate wafer capable of supporting growth of indium gallium arsenide nitride in the reactor, supplying a Group III–V precursor mixture comprising an arsenic precursor, a nitrogen precursor, a gallium precursor, an indium precursor and a carrier gas to the reactor and pressurizing the reactor to a sub-atmospheric elevated growth pressure no higher than that at which a layer of indium gallium arsenide layer having a nitrogen fraction commensurate with light emission at a wavelength longer than 1.2 ?m is deposited over the substrate wafer.

Abstract: A method of fabrication of a semiconductor integrated circuit device, calls for disposing, in an ultrapure water preparing system, UF equipment having therein a UF module which has been manufactured by disposing, in a body thereof, a plurality of capillary hollow fiber membranes composed of a polysulfone membrane or polyimide membrane, bonding the plurality of hollow fiber membranes at end portions thereof by hot welding, and by this hot welding, simultaneously adhering the hollow fiber membranes to the body. Upon preparation of ultrapure water to be used for the fabrication of the semiconductor integrated circuit device, it is possible to prevent run-off of ionized amine into the ultrapure water.

Abstract: A material layer containing impurities that react with water molecules is formed on a substrate. The material layer is then heated under a pressure exceeding one atmosphere and in the presence of water vapor to generate pores in the material layer. The material layer may form the interlayer insulating layer of a semiconductor device.

Abstract: A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.

Abstract: Disclosed herein is a method of improving the adhesion of a hydrophobic self-assembled monolayer (SAM) coating to a surface of a MEMS structure, for the purpose of preventing stiction. The method comprises pretreating surfaces of the MEMS structure with a plasma generated from a source gas comprising oxygen and, optionally, hydrogen. The treatment oxidizes the surfaces, which are then reacted with hydrogen to form bonded OH groups on the surfaces. The hydrogen source may be present as part of the plasma source gas, so that the bonded OH groups are created during treatment of the surfaces with the plasma. Also disclosed herein is an integrated method for release and passivation of MEMS structures.

Abstract: A process for heat-treating a single crystal silicon segment to influence the profile of minority carrier recombination centers in the segment. The segment has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the segment is subjected to a heat-treatment to form crystal lattice vacancies, the vacancies being formed in the bulk of the silicon. The segment is then cooled from the temperature of said heat treatment at a rate which allows some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a segment having a vacancy concentration profile in which the peak density is at or near the central plane with the concentration generally decreasing in the direction of the front surface of the segment. Platinum atoms are then in-diffused into the silicon matrix such that the resulting platinum concentration profile is substantially related to the concentration profile of the crystal lattice vacancies.

Abstract: The present invention relates to a method of manufacturing a semiconductor device having an excellent gettering effect. In this method, when phosphorus is added to a poly-Si film, which has been crystallized by the addition of a metal, to subject the resultant poly-Si film to the heat treatment to carry out gettering therefor, the device is performed for the shape of the island-like insulating film on the poly-Si film which is employed when implanting phosphorus. Thereby, the area of the boundary surface between the region to which phosphorus has been added and the region to which no phosphorus has been added is increased to enhance gettering efficiency.

Abstract: In a conventional evaluation method of IG effectivity on Cu in semiconductor silicon substrates, it is required to actually conduct the device process, or a great deal of time, manpower and expenses for manufacturing a MOS device for dielectric breakdown estimation and the like are needed, but in the present invention, the problem was solved by experimentally finding in advance the optimum ranges of the diagonal length and density of oxygen precipitates which make the IG effectivity on Cu favorable, and conducting a heat treatment for the addition of IG effectivity based on a simulation by calculations using Fokker-Planck equations so that the diagonal length and density of plate-like precipitates fall within the optimum ranges.

Abstract: A method for making high quality InGaAsN semiconductor devices is presented. The method allows the making of high quality InGaAsN semiconductor devices using a single MOCVD reactor while avoiding aluminum contamination.

Abstract: White defects caused by a dark-current of a solid-state imaging device is reduced by effectively bringing out gettering capability of a buried getter sink layer. A buried getter sink layer is formed by introducing to the semiconductor substrate a substance of a second element which is a congener of a first element composing a semiconductor substrate, a crystal growth layer is formed by crystal growing a substance of the first element on a surface of the semiconductor substrate, and a solid-state imaging element is formed inside and on the crystal growth layer at a lower temperature than that in the case of forming an extrinsic getter sink layer by introducing a substance of a third element of a different group from the first element on a back surface of the semiconductor substrate.

Abstract: The present invention relates to a method of manufacturing a silicon-on-insulator substrate, comprising the steps of (1) providing a silicon-on-insulator semiconductor wafer having at least one surface of a silicon film; (2) implanting an inert atom into the at least one surface to form a damaged surface layer including a gettering site on the silicon film and to leave an undamaged region of the silicon film; (3) subjecting the wafer to conditions to getter at least one impurity from the silicon film into the gettering site; and (4) removing the damaged surface layer.

Abstract: A method for preventing oxide layer peeling in a high temperature annealing process including providing a plurality of spaced apart stacked semiconductor wafers for carrying out a high temperature annealing process including ambient nitrogen gas the plurality of spaced apart stacked semiconductor wafers stacked such that a process surface including an oxide layer of at least one semiconductor wafer is adjacent to a backside surface of another semiconductor wafer said backside surface having a layer of silicon nitride formed thereon prior to carrying out the high temperature annealing process; and, carrying out the high temperature annealing process.

Abstract: A method for making high quality InGaAsN semiconductor devices is presented. The method allows the making of high quality InGaAsN semiconductor devices using a single MOCVD reactor while avoiding aluminum contamination.

Abstract: A method of using dichloroethene and ammonia to provide chlorine and nitrogen during the growth of an in-situ hardened gate dielectric. The method provides a gaseous source of gettering agent and a gaseous source of dielectric strengthening agent that are compatible with each other and can be used during the formation of in-situ hardened dielectric or the strengthening of an already formed dielectric.

Abstract: A method and apparatus are provided for eliminating contaminants including metallic and/or hydrocarbon-containing contaminants on a surface of a semiconductor substrate by heating a semiconductor substrate which may have contaminates on the surface thereof to an elevated temperature within an integrated closed system while simultaneously purging the integrated closed system with a chlorine-containing gas. At the elevated temperatures the chlorine dissociates from the chlorine-containing gas and reacts with the contaminates on the substrate surface to form volatile chloride byproducts with such contaminants which are removed from the integrated closed system while the substrate is continuously heated and purged with the chlorine-containing gas. Subsequently, the substrate is moved to a cooling chamber within the integrated closed system and cooled to provide a semiconductor substrate having a clean surface.

Abstract: A process for heat-treating a single crystal silicon wafer to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The wafer has a front surface, a back surface, and a central plane between the front and back surfaces. In the process, the wafer is subjected to a heat-treatment to form crystal lattice vacancies in the wafer. During the heat-treatment, the front and back surfaces of the wafer are each exposed to either a nitriding gas or a non-nitriding gas. The front surface of the heat-treated wafer is then oxidized by heating in the presence of an oxygen-containing atmosphere in order to further effect the vacancy concentration profile within the wafer.

Abstract: The invention includes methods of forming microstructure devices. In an exemplary method, a substrate is provided which includes a first material and a second material. At least one of the first and second materials is exposed to vapor-phase alkylsilane-containing molecules to form a coating over the at least one of the first and second materials.

Abstract: A process is disclosed for removing a photoresist mask used to form openings in an underlying layer of low k carbon-doped silicon oxide dielectric material of an integrated circuit structure formed on a semiconductor substrate, which comprises exposing the photoresist mask in a plasma reactor to a plasma formed using a reducing gas until the photoresist mask is removed. In a preferred embodiment the reducing gas is selected from the group consisting of NH3, H2, forming gas, and a mixture of NH3 and H2.

Abstract: A process for forming a non-porous dielectric diffusion barrier layer on etched via and trench sidewall surfaces in a layer of porous low k dielectric material comprises exposing such etched surfaces to a plasma formed from one or more gases such as, for example, O2; H2; Ar; He; SiH4; NH3; N2; CHxFy, where x=1-3 and y=4-y; H2O; and mixtures of same, for a period of time sufficient to form from about 1 nanometer (nm) to about 20 nm of the non-porous dielectric diffusion barrier layer which prevents adsorption of moisture and other process gases into the layer of porous low k dielectric material, and prevents degassing from the porous low k dielectric material during subsequent processing.

Abstract: The present invention increases the safety of a reactor for generating water vapor from oxygen and hydrogen, provides ultra-pure water vapor in an amount necessary for practical use safely, stably and continuously, provides ultra-pure water vapor concentrations to nearly 100 percent without the need of an inert transporting gas, and provides a catalyst with long term, high catalytic activity within the reactor. Specifically, the system comprises a catalyst vessel and a plurality of sorption vessels. The catalyst vessel is made of a heat-resistant material and includes an inlet and an outlet for water vapor and inert gas mixture, a heat source, and has a platinum or palladium catalyst within the catalyst vessel. The sorption vessels are made of a heat-resistant material and includes an inlet and an outlet for water vapor and inert gas mixture, a heat source, and has a molecular sieve water vapor sorption material within the sorption vessel.

Abstract: Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step, that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.

Abstract: A method of using dichloroethene and ammonia to provide chlorine and nitrogen during the growth of an in-situ hardened gate dielectric. The method provides a gaseous source of gettering agent and a gaseous source of dielectric strengthening agent that are compatible with each other and can be used during the formation of in-situ hardened dielectric or the strengthening of an already formed dielectric.

Abstract: A method of improving the post-etch corrosion resistance of aluminum-containing wafers by performing a two-step post-etch passivation sequence which does not involve a plasma. In the first step the pressure is high, relative to typical passivation procedures, and the wafer temperature is relatively low. In the second step, the pressure is ramped down and the wafer temperature is ramped up. This two-step approach results in a more-efficient removal of chlorine from the wafer, and hence improved corrosion resistance.

Abstract: An electronic device that is sealed under vacuum includes a substrate, a transistor formed on the substrate, and a dielectric layer covering at least a portion of the transistor. The electronic device further includes a layer of non-evaporable getter material disposed on a portion of the dielectric layer; and a vacuum device disposed on a portion of the substrate. Electrical power pulses activate the non-evaporable getter material.

Abstract: The peeling of a thin-film single-crystal from a substrate is carried out so that the directions of straight lines on the single-crystal surface made by planes on which the single-crystal is apt to cleave are different from the front line direction of the peeled single-crystal. This single-crystal is used in a solar cell and a drive circuit member of an image display element. A method is provided which prevents a decrease in quality and yield of a single crystal layer when it is peeled from a substrate. A flexible solar cell module having a thin film single-crystal layer is made so that its flexing direction is different from the single-crystal's cleaving direction. Thus, a thin-film single-crystal solar cell module having excellent durability and reliability due to a lack of defect or cracking during production and use, and a method for producing the same, is provided.

Abstract: A surface of a substrate is oxidized at a temperature equal to or higher than 1050° C., or at a oxidation speed equal to or higher than 7.5 nm/min to form an oxide film with a thickness equal to or more than 1500 nm. when the oxide film is removed, a density of pits existent at the surface of a substrate is equal to or less than that prior to the oxidation treatment and a depth of a pit existent there is equal to or less than 50 nm. An element isolation withstand voltage can be prevented from lowering and a fabrication yield of a miniaturized, highly integrated semiconductor device can be improved.

Abstract: A combined preanneal/oxidation step using a rapid thermal process (RTP) for treatment of a silicon wafer to form a thermal oxide of a given thickness while simultaneously adjusting the denuded zone depth and bulk micro defect density (BMD) comprising: exposing the wafer to a controlled temperature and a controlled preannealing time in an oxidation ambient at ambient pressure to obtain a target thermal oxide thickness that is preselected to correspond to a preselected denuded zone depth.

Abstract: A preprocessing method of a metal film formation process before formation of a BLM film on a resist film of a substrate to be processed, wherein the resist film of substrate to be processed is irradiated with plasma, utilizing a plasma processing apparatus providing independent plasma generating power source and substrate bias power source to form an overhand area at the end face of a connecting hole and change the property of the surface area.

Abstract: The invention includes semiconductor processing methods, including trench isolation. In one implementation, an oxide layer is deposited over a substrate. The deposited oxide layer is exposed to a chlorine containing gas effective to getter metals outwardly therefrom. In one implementation, a dielectric layer, for example silicon dioxide, is plasma enhanced chemical vapor deposited over a substrate within a chamber comprising an internal metal surface under conditions effective to incorporate metal from the chamber surface within the dielectric layer. The dielectric layer is then exposed to a chlorine containing gas effective to getter at least some of said metal outwardly therefrom. In one implementation, a trench isolation method comprises forming a series of isolation trenches into a semiconductive substrate Silicon dioxide is chemical vapor deposited to within the trenches, with the silicon dioxide comprising metal impurity therein.

Abstract: Disclosed is an improved CMOS fabrication method that allows an implanted well in a bare silicon wafer to be simultaneously, driven annealed and denuded in a single process step. More specifically, a single step drive-anneal-denude (DAD) process is accomplished using a non-inert ambient environment. The DAD process is accomplished in a combination argon/hydrogen ambient environment. This process causes the silicon wafer to roughen slightly and is followed by an oxidation step, that optionally takes place in a combination argon/oxygen ambient environment to smooth out the silicon surface. The oxidation step may also optionally act as a pad-oxide or screening oxide for subsequent fabrication.

Abstract: In order to separate first and second base substrate without cracking them, and use a damaged base substrate again as a semiconductor substrate to enhance a yield, there is disclosed a preparation method of a semiconductor substrate comprising the steps of separating a composite member formed by bonding the first and second base substrates to each other via an insulating layer into a plurality of members at a separation area formed in a position different from a bonded face to transfer a part of one base substrate onto the other base. A mechanical strength of the separation area is non-uniform along the bonded face in the composite member.