Utilizing Epitaxial Lateral Overgrowth Patents (Class 438/481)
  • Patent number: 9741824
    Abstract: The present disclosure provides a method for forming a semiconductor device. The method includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and forming trenches in the semiconductor substrate on both sides of the gate structure. The method also includes forming a stress layer on inner sidewalls of each trench to fill up the trench; forming an interlayer on the stress layer, and forming a capping layer on the interlayer, wherein a top surface of the capping layer is higher than a top surface of the semiconductor substrate, and a lattice mismatch between the interlayer and the capping layer is lower than a lattice mismatch between the capping layer and the stress layer.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: August 22, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Huojin Tu
  • Patent number: 9673046
    Abstract: The invention provides a nonpolar or semipolar GaN substrate, in which a nitride semiconductor crystal having a low stacking fault density can be epitaxially grown on the main surface of the substrate, and a method for manufacturing an M-plane GaN substrate by forming a mask pattern having a line-shaped opening parallel to an a-axis of a C-plane GaN substrate on an N-polar plane of the C-plane GaN substrate, growing a plane-shape GaN crystal of which thickness direction is an m-axis direction from the opening of the mask pattern by an ammonothermal method, and cutting out the M-plane GaN substrate from the plane-shape GaN crystal.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: June 6, 2017
    Assignee: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Yusuke Tsukada, Shuichi Kubo, Kazunori Kamada, Hideo Fujisawa, Tatsuhiro Ohata, Hirotaka Ikeda, Hajime Matsumoto, Yutaka Mikawa
  • Patent number: 9620504
    Abstract: A semiconductor device includes merged contact plugs. A multi-fin active having N sub-fins is formed in a substrate. A contact plug is formed on the impurity areas. N is an integer between about eight (8) and about one thousand (1000). The N sub-fins include a first sub-fin formed in the outermost portion of the multi-fin active and a second sub-fin formed near the first sub-fin. A straight line perpendicular to a surface of the substrate and passes through a virtual bottom edge of the contact plug is disposed between the first sub-fin and the second sub-fin, or through the second sub-fin. The virtual bottom edge of the contact plug is defined at a cross point of a correlation line extending on a side surface of the contact plug and a horizontal line in contact with a lowermost end of the contact plug and parallel to the surface of the substrate.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: April 11, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyerim Moon, Myounghun Choi
  • Patent number: 9419074
    Abstract: As disclosed herein, a semiconductor device with aspect ratio trapping including, a bulk substrate, a plurality of isolation pillars formed on the bulk substrate, wherein one or more gaps are formed between the isolation pillars, an oxide layer formed by epitaxy on the bulk substrate, between the isolation pillars, wherein the oxide layer partially fills the gaps between the isolation pillars, one or more fins formed over the oxide layer between the isolation pillars, such that the one or more fins fill the gaps between the isolation pillars, wherein the oxide layer electrically isolates the one or more fins from the bulk substrate. The size of the gaps between the isolation pillars is selected to statistically eliminate defects caused by a lattice mismatch between the bulk substrate and the oxide layer. The semiconductor device may also contain an aspect-ratio trapping layer between the bulk substrate and oxide layer.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: August 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9419126
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 16, 2016
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Xiaodong Yang, Jin Ping Liu, Yanxiang Liu, Xusheng Wu
  • Patent number: 9396936
    Abstract: A method for growing aluminum indium nitride (AlInN) films on silicon substrates comprises several steps: firstly, arranging a silicon substrate in a reaction chamber; secondly, providing multiple reaction gases in the reaction chamber, wherein the reaction gases include aluminum precursors, indium precursors and nitrogen-containing gases; finally, dynamically adjusting flow rates of the reaction gases and directly growing an AlInN layer on the silicon substrate via a crystal growth process. By directly forming an AlInN layer on the silicon substrate, lattice matching is increased, residual thermal stress is reduced and film quality is improved. In addition, fabrication process is simplified and thus cost is reduced.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: July 19, 2016
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Li Chang, Jr-Yu Chen, Wei-Chun Chen, Pei-Yin Lin
  • Patent number: 9368582
    Abstract: An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The electronic device also includes a first epitaxial layer coupled to the III-V substrate and a second epitaxial layer coupled to the first epitaxial layer. The electronic device further includes a first contact in electrical contact with the substrate and a second contact in electrical contact with the second epitaxial layer.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: June 14, 2016
    Assignee: Avogy, Inc.
    Inventors: Isik C. Kizilyalli, David P. Bour, Thomas R. Prunty, Gangfeng Ye
  • Patent number: 9349594
    Abstract: As disclosed herein, a semiconductor device with aspect ratio trapping is provided, including a bulk substrate, a plurality of isolation pillars formed on the bulk substrate, wherein one or more gaps are formed between the isolation pillars, an oxide layer formed by epitaxy on the bulk substrate, between the isolation pillars, wherein the oxide layer partially fills the gaps between the isolation pillars, one or more fins formed over the oxide layer between the isolation pillars, such that the one or more fins fill the gaps between the isolation pillars, wherein the oxide layer electrically isolates the one or more fins from the bulk substrate. The oxide layer has an aspect ratio that is selected to substantially eliminate defects at the interface between the oxide layer and the fins. The semiconductor device may also include a semiconductor layer between the bulk substrate and oxide layer.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: May 24, 2016
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9293648
    Abstract: A light emitting device includes an n-type layer, a p-type layer structure, a layer of p-type nano-dots imbedded in the p-type layer structure, and an active region sandwiched between the n-type layer and the p-type layer structure, where the p-type nano-dots possess a sheet density of 1010 to 1012 cm?2, a lateral dimension of 2-20 nm, and a vertical dimension of 1-5 nm. The p-type layer structure with a layer of p-type nano-dots imbedded therein provides good vertical conductivity and UV transparency. Also provided is a method for making the light emitting device.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: March 22, 2016
    Assignee: BOLB INC.
    Inventors: Jianping Zhang, Hongmei Wang
  • Patent number: 9202762
    Abstract: A method for making an integrated circuit includes at least a tri-gate FinFET and a dual-gate FinFET. The method includes providing a semiconductor on insulator (SOI) substrate. The method also includes implanting impurities into the substrate for adjusting a threshold voltage. The method provides a nitride film overlying a surface region of the substrate and selectively etches the silicon nitride film to form a nitride cap region. The method etches the silicon layer to form a first and a second silicon fin regions. The nitride cap region is maintained on a portion of a surface region of the first silicon fin region. The method includes forming a gate dielectric, depositing a polysilicon film, and planarizing the polysilicon film by chemical mechanical polishing (CMP) using the nitride cap region as a polish stop. The method etches the polysilicon film to form gate electrodes. The method forms elevated source and drain regions.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: December 1, 2015
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: DeYuan Xiao
  • Patent number: 9177805
    Abstract: Integrated circuits having metal-insulator-semiconductor (MIS) contact structures and methods for fabricating integrated circuits having metal-insulator-semiconductor (MIS) contact structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure formed from semiconductor material overlying a semiconductor substrate. The method includes depositing a layer of high-k dielectric material over the fin structure. Further, the method includes forming a metal layer or layers over the layer of high-k dielectric material to provide the fin structure with a metal-insulator-semiconductor (MIS) contact structure.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: November 3, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Guillaume Bouche, Shao Ming Koh, Jeremy A. Wahl, Andy C. Wei
  • Patent number: 9153582
    Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, You-Ru Lin, Cheng-Tien Wan, Cheng-Hsien Wu, Chih-Hsin Ko
  • Patent number: 9048091
    Abstract: A method of manufacturing an III-N substrate includes bonding a Si substrate to a support substrate, the Si substrate having a (111) growth surface facing away from the support substrate, thinning the Si substrate at the (111) growth surface to a thickness of 100 ?m or less, and forming III-N material on the (111) growth surface of the Si substrate after the Si substrate is thinned. The support substrate has a coefficient of thermal expansion more closely matched to that of the III-N material than the Si substrate. Other methods of manufacturing an III-N substrate are disclosed, as well as the corresponding wafer structures.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: June 2, 2015
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Vielemeyer
  • Patent number: 9040331
    Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 9034738
    Abstract: A method for manufacturing a light-emitting diode, which includes the steps of: providing a substrate having a plurality of protruded portions on one main surface thereof wherein the protruded portion is made of a material different in type from that of the substrate and growing a first nitride-based III-V Group compound semiconductor layer on each recess portion of the substrate through a state of making a triangle in section wherein a bottom surface of the recess portion becomes a base of the triangle; laterally growing a second nitride-based III-V Group compound semiconductor layer on the substrate from the first nitride-based III-V Group compound semiconductor layer; and successively growing, on the second nitride-based III-V Group compound semiconductor layer, a third nitride-based III-V Group compound semiconductor layer of a first conduction type, an active layer, and a fourth nitride-based III-V compound semiconductor layer of a second conduction type.
    Type: Grant
    Filed: September 21, 2006
    Date of Patent: May 19, 2015
    Assignee: SONY CORPORATION
    Inventors: Akira Ohmae, Michinori Shiomi, Noriyuki Futagawa, Takaaki Ami, Takao Miyajima, Yuuji Hiramatsu, Izuho Hatada, Nobukata Okano, Shigetaka Tomiya, Katsunori Yanashima, Tomonori Hino, Hironobu Narui
  • Patent number: 9034717
    Abstract: Methods for forming a layer of semiconductor material and a semiconductor-on-insulator structure are provided. A substrate including one or more devices or features formed therein is provided. A seed layer is bonded to the substrate, where the seed layer includes a crystalline semiconductor structure. A first portion of the seed layer that is adjacent to an interface between the seed layer and the substrate is amorphized. A second portion of the seed layer that is not adjacent to the interface is not amorphized and maintains the crystalline semiconductor structure. Dopant implantation is performed to form an N-type conductivity region or a P-type conductivity region in the first portion of the seed layer. A solid-phase epitaxial growth process is performed to crystallize the first portion of the seed layer. The SPE growth process uses the crystalline semiconductor structure of the second portion of the seed layer as a crystal template.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Jean-Pierre Colinge
  • Patent number: 9006083
    Abstract: Methods and structures for GaN on silicon-containing substrates are disclosed, comprising a texturing process to generate a rough surface containing (111) surface, which then can act as an underlayer for epitaxial GaN. LED devices are then fabricated on the GaN layer. Variations of the present invention include different orientations of silicon layer instead of (100), such as (110) or others; and other semiconductor materials instead of GaN, such as other semiconductor materials suitable for LED devices.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 14, 2015
    Inventor: Ananda H. Kumar
  • Patent number: 9006057
    Abstract: A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form ?-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the ?-shaped source/drain grooves.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: April 14, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Changliang Qin, Peizhen Hong, Huaxiang Yin
  • Patent number: 8993420
    Abstract: A method of forming an epitaxial layer includes forming a plurality of first insulation patterns in a substrate, the plurality of first insulation patterns spaced apart from each other, forming first epitaxial patterns on the plurality of first insulation patterns, forming second insulation patterns between the plurality of first insulation patterns to contact the plurality of first insulation patterns, and forming second epitaxial patterns on the second insulation patterns and between the first epitaxial patterns to contact the first epitaxial patterns, the first epitaxial patterns and the second epitaxial patterns forming a single epitaxial layer.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: March 31, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joong-han Shin, Bong-jin Kuh, Ki-chul Kim, Jeong-meung Kim, Eun-ha Lee, Jong-sung Lim, Han-mei Choi
  • Patent number: 8993418
    Abstract: The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: March 31, 2015
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics, Inc.
    Inventors: Vincent Destefanis, Nicolas Loubet
  • Publication number: 20150079771
    Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes several operations as follows. A semiconductor substrate is received. A trench along a depth in the semiconductor substrate is formed. The semiconductor substrate is exposed in a hydrogen containing atmosphere. Dopants are inserted into a portion of the semiconductor substrate. A dielectric is filled in the trench. The dopants are driven into a predetermined distance in the semiconductor substrate.
    Type: Application
    Filed: July 24, 2014
    Publication date: March 19, 2015
    Inventors: Tai-I YANG, Jheng-Sheng YOU, Chi-Fu LIN, Tien-Lu LIN
  • Patent number: 8980729
    Abstract: An SOI substrate and a method for forming the SOI substrate are provided. An SOI substrate can be formed by forming a silicon-germanium layer on a first baseplate. A top silicon layer can be formed on the silicon-germanium layer. A first insulating layer can be formed on the top silicon layer. An ion implanted layer can be formed in one of the silicon-germanium layer and the first baseplate. A second baseplate can be bonded to the first insulating layer. A first annealing process can be performed to anneal and split the one of the silicon-germanium layer and the first baseplate at the ion implanted layer. The silicon-germanium layer can be removed from the top silicon layer to expose the top silicon layer and to form the SOI substrate comprising the first insulating layer formed between the top silicon layer and the second baseplate.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Manufacturing International Corp.
    Inventor: Aries Chen
  • Publication number: 20150064884
    Abstract: A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 5, 2015
    Applicant: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Hong He, Ali Khakifirooz
  • Patent number: 8969181
    Abstract: Oxygen, silicon, germanium, carbon, or nitrogen is selectively implanted into a workpiece. The workpiece is annealed to incorporate the ions into the workpiece. A compound semiconductor is then formed on the workpiece. For example, gallium nitride may be formed on a silicon, silicon carbide, or sapphire workpiece. The width of the implanted regions can be configured to compensate for any shrinkage during annealing.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: March 3, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Morgan D. Evans, Christopher R. Hatem
  • Publication number: 20150056792
    Abstract: An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 26, 2015
    Applicant: Intemational Business Machines Corporation
    Inventors: Thomas N. Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8956960
    Abstract: According to an embodiment, a method for stress-reduced forming a semiconductor device includes: providing a semiconductor wafer including an upper side and a first semiconductor layer of a first semiconductor material at the upper side; forming, in a vertical cross-section which is substantially orthogonal to the upper side, at the upper side a plurality of first vertical trenches and a plurality of second vertical trenches between adjacent first vertical trenches so that the first vertical trenches have, in the vertical cross-section, a larger horizontal extension than the second vertical trenches; and forming a plurality of third semiconductor layers at the upper side which are, in the vertical cross-section, spaced apart from each other by gaps each of which overlaps, in the vertical cross-section, with a respective first vertical trench when seen from above. At least one of the third semiconductor layers includes a semiconductor material which is different to the first semiconductor material.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: February 17, 2015
    Assignee: Infineon Technologies AG
    Inventors: Peter Irsigler, Hans-Joachim Schulze
  • Patent number: 8952478
    Abstract: A radiation conversion device such as a photovoltaic cell, a photodiode or a semiconductor radiation detection device, includes a semiconductor portion with first compensation zones of a first conductivity type and a base portion that separates the first compensation zones from each other. The first compensations zones are arranged in pillar structures. Each pillar structure includes spatially separated first compensation zones and extends in a vertical direction with respect to a main surface of the semiconductor portion. Between neighboring ones of the pillar structures the base portion includes second compensation zones of a second conductivity type, which is complementary to the first conductivity type. The radiation conversion device combines high radiation hardness with cost effective manufacturing.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Armin Willmeroth, Hans-Joachim Schulze
  • Publication number: 20150035123
    Abstract: A curvature-control-material (CCM) is formed on one side of a substrate prior to forming a Group III nitride material on the other side of the substrate. The CCM possess a thermal expansion coefficient (TEC) that is lower than the TEC of the substrate and is stable at elevated growth temperatures required for formation of a Group III nitride material. In some embodiments, the deposition conditions of the CCM enable a flat-wafer condition for the Group III nitride material maximizing the emission wavelength uniformity of the Group III nitride material. Employment of the CCM also reduces the final structure bowing during cool down leading to reduced convex substrate curvatures. In some embodiments, the final structure curvature can further be engineered to be concave by proper selection of CCM properties, and via controlled selective etching of the CCM, this method enables the final structure to be flat.
    Type: Application
    Filed: August 1, 2013
    Publication date: February 5, 2015
    Applicant: International Business Machines Corporation
    Inventors: Can Bayram, Stephen W. Bedell, Devendra K. Sadana
  • Patent number: 8946064
    Abstract: A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, Judson R. Holt, Alexander Reznicek, Thomas A. Wallner
  • Patent number: 8940614
    Abstract: A method of forming an epitaxial SiC film on SiC substrates in a warm wall CVD system, wherein the susceptor is actively heated and the ceiling and sidewall are not actively heated, but are allowed to be indirectly heated by the susceptor. The method includes a first process of reaction cell preparation and a second process of epitaxial film growth. The epitaxial growth is performed by flowing parallel to the surface of the wafers a gas mixture of hydrogen, silicon and carbon gases, at total gas velocity in a range 120 to 250 cm/sec.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 27, 2015
    Assignee: Dow Corning Corporation
    Inventors: Mark J. Loboda, Jie Zhang
  • Publication number: 20150021624
    Abstract: A method to remove epitaxial semiconductor layers from a substrate by growing an epitaxial sacrificial layer on the substrate where the sacrificial layer is a transition metal nitride (TMN) or a TMN ternary compound, growing one or more epitaxial device layers on the sacrificial layer, and separating the device layers from the substrate by etching the sacrificial layer to completely remove the sacrificial layer without damaging or consuming the substrate or any device layer. Also disclosed are the related semiconductor materials made by this method.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 22, 2015
    Inventors: David J. Meyer, Brian P. Downey
  • Patent number: 8937005
    Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 20, 2015
    Assignee: SuVolta, Inc.
    Inventors: Lance S. Scudder, Pushkar Ranade, Charles Stager, Urupattur C. Sridharan, Dalong Zhao
  • Patent number: 8932942
    Abstract: Method of forming an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer. The method comprises etching a cavity into the top silicon layer and the insulator layer. A selective epitaxial step is performed for growing an epitaxial layer of silicon inside the cavity up to the surface of the top silicon layer. An electrical device comprising an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer formed according to the inventive method.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: January 13, 2015
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Philipp Steinmann, Manfred Schiekofer, Michael Kraus, Thomas Scharnagl, Wolfgang Schwartz
  • Patent number: 8928006
    Abstract: A groove structure formed on a surface of a substrate. The groove structure includes a lateral epitaxial pattern in a cross section perpendicular to the surface, which has: a first edge inclined to the surface; a second edge adjacent to first edge and parallel to the surface; a third edge parallel to the first edge, having a projection on the surface covering the second edge; and a fourth edge adjacent to the third edge. A first intersection between the second edge and the third edge on the second edge and an injection of a second intersection between the third edge and the fourth edge on the second edge are located on two sides of a third intersection between the first edge and the second edge, or the injection of the second intersection between the third edge and the fourth edge on the second edge coincides with the third intersection.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: January 6, 2015
    Assignees: Shenzhen BYD Auto R&D Company Limited, BYD Company Limited
    Inventors: Chunlin Xie, Xilin Su, Hongpo Hu, Wang Zhang
  • Patent number: 8927386
    Abstract: The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: January 6, 2015
    Assignees: CSMC Technologies FAB1 Co., Ltd., CSMC Technologies FAB2 Co., Ltd.
    Inventors: Tzong Shiann Wu, Genyi Wang, Leibing Yuan, Pengpeng Wu
  • Patent number: 8921205
    Abstract: Chemical vapor deposition methods are used to deposit amorphous silicon-containing films over various substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. Preferably, the deposited amorphous silicon-containing film is annealed to produce crystalline regions over all or part of an underlying substrate.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: December 30, 2014
    Assignee: ASM America, Inc.
    Inventor: Michael A. Todd
  • Patent number: 8921177
    Abstract: A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hsi Yeh, Hsien-Hsin Lin, Ying-Hsueh Chang Chien, Yi-Fang Pai, Chi-Ming Yang, Chin-Hsiang Lin
  • Patent number: 8916445
    Abstract: Semiconductor devices with reduced substrate defects and methods of manufacture are disclosed. The method includes forming a dielectric material on a substrate. The method further includes forming a shallow trench structure and deep trench structure within the dielectric material. The method further includes forming a material within the shallow trench structure and deep trench structure. The method further includes forming active areas of the material separated by shallow trench isolation structures. The shallow trench isolation structures are formed by: removing the material from within the deep trench structure and portions of the shallow trench structure to form trenches; and depositing an insulator material within the trenches.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: December 23, 2014
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 8916455
    Abstract: Inexpensive semiconductors are produced by depositing a single crystal or large grained silicon on an inexpensive substrate. These semiconductors are produced at low enough temperatures such as temperatures below the melting point of glass. Semiconductors produced are suitable for semiconductor devices such as photovoltaics or displays.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: December 23, 2014
    Assignees: Solar Tectic LLC, Trustees of Dartmouth College
    Inventors: Karin Chaudhari, Ashok Chaudhari, Pia Chaudhari
  • Patent number: 8906788
    Abstract: A method for making an epitaxial structure is provided. The method includes the following steps. A substrate is provided. The substrate has an epitaxial growth surface for growing epitaxial layer. A first carbon nanotube layer is placed on the epitaxial growth surface. A first epitaxial layer is epitaxially grown on the epitaxial growth surface. A second carbon nanotube layer is placed on the first epitaxial layer. A second epitaxial layer is epitaxially grown on the first epitaxial layer.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 9, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8907359
    Abstract: An optoelectronic semiconductor component comprising a semiconductor layer sequence (3) based on a nitride compound semiconductor and containing an n-doped region (4), a p-doped region (8) and an active zone (5) arranged between the n-doped region (4) and the p-doped region (8) is specified. The p-doped region (8) comprises a p-type contact layer (7) composed of InxAlyGa1-x-yN where 0?x?1, 0?y?1 and x+y?1. The p-type contact layer (7) adjoins a connection layer (9) composed of a metal, a metal alloy or a transparent conductive oxide, wherein the p-type contact layer (7) has first domains (1) having a Ga-face orientation and second domains (2) having an N-face orientation at an interface with the connection layer (9).
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: December 9, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Martin Strassburg, Lutz Höppel, Matthias Peter, Ulrich Zehnder, Tetsuya Taki, Andreas Leber, Rainer Butendeich, Thomas Bauer
  • Publication number: 20140357063
    Abstract: The present invention discloses manufacturing methods of semiconductor substrates. The method includes following steps: providing a semiconductor substrate with a nucleation layer, forming a microparticle etching mask on the nucleation layer, etching the nucleation layer, filling sol-gel into etched notches of the semiconductor substrate, removing the microparticle etching mask, performing growth of epitaxy rods and performing lateral connection of the top of the epitaxy rods to form a defect-free semiconductor substrate. The production methods of the present invention can confine the defects from the nucleation layer or the epitaxy rods to the epitaxy rods so as to generate a defect-free semiconductor substrate, that is, a semiconductor substrate with a defect-free growth film, after the lateral connection of the top of the epitaxy rods.
    Type: Application
    Filed: July 16, 2013
    Publication date: December 4, 2014
    Inventors: Chong-Ming LEE, Chung-Hua LEE
  • Patent number: 8900977
    Abstract: A method for making epitaxial structure is provided. The method includes providing a substrate having an epitaxial growth surface, placing a graphene layer on the epitaxial growth surface, and epitaxially growing an epitaxial layer on the epitaxial growth surface. The graphene layer includes a number of apertures to expose a part of the epitaxial growth surface. The epitaxial layer is grown from the exposed part of the epitaxial growth surface and through the aperture.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: December 2, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 8895413
    Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: November 25, 2014
    Assignee: Luxtera, Inc.
    Inventors: Thierry Pinguet, Steffen Gloeckner, Peter De Dobbelaere, Sherif Abdalla, Daniel Kucharski, Gianlorenzo Masini, Kosei Yokoyama, John Guckenberger, Attila Mekis
  • Patent number: 8895337
    Abstract: A top-down method of fabricating vertically aligned Group III-V micro- and nanowires uses a two-step etch process that adds a selective anisotropic wet etch after an initial plasma etch to remove the dry etch damage while enabling micro/nanowires with straight and smooth faceted sidewalls and controllable diameters independent of pitch. The method enables the fabrication of nanowire lasers, LEDs, and solar cells.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: November 25, 2014
    Assignee: Sandia Corporation
    Inventors: George T. Wang, Qiming Li
  • Patent number: 8877619
    Abstract: Structures and processes are provided that can be used for effectively integrating different transistor designs across a process platform. In particular, a bifurcated process is provided in which dopants and other processes for forming some transistor types may be performed prior to STI or other device isolation processes, and other devices may be formed thereafter. Thus, doping and other steps and their sequence with respect to the STI process can be selected to be STI-first or STI-last, depending on the device type to be manufactured, the range of device types that are manufactured on the same wafer or die, or the range of device types that are planned to be manufactured using the same or similar mask sets.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: November 4, 2014
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Lucian Shifren, Pushkar Ranade, Lance Scudder, Dalong Zhao, Teymur Bakhisher, Sameer Pradhan
  • Patent number: 8877616
    Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: November 4, 2014
    Assignee: Luxtera, Inc.
    Inventors: Thierry Pinguet, Steffen Gloeckner, Peter De Dobbelaere, Sherif Abdalla, Daniel Kucharski, Gianlorenzo Masini, Kosei Yokoyama, John Guckenberger, Attila Mekis
  • Patent number: 8878211
    Abstract: Provided are a heterogeneous substrate, a nitride-based semiconductor device using the same, and a manufacturing method thereof to form a high-quality non-polar or semi-polar nitride layer on a non-polar or semi-polar plane of the heterogeneous substrate by adjusting a crystal growth mode. A base substrate having one of a non-polar plane and a semi-polar plane is prepared, and a nitride-based nucleation layer is formed on the plane of the base substrate. A first buffer layer is grown faster in the vertical direction than in the lateral direction on the nucleation layer. A lateral growth layer is grown faster in the lateral direction than in the vertical direction on the first buffer layer. A second buffer layer is formed on the lateral growth layer. A silicon nitride layer having a plurality of holes may be formed between the lateral growth layer on the first buffer layer and the second buffer layer.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: November 4, 2014
    Assignee: Korea Electronics Technology Institute
    Inventors: Sung Min Hwang, Kwang Hyeon Baik, Yong Gon Seo, Hyung Do Yoon, Jae Hyoun Park
  • Patent number: 8871617
    Abstract: In one aspect, methods of forming mixed metal thin films comprising at least two different metals are provided. In some embodiments, a mixed metal oxide thin film is formed by atomic layer deposition and subsequently reduced to a mixed metal thin film. Reduction may take place, for example, in a hydrogen atmosphere. The presence of two or more metals in the mixed metal oxide allows for reduction at a lower reduction temperature than the reduction temperature of the individual oxides of the metals in the mixed metal oxide film.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: October 28, 2014
    Assignee: ASM IP Holding B.V.
    Inventors: Viljami J. Pore, Eva Tois
  • Patent number: 8871546
    Abstract: Various embodiments of the present disclosure pertain to selective photo-enhanced wet oxidation for nitride layer regrowth on substrates. In one aspect, a method may comprise: forming a first III-nitride layer with a first low bandgap energy on a first surface of a substrate; forming a second III-nitride layer with a first high bandgap energy on the first III-nitride layer; transforming portions of the first III-nitride layer into a plurality of III-oxide stripes by photo-enhanced wet oxidation; forming a plurality of III-nitride nanowires with a second low bandgap energy on the second III-nitride layer between the III-oxide stripes; and selectively transforming at least some of the III-nitride nanowires into III-oxide nanowires by selective photo-enhanced oxidation.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: October 28, 2014
    Assignee: Opto Tech Corporation
    Inventors: Lung-Han Peng, Jeng-Wei Yu, Po-Chun Yeh