Abstract: A metallic structure for an optical semiconductor device including a conductive base body having disposed thereon metallic layers in the following order: a nickel or nickel alloy plated layer, a gold or gold alloy plated layer, and an indium or indium alloy plated layer, wherein the indium or indium alloy plated layer has a thickness in a range of 0.002 ?m or more and 0.3 ?m or less.

Abstract: A SiC composite substrate includes a SiC single crystal layer and at least one biaxially oriented SiC layer. The at least one biaxially oriented SiC layer is disposed on the SiC single crystal. In the biaxially oriented SiC layer, the SiC is oriented in both a c-axis direction and an a-axis direction. The biaxially oriented SiC layer has pores and has a density of defect reaching the surface of 1.0×101/cm2 or less.

Abstract: Embodiments described herein relate to a method of epitaxial deposition of p-channel metal oxide semiconductor (MMOS) source/drain regions within horizontal gate all around (hGAA) device structures. Combinations of precursors are described herein, which grow of the source/drain regions on predominantly <100> surfaces with reduced or negligible growth on <110> surfaces. Therefore, growth of the source/drain regions is predominantly located on the top surface of a substrate instead of the alternating layers of the hGAA structure. The precursor combinations include a silicon containing precursor, a germanium containing precursor, and a boron containing precursor. At least one of the precursors further includes chlorine.

Abstract: A method includes forming a semiconductor structure. The structure includes a first material, a blocking material, a second material in an amorphous form, and a third material in an amorphous form. The blocking material is disposed between the first material and the second material. At least the second material and the third material each comprise silicon and/or germanium. The structure is exposed to a temperature above a crystallization temperature of the third material and below a crystallization temperature of the second material. Semiconductor structures, memory devices, and systems are also disclosed.

Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include depositing a silicon-containing material on the substrate. Subsequent a first period of time, the methods may include providing a germanium-containing precursor to the processing region of the semiconductor processing chamber. The methods may include thermally reacting the silicon-containing precursor and the germanium-containing precursor at a temperature greater than or about 400° C. The methods may include forming a silicon-and-germanium-containing layer on the substrate.

Abstract: The disclosed embodiments relate to an integrated circuit structure and methods of forming them in which photonic devices are formed on the back end of fabricating a CMOS semiconductor structure containing electronic devices. Doped regions associated with the photonic devices are formed using microwave annealing for dopant activation.

Abstract: Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.

Abstract: A method of making free-standing ALD-coated plasmonic nanoparticles. The method comprises providing a plurality of semiconductor quantum dots. One or more conformal layers of dielectric material are deposited over the quantum dots to form dielectric-coated quantum dots. A conformal metallic nanoshell is deposited over the dielectric-coated quantum dots to form plasmonic nanoparticles. At least one layer chosen from i) the conformal layers of dielectric material and ii) the conformal metallic nanoshell is deposited using a vapor phase atomic layer deposition (ALD) process. Plasmonic nanoparticles and systems employing the nanoparticles are also disclosed.

Abstract: A method for depositing a boron doped silicon germanium (Si1-xGex) film is disclosed. The method may include: providing a substrate within a reaction chamber; heating the substrate to a deposition temperature; flowing a silicon precursor, a germanium precursor, and a halide gas into the reaction chamber through a first gas injector; flowing a boron dopant precursor into the reaction chamber through a second gas injector independent from the first gas injector; contacting the substrate with the silicon precursor, the germanium precursor, the halide gas and the boron dopant precursor; and depositing the boron doped silicon germanium (Si1-xGex) film over a surface of the substrate.

Abstract: The semiconductor device includes a substrate, a fin structure, a source/drain region, and a gate structure. The fin structure includes a first-stage fin region, a second-stage fin region, and a third-stage fin region. The second-stage fin region is under the first-stage fin region. The third-stage fin region is under the second-stage fin region. The source/drain region is on a top surface of the second-stage fin region. The gate structure is over the first-stage fin region and wraps around a top surface and sidewalls of the first-stage fin region. The top surface of the second-stage fin region is lower than the top surface of the first-stage fin region. A width of the third-stage fin region is greater than a width of the second-stage fin region, and the width of the second-stage fin region is substantially the same as a width of the first-stage fin region.

Abstract: A semiconductor device including a nanostructure, comprising a planar layer (1020) of a Ill-nitride semiconductor crystal, which layer includes an array of epitaxially grown nanowire structures (1010), and semiconductor material (1016) which is redistributed from said nanowire structures in a reformation step after epitaxial growth, arranged to fill out a spacing between the nanowire structures, wherein the array of nanowire structures and the semiconductor material form a coherent layer.

Abstract: A plurality of trenches are formed so as to reach a prescribed depth from the surface of an n-type epitaxial layer. A refractory metal carbide film, such as a TaC film is formed via sputtering on the surface of sections (mesa regions) of the n-type epitaxial layer interposed between the adjacent trenches. Sections of the TaC film on the inner walls of the trenches are removed via etching. While the surface of the mesa regions is covered by the TaC film, the inside of the trenches is filled with a p-type epitaxial layer that is grown by CVD, thereby forming a parallel pn structure. Then, sections of the p-type epitaxial layer protruding above the surface of the parallel pn structure and the TaC film above the surface of the mesa regions are ground until top surfaces of n-type regions and p-type regions of the parallel pn structure are exposed.

Abstract: A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.

Abstract: A semiconductor structure including a multi-faceted epitaxial semiconductor structure within both a source region and a drain region and on exposed surfaces of a semiconductor fin is provided. The multi-faceted epitaxial semiconductor structure includes faceted epitaxial semiconductor material portions located on different portions of each vertical sidewall of the semiconductor fin and a topmost faceted epitaxial semiconductor material portion that is located on an exposed topmost horizontal surface of the semiconductor fin. The multi-faceted epitaxial semiconductor structure has increased surface area and thus an improvement in contact resistance can be obtained utilizing the same.

Abstract: The present disclosure provides a method for forming a semiconductor device. The method includes providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; and forming trenches in the semiconductor substrate on both sides of the gate structure. The method also includes forming a stress layer on inner sidewalls of each trench to fill up the trench; forming an interlayer on the stress layer, and forming a capping layer on the interlayer, wherein a top surface of the capping layer is higher than a top surface of the semiconductor substrate, and a lattice mismatch between the interlayer and the capping layer is lower than a lattice mismatch between the capping layer and the stress layer.

Abstract: The invention provides a nonpolar or semipolar GaN substrate, in which a nitride semiconductor crystal having a low stacking fault density can be epitaxially grown on the main surface of the substrate, and a method for manufacturing an M-plane GaN substrate by forming a mask pattern having a line-shaped opening parallel to an a-axis of a C-plane GaN substrate on an N-polar plane of the C-plane GaN substrate, growing a plane-shape GaN crystal of which thickness direction is an m-axis direction from the opening of the mask pattern by an ammonothermal method, and cutting out the M-plane GaN substrate from the plane-shape GaN crystal.

Abstract: A semiconductor device includes merged contact plugs. A multi-fin active having N sub-fins is formed in a substrate. A contact plug is formed on the impurity areas. N is an integer between about eight (8) and about one thousand (1000). The N sub-fins include a first sub-fin formed in the outermost portion of the multi-fin active and a second sub-fin formed near the first sub-fin. A straight line perpendicular to a surface of the substrate and passes through a virtual bottom edge of the contact plug is disposed between the first sub-fin and the second sub-fin, or through the second sub-fin. The virtual bottom edge of the contact plug is defined at a cross point of a correlation line extending on a side surface of the contact plug and a horizontal line in contact with a lowermost end of the contact plug and parallel to the surface of the substrate.

Abstract: As disclosed herein, a semiconductor device with aspect ratio trapping including, a bulk substrate, a plurality of isolation pillars formed on the bulk substrate, wherein one or more gaps are formed between the isolation pillars, an oxide layer formed by epitaxy on the bulk substrate, between the isolation pillars, wherein the oxide layer partially fills the gaps between the isolation pillars, one or more fins formed over the oxide layer between the isolation pillars, such that the one or more fins fill the gaps between the isolation pillars, wherein the oxide layer electrically isolates the one or more fins from the bulk substrate. The size of the gaps between the isolation pillars is selected to statistically eliminate defects caused by a lattice mismatch between the bulk substrate and the oxide layer. The semiconductor device may also contain an aspect-ratio trapping layer between the bulk substrate and oxide layer.

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a semiconductor substrate includes a shallow trench isolation structure disposed therein. A gate electrode structure overlies semiconductor material of the semiconductor substrate. A first sidewall spacer is formed adjacent to the gate electrode structure, with a first surface of the shallow trench isolation structure exposed and spaced from the first sidewall spacer by a region of the semiconductor material. The first surface of the shallow trench isolation structure is masked with an isolation structure mask. The region of the semiconductor material is free from the isolation structure mask. A recess is etched in the region of the semiconductor material, with the isolation structure mask in place. A semiconductor material is epitaxially grown within the recess to form an epitaxially-grown semiconductor region adjacent to the gate electrode structure.

Abstract: A method for growing aluminum indium nitride (AlInN) films on silicon substrates comprises several steps: firstly, arranging a silicon substrate in a reaction chamber; secondly, providing multiple reaction gases in the reaction chamber, wherein the reaction gases include aluminum precursors, indium precursors and nitrogen-containing gases; finally, dynamically adjusting flow rates of the reaction gases and directly growing an AlInN layer on the silicon substrate via a crystal growth process. By directly forming an AlInN layer on the silicon substrate, lattice matching is increased, residual thermal stress is reduced and film quality is improved. In addition, fabrication process is simplified and thus cost is reduced.

Abstract: An electronic device includes a III-V substrate having a hexagonal crystal structure and a normal to a growth surface characterized by a misorientation from the <0001> direction of between 0.15° and 0.65°. The electronic device also includes a first epitaxial layer coupled to the III-V substrate and a second epitaxial layer coupled to the first epitaxial layer. The electronic device further includes a first contact in electrical contact with the substrate and a second contact in electrical contact with the second epitaxial layer.

Abstract: As disclosed herein, a semiconductor device with aspect ratio trapping is provided, including a bulk substrate, a plurality of isolation pillars formed on the bulk substrate, wherein one or more gaps are formed between the isolation pillars, an oxide layer formed by epitaxy on the bulk substrate, between the isolation pillars, wherein the oxide layer partially fills the gaps between the isolation pillars, one or more fins formed over the oxide layer between the isolation pillars, such that the one or more fins fill the gaps between the isolation pillars, wherein the oxide layer electrically isolates the one or more fins from the bulk substrate. The oxide layer has an aspect ratio that is selected to substantially eliminate defects at the interface between the oxide layer and the fins. The semiconductor device may also include a semiconductor layer between the bulk substrate and oxide layer.

Abstract: A light emitting device includes an n-type layer, a p-type layer structure, a layer of p-type nano-dots imbedded in the p-type layer structure, and an active region sandwiched between the n-type layer and the p-type layer structure, where the p-type nano-dots possess a sheet density of 1010 to 1012 cm?2, a lateral dimension of 2-20 nm, and a vertical dimension of 1-5 nm. The p-type layer structure with a layer of p-type nano-dots imbedded therein provides good vertical conductivity and UV transparency. Also provided is a method for making the light emitting device.

Abstract: A method for making an integrated circuit includes at least a tri-gate FinFET and a dual-gate FinFET. The method includes providing a semiconductor on insulator (SOI) substrate. The method also includes implanting impurities into the substrate for adjusting a threshold voltage. The method provides a nitride film overlying a surface region of the substrate and selectively etches the silicon nitride film to form a nitride cap region. The method etches the silicon layer to form a first and a second silicon fin regions. The nitride cap region is maintained on a portion of a surface region of the first silicon fin region. The method includes forming a gate dielectric, depositing a polysilicon film, and planarizing the polysilicon film by chemical mechanical polishing (CMP) using the nitride cap region as a polish stop. The method etches the polysilicon film to form gate electrodes. The method forms elevated source and drain regions.

Abstract: Integrated circuits having metal-insulator-semiconductor (MIS) contact structures and methods for fabricating integrated circuits having metal-insulator-semiconductor (MIS) contact structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure formed from semiconductor material overlying a semiconductor substrate. The method includes depositing a layer of high-k dielectric material over the fin structure. Further, the method includes forming a metal layer or layers over the layer of high-k dielectric material to provide the fin structure with a metal-insulator-semiconductor (MIS) contact structure.

Abstract: A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.

Abstract: A method of manufacturing an III-N substrate includes bonding a Si substrate to a support substrate, the Si substrate having a (111) growth surface facing away from the support substrate, thinning the Si substrate at the (111) growth surface to a thickness of 100 ?m or less, and forming III-N material on the (111) growth surface of the Si substrate after the Si substrate is thinned. The support substrate has a coefficient of thermal expansion more closely matched to that of the III-N material than the Si substrate. Other methods of manufacturing an III-N substrate are disclosed, as well as the corresponding wafer structures.

Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.

Abstract: Methods for forming a layer of semiconductor material and a semiconductor-on-insulator structure are provided. A substrate including one or more devices or features formed therein is provided. A seed layer is bonded to the substrate, where the seed layer includes a crystalline semiconductor structure. A first portion of the seed layer that is adjacent to an interface between the seed layer and the substrate is amorphized. A second portion of the seed layer that is not adjacent to the interface is not amorphized and maintains the crystalline semiconductor structure. Dopant implantation is performed to form an N-type conductivity region or a P-type conductivity region in the first portion of the seed layer. A solid-phase epitaxial growth process is performed to crystallize the first portion of the seed layer. The SPE growth process uses the crystalline semiconductor structure of the second portion of the seed layer as a crystal template.

Abstract: A method for manufacturing a light-emitting diode, which includes the steps of: providing a substrate having a plurality of protruded portions on one main surface thereof wherein the protruded portion is made of a material different in type from that of the substrate and growing a first nitride-based III-V Group compound semiconductor layer on each recess portion of the substrate through a state of making a triangle in section wherein a bottom surface of the recess portion becomes a base of the triangle; laterally growing a second nitride-based III-V Group compound semiconductor layer on the substrate from the first nitride-based III-V Group compound semiconductor layer; and successively growing, on the second nitride-based III-V Group compound semiconductor layer, a third nitride-based III-V Group compound semiconductor layer of a first conduction type, an active layer, and a fourth nitride-based III-V compound semiconductor layer of a second conduction type.

Abstract: Methods and structures for GaN on silicon-containing substrates are disclosed, comprising a texturing process to generate a rough surface containing (111) surface, which then can act as an underlayer for epitaxial GaN. LED devices are then fabricated on the GaN layer. Variations of the present invention include different orientations of silicon layer instead of (100), such as (110) or others; and other semiconductor materials instead of GaN, such as other semiconductor materials suitable for LED devices.

Abstract: A method of manufacturing a semiconductor device is disclosed. In one embodiment, the method comprises: forming a gate stack on a substrate; etching the substrate on both sides of the gate stack to form C-shaped source/drain grooves; and wet-etching the C-shaped source/drain grooves to form ?-shaped source/drain grooves. With this method, it is possible to effectively increase stress applied to a channel region, to accurately control a depth of the source/drain grooves, and to reduce roughness of side walls and bottom portions of the grooves and thus reduce defects by etching the C-shaped source/drain grooves and then further wet-etching them to form the ?-shaped source/drain grooves.

Abstract: A method of forming an epitaxial layer includes forming a plurality of first insulation patterns in a substrate, the plurality of first insulation patterns spaced apart from each other, forming first epitaxial patterns on the plurality of first insulation patterns, forming second insulation patterns between the plurality of first insulation patterns to contact the plurality of first insulation patterns, and forming second epitaxial patterns on the second insulation patterns and between the first epitaxial patterns to contact the first epitaxial patterns, the first epitaxial patterns and the second epitaxial patterns forming a single epitaxial layer.

Abstract: The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes several operations as follows. A semiconductor substrate is received. A trench along a depth in the semiconductor substrate is formed. The semiconductor substrate is exposed in a hydrogen containing atmosphere. Dopants are inserted into a portion of the semiconductor substrate. A dielectric is filled in the trench. The dopants are driven into a predetermined distance in the semiconductor substrate.

Abstract: An SOI substrate and a method for forming the SOI substrate are provided. An SOI substrate can be formed by forming a silicon-germanium layer on a first baseplate. A top silicon layer can be formed on the silicon-germanium layer. A first insulating layer can be formed on the top silicon layer. An ion implanted layer can be formed in one of the silicon-germanium layer and the first baseplate. A second baseplate can be bonded to the first insulating layer. A first annealing process can be performed to anneal and split the one of the silicon-germanium layer and the first baseplate at the ion implanted layer. The silicon-germanium layer can be removed from the top silicon layer to expose the top silicon layer and to form the SOI substrate comprising the first insulating layer formed between the top silicon layer and the second baseplate.

Abstract: A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures.

Abstract: Oxygen, silicon, germanium, carbon, or nitrogen is selectively implanted into a workpiece. The workpiece is annealed to incorporate the ions into the workpiece. A compound semiconductor is then formed on the workpiece. For example, gallium nitride may be formed on a silicon, silicon carbide, or sapphire workpiece. The width of the implanted regions can be configured to compensate for any shrinkage during annealing.

Abstract: An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit.

Abstract: According to an embodiment, a method for stress-reduced forming a semiconductor device includes: providing a semiconductor wafer including an upper side and a first semiconductor layer of a first semiconductor material at the upper side; forming, in a vertical cross-section which is substantially orthogonal to the upper side, at the upper side a plurality of first vertical trenches and a plurality of second vertical trenches between adjacent first vertical trenches so that the first vertical trenches have, in the vertical cross-section, a larger horizontal extension than the second vertical trenches; and forming a plurality of third semiconductor layers at the upper side which are, in the vertical cross-section, spaced apart from each other by gaps each of which overlaps, in the vertical cross-section, with a respective first vertical trench when seen from above. At least one of the third semiconductor layers includes a semiconductor material which is different to the first semiconductor material.

Abstract: A radiation conversion device such as a photovoltaic cell, a photodiode or a semiconductor radiation detection device, includes a semiconductor portion with first compensation zones of a first conductivity type and a base portion that separates the first compensation zones from each other. The first compensations zones are arranged in pillar structures. Each pillar structure includes spatially separated first compensation zones and extends in a vertical direction with respect to a main surface of the semiconductor portion. Between neighboring ones of the pillar structures the base portion includes second compensation zones of a second conductivity type, which is complementary to the first conductivity type. The radiation conversion device combines high radiation hardness with cost effective manufacturing.

Abstract: A curvature-control-material (CCM) is formed on one side of a substrate prior to forming a Group III nitride material on the other side of the substrate. The CCM possess a thermal expansion coefficient (TEC) that is lower than the TEC of the substrate and is stable at elevated growth temperatures required for formation of a Group III nitride material. In some embodiments, the deposition conditions of the CCM enable a flat-wafer condition for the Group III nitride material maximizing the emission wavelength uniformity of the Group III nitride material. Employment of the CCM also reduces the final structure bowing during cool down leading to reduced convex substrate curvatures. In some embodiments, the final structure curvature can further be engineered to be concave by proper selection of CCM properties, and via controlled selective etching of the CCM, this method enables the final structure to be flat.

Abstract: A method of forming a semiconductor device that includes providing a substrate including a semiconductor layer on a germanium-containing silicon layer and forming a gate structure on a surface of a channel portion of the semiconductor layer. Well trenches are etched into the semiconductor layer on opposing sides of the gate structure. The etch process for forming the well trenches forms an undercut region extending under the gate structure and is selective to the germanium-containing silicon layer. Stress inducing semiconductor material is epitaxially grown to fill at least a portion of the well trench to provide at least one of a stress inducing source region and a stress inducing drain region having a planar base.

Abstract: A method of forming an epitaxial SiC film on SiC substrates in a warm wall CVD system, wherein the susceptor is actively heated and the ceiling and sidewall are not actively heated, but are allowed to be indirectly heated by the susceptor. The method includes a first process of reaction cell preparation and a second process of epitaxial film growth. The epitaxial growth is performed by flowing parallel to the surface of the wafers a gas mixture of hydrogen, silicon and carbon gases, at total gas velocity in a range 120 to 250 cm/sec.

Abstract: A method to remove epitaxial semiconductor layers from a substrate by growing an epitaxial sacrificial layer on the substrate where the sacrificial layer is a transition metal nitride (TMN) or a TMN ternary compound, growing one or more epitaxial device layers on the sacrificial layer, and separating the device layers from the substrate by etching the sacrificial layer to completely remove the sacrificial layer without damaging or consuming the substrate or any device layer. Also disclosed are the related semiconductor materials made by this method.

Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

Abstract: Method of forming an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer. The method comprises etching a cavity into the top silicon layer and the insulator layer. A selective epitaxial step is performed for growing an epitaxial layer of silicon inside the cavity up to the surface of the top silicon layer. An electrical device comprising an electrical contact between a support wafer and a surface of a top silicon layer of a silicon-on-insulator wafer formed according to the inventive method.

Abstract: The present invention provides a method for manufacturing a deep-trench super PN junction. The method includes: a deposition step for forming an epitaxial layer on a substrate; forming a first dielectric layer and a second dielectric layer in sequence on the epitaxial layer; forming deep trenches in the epitaxial layer; completely filling the deep trenches with an epitaxial material and the epitaxial material is beyond the second dielectric layer; filling the entire surface of the second dielectric layer and the epitaxial layer such as Si using a third dielectric to from a surface filling layer with a predetermined height; etching back on the surface filling layer to the interface of the first dielectric layer and the epitaxial layer; and a removing step for removing the first dielectric layer, the second dielectric layer and the surface filling layer to planarize Si epitaxial material.

Abstract: A groove structure formed on a surface of a substrate. The groove structure includes a lateral epitaxial pattern in a cross section perpendicular to the surface, which has: a first edge inclined to the surface; a second edge adjacent to first edge and parallel to the surface; a third edge parallel to the first edge, having a projection on the surface covering the second edge; and a fourth edge adjacent to the third edge. A first intersection between the second edge and the third edge on the second edge and an injection of a second intersection between the third edge and the fourth edge on the second edge are located on two sides of a third intersection between the first edge and the second edge, or the injection of the second intersection between the third edge and the fourth edge on the second edge coincides with the third intersection.

Abstract: A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid.