On Insulating Substrate Or Layer Patents (Class 438/479)
  • Patent number: 11990476
    Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having <111> lateral sidewalls along a <110> carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having <111> lateral sidewalls along a <110> carrier transport direction.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Cory E. Weber, Harold W. Kennel, Willy Rachmady, Gilbert Dewey
  • Patent number: 11888024
    Abstract: A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material; introducing dopants into a portion of the filling material; and applying a first thermal processing to the semiconductor body to spread the dopants in the filling material along a vertical direction of the filling material by a diffusion process. The vertical doping profile of the dopants within the doped filling material is shaped during the first thermal processing. Additionally, the dopants are substantially confined to within the trench and substantially do not diffuse from the doped filling material into the semiconductor body during the first thermal processing. A second thermal processing is applied to the semiconductor body after the first thermal processing to cause diffusion of the dopants from the doped filling material into the semiconductor body adjoining the trench.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: January 30, 2024
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Ploss, Hans-Joachim Schulze
  • Patent number: 11807936
    Abstract: A method of producing gallium-doped zinc oxide films with enhanced conductivity. The method includes depositing a gallium-doped zinc oxide film on a substrate using a pulsed laser and subjecting the deposited gallium-dope zinc oxide film to a post-treatment effecting recrystallization in the deposited film, wherein the recrystallization enhances the conductivity of the film. Another method of producing gallium-doped zinc oxide films with enhanced conductivity. The method includes the steps of depositing a gallium-doped zinc oxide film on a substrate using a pulsed laser and subjecting the deposited gallium-dope zinc oxide film to an ultraviolet laser beam resulting in recrystallization in the film, wherein the recrystallization enhances the conductivity of the film. A film comprising gallium-doped zinc oxide wherein the film contains a recrystallized grain structure on its surface.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: November 7, 2023
    Assignee: Purdue Research Foundation
    Inventors: Gary J. Cheng, Qiong Nian
  • Patent number: 11795538
    Abstract: The preparation method for a nano composite coating having a shell-simulated multi-arch structure includes: constructing a discontinuous metal seed layer using a vacuum plating technology; and inducing the deposition of a continuous multi-arch structure layer utilizing the discontinuous metal seed layer, thereby realizing the controllable orientated growth of the nano composite coating having the shell-simulated multi-arch structure.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: October 24, 2023
    Assignee: NINGBO INSTITUTE OF MATERIALS TECHNOLOGY & ENGINEERING, CHINESE ACADEMY OF SCIENCES
    Inventors: Liping Wang, Minpeng Dong, Jinlong Li
  • Patent number: 11778817
    Abstract: A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: October 3, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ashish Kumar Baraskar, Raghuveer S. Makala, Peter Rabkin
  • Patent number: 11749530
    Abstract: A method of removing a phosphorus-doped silicon film doped with phosphorus, includes: forming a silicon oxide film by oxidizing the phosphorus-doped silicon film in a substrate including the phosphorus-doped silicon film and an undoped silicon film which is not been doped with the phosphorus, wherein at least the phosphorus-doped silicon film is exposed to a surface of the substrate; and selectively etching and removing the silicon oxide film from the silicon oxide film and the undoped silicon film.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: September 5, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Yoshihiro Takezawa, Masahisa Watanabe
  • Patent number: 11738505
    Abstract: An additive manufacturing system includes at least two photoconductor plates attached to a substrate. Each photoconductor plate can include separate the Linear Electro layers and transparent conductive oxide layers.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: August 29, 2023
    Assignee: Seurat Technologies, Inc.
    Inventors: Francis L. Leard, James A. DeMuth, Andrew J. Bayramian, Drew W. Kissinger, Joseph Gillespie
  • Patent number: 11726377
    Abstract: A display device includes: a substrate including a display region and a peripheral region, wherein the peripheral region is adjacent to the display region; a first transistor disposed on the peripheral region, wherein the first transistor includes a first semiconductor layer and the first semiconductor layer is a silicon semiconductor layer; and a second transistor disposed on the display region, wherein the second transistor includes a second semiconductor layer and the second semiconductor layer is an oxide semiconductor layer, wherein the first transistor is electrically connected to the second transistor.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: August 15, 2023
    Assignee: INNOLUX CORPORATION
    Inventors: Chandra Lius, Kuan-Feng Lee, Nai-Fang Hsu
  • Patent number: 11711919
    Abstract: A semiconductor memory device comprises: a plurality of first conductive layers arranged separated from each other in a first direction; a plurality of second conductive layers arranged, electrically insulated from the plurality of first conductive layers, at a different position in a second direction intersecting the first direction with respect to the first conductive layers; a plurality of memory structures; and a source structure. Respective one ends of the plurality of memory structures and one end of the source structure are electrically connected. The respective other ends of the plurality of memory structures are respectively electrically connected to different first wirings of a plurality of first wirings formed in the same layer in the first direction. The other end of the source structure is electrically connected to a second wiring formed in a different layer from the plurality of first wirings in the first direction.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: July 25, 2023
    Assignee: Kioxia Corporation
    Inventor: Daigo Ichinose
  • Patent number: 11704532
    Abstract: Techniques are disclosed for a hybrid undo/redo for text editing, where non-linear undo and redo operations are performed across dynamic regions in a document and linear undo and redo operations are performed within the dynamic regions in the document. In an example, the hybrid undo/redo may be achieved by maintaining respective region offset values for the dynamic regions created in a document by the edits made to the document. In operation, the respective region offset values associated with the dynamic regions can be used to negate or otherwise counteract the effect of edits made in the dynamic regions.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: July 18, 2023
    Assignee: Citrix Systems, Inc.
    Inventors: Yajun Yao, Yuan Bai, Juanjuan Chen
  • Patent number: 11700855
    Abstract: Methods of synthesizing Bi2S3—CdS particles in the form of spheres as well as properties of these Bi2S3—CdS particles are described. Methods of photocatalytic degradation of organic pollutants employing these Bi2S3—CdS particles and methods of preventing or reducing microbial growth on a surface by applying these Bi2S3—CdS particles in the form of a solution or an antimicrobial product onto the surface are also specified.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: July 18, 2023
    Assignee: Imam Abdulrahman Bin Faisal University
    Inventors: Muhammad Nawaz, Faiza Qureshi
  • Patent number: 11695059
    Abstract: A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: July 4, 2023
    Assignee: International Business Machines Corporation
    Inventors: Tao Li, Indira Seshadri, Nelson Felix, Eric Miller
  • Patent number: 11670539
    Abstract: A method of making a semiconductor arrangement includes forming a first layer of molecular ions in a first wafer interface region of a first wafer, forming a second layer of molecular ions in a second wafer interface region of a second wafer, forming a first molecular bond connecting the first wafer interface region to the second wafer interface region by applying pressure to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region, and annealing the first wafer and the second wafer to form a second molecular bond connecting the first wafer interface region to the second wafer interface region.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Che Lee, Sheng-Chau Chen, Cheng-Hsien Chou, Cheng-Yuan Tsai
  • Patent number: 11664373
    Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: May 30, 2023
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Patrick Morrow, Gilbert Dewey, Willy Rachmady, Rishabh Mehandru
  • Patent number: 11664474
    Abstract: Embodiments of the present application provide an array substrate, a fabrication method for an array substrate, and a display panel. The array substrate includes a substrate, a gate, a gate insulating layer, a seed layer, and a semiconductor layer that are sequentially stacked. A surface of the semiconductor layer away from the seed layer has a concave-convex structure formed by growth of nanocrystalline grains, which enhances light absorption of the semiconductor layer and solves the problems of poor light sensitivity and slow response speed of semiconductor devices.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: May 30, 2023
    Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD
    Inventor: Yuhao Zhai
  • Patent number: 11658087
    Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: May 23, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin
  • Patent number: 11652017
    Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: May 16, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin
  • Patent number: 11625001
    Abstract: The invention discloses an optical system for generating arbitrary-order optical vortex arrays and finite optical lattices with defects, comprising a laser, a collimating and beam-expanding system, a spatial light modulator, a 4-f lens system, and an image detector which are disposed according to a light path. After passing through the collimating and beam-expanding system, the linearly-polarized Gaussian beam emitted by the laser is radiated to the spatial light modulator to be modulated in complex amplitude; the first-order diffraction beam of the emergent light generates an arbitrary-order alternating optical vortex array on the back focal plane of the first 2-f lens system, and an adjustable finite optical lattice with defects on the back focal plane of the second 2-f lens system. The topological charge value of each vortex and the spacing between vortices, in the generated arbitrary-order alternating optical vortex array, can be precisely controlled.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: April 11, 2023
    Assignee: Zhejiang University
    Inventors: Ligang Wang, Dadong Liu
  • Patent number: 11619870
    Abstract: A projector includes a laser source, a light modulation element configured to modulate light emitted from the laser source in accordance with image information, and a light transmissive member disposed in a light path between the laser source and the light modulation element, and configured to transmit the light emitted from the laser source, wherein the laser source and the light modulation element are bonded to the light transmissive member, the laser source includes a substrate, and a laminated structure provided to the substrate, and having a light emitting layer configured to emit light, and the laminated structure constitutes a photonic crystal structure configured to confine the light emitted by the light emitting layer in an in-plane direction of the substrate, and emit the light emitted by the light emitting layer in a normal direction of the substrate.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 4, 2023
    Inventor: Yoshitaka Itoh
  • Patent number: 11621270
    Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: April 4, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Dimitrios Pavlopoulos, Kunal Shrotri, Anish A. Khandekar
  • Patent number: 11616206
    Abstract: The yield of a separation process is improved. The mass productivity of a display device which is formed through a separation process is improved. A layer is formed over a substrate with use of a material including a resin or a resin precursor. Next, a resin layer is formed by performing heat treatment on the layer. Next, a layer to be separated is formed over the resin layer. Then, the layer to be separated and the substrate are separated from each other. The heat treatment is performed in an atmosphere containing oxygen or while supplying a gas containing oxygen.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: March 28, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masakatsu Ohno, Kayo Kumakura, Hiroyuki Watanabe, Seiji Yasumoto, Satoru Idojiri, Hiroki Adachi
  • Patent number: 11588032
    Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: February 21, 2023
    Inventors: Kwang Soo Seol, Chanjin Park, Kihyun Hwang, Hanmei Choi, Sunghoi Hur, Wansik Hwang, Toshiro Nakanishi, Kwangmin Park, Juyul Lee
  • Patent number: 11587787
    Abstract: A film forming method includes: forming a laminated film, in which an interface layer, a bulk layer, and a surface layer are laminated in this order, on a base; and crystallizing the laminated film, wherein the bulk layer is formed of a film that is easier to crystallize than the interface layer in crystallizing the laminated film, and wherein the surface layer is formed of a film that is easier to crystallize than the bulk layer in crystallizing the laminated film.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: February 21, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihiro Takezawa, Daisuke Suzuki, Hiroyuki Hayashi, Yutaka Motoyama
  • Patent number: 11550140
    Abstract: Increasing transparency of one or more micro-displays. A method includes attaching a transparent cover to at least a portion of a semiconductor wafer. The at least a portion of the semiconductor wafer includes the one or more micro-displays. The one or more micro-displays include one or more active silicon areas. The method further includes, after the transparent cover has been attached to the at least a portion of the semiconductor wafer, removing silicon between one or more of the active silicon areas.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: January 10, 2023
    Assignee: L3HARRIS TECHNOLOGIES, INC.
    Inventors: Jacob Becker, Jon Burnsed
  • Patent number: 11502217
    Abstract: A method and apparatus for reducing as-deposited and metastable defects relative to amorphous silicon (a-Si) thin films, its alloys and devices fabricated therefrom that include heating an earth shield positioned around a cathode in a parallel plate plasma chemical vapor deposition chamber to control a temperature of a showerhead in the deposition chamber in the range of 350° C. to 600° C. An anode in the deposition chamber is cooled to maintain a temperature in the range of 50° C. to 450° C. at the substrate that is positioned at the anode. In the apparatus, a heater is embedded within the earth shield and a cooling system is embedded within the anode.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: November 15, 2022
    Inventor: Gautam Ganguly
  • Patent number: 11493385
    Abstract: Embodiments of the present invention are directed to lightweight, portable spectrograph systems configured for applications in high-throughput crop phenotyping and plant health assessment, and associated methods.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: November 8, 2022
    Assignee: University of Florida Research Foundation, Incorporated
    Inventors: Stephen Scott Eikenberry, Md. Ali Babar
  • Patent number: 11462645
    Abstract: A semiconductor device which has favorable electrical characteristics is provided. A method for manufacturing a semiconductor device with high productivity is provided. A method for manufacturing a semiconductor device with a high yield is provided.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: October 4, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasutaka Nakazawa, Yukinori Shima, Kenichi Okazaki, Junichi Koezuka, Shunpei Yamazaki
  • Patent number: 11462579
    Abstract: A method for forming a transfer gate includes (i) forming a dielectric pillar on a surface of a semiconductor substrate and (ii) growing an epitaxial layer on the semiconductor substrate and surrounding the dielectric pillar. The dielectric pillar has a pillar height that exceeds an epitaxial-layer height of the epitaxial layer relative to the surface. The method also includes removing the dielectric pillar to yield a trench in the epitaxial layer. A pixel includes a doped semiconductor substrate having a front surface opposite a back surface. The front surface forms a trench extending a depth zT with respect to the front surface within the doped semiconductor substrate along a direction z perpendicular to the front surface and the back surface. The pixel has a dopant concentration profile, a derivative thereof with respect to direction z being discontinuous at depth zT.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: October 4, 2022
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hui Zang, Gang Chen
  • Patent number: 11392024
    Abstract: A portion of a buffer layer on a backside of a substrate of a photomask assembly may be removed prior to formation of one or more capping layers on the backside of the substrate. The one or more capping layers may be formed directly on the backside of the substrate where the buffer layer is removed from the substrate, and a hard mask layer may be formed directly on the one or more capping layers. The one or more capping layers may include a low-stress material to promote adhesion between the one or more capping layers and the substrate, and to reduce and/or minimize peeling and delamination of the capping layer(s) from the substrate. This may reduce the likelihood of damage to the pellicle layer and/or other components of the photomask assembly and/or may increase the yield of an exposure process in which the photomask assembly is used.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: July 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Hao Lee, Hsi-Cheng Hsu, Jui-Chun Weng, Han-Zong Pan, Hsin-Yu Chen, You-Cheng Jhang
  • Patent number: 11387102
    Abstract: A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung Ying Lee, Shao-Ming Yu
  • Patent number: 11387382
    Abstract: The invention provides a bifacial photovoltaic cell comprising: a semiconductor substrate, the substrate comprising an n+ layer on a first surface, and a p+ layer on a second surface. The n+ layer comprises an n-dopant and the p+ layer comprises a p-dopant. The cell further comprises a passivating and/or antireflective coating on the doped first and second surfaces. The cell is characterized in that the second surface of the semiconductor substrate has an area substantially devoid of the p-dopant on an edge of the second surface having a width in the range of 0.1-0.5 mm; wherein the area is formed by etching the semiconductor substrate.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: July 12, 2022
    Assignee: SOLAROUND LTD.
    Inventors: Naftali Paul Eisenberg, Lev Kreinin
  • Patent number: 11362103
    Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Changhan Kim, Gianpietro Carnevale
  • Patent number: 11313038
    Abstract: A method of fabricating semi-polar gallium nitride includes providing a silicon-on-insulator (SOI) substrate. The SOI substrate includes a substrate, a silicon oxide layer and a silicon substrate. The silicon substrate has (1,0,0) facets. The silicon oxide layer is disposed between the substrate and the silicon substrate. Later, a vapor etching process is performed to etch the (1,0,0) facets to form (1,1,1) facets. The vapor etching process is performed by disposing a nebulizer under the SOI substrate. The top surface of the silicon substrate faces the nebulizer. Later, the nebulizer turns etchant into mist to etch the (1,0,0) facets by the mist to form (1,1,1) facets. Finally, an epitaxial process is performed to grow a semi-polar gallium nitride layer on the (1,1,1) facets.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: April 26, 2022
    Assignee: Wafer Works Corporation
    Inventors: Wen-Chung Li, Ping-Hai Chiao
  • Patent number: 11201231
    Abstract: A silicon germanium alloy is formed on sidewall surfaces of a silicon fin. An oxidation process or a thermal anneal is employed to convert a portion of the silicon fin into a silicon germanium alloy fin. In some embodiments, the silicon germanium alloy fin has a wide upper portion and a narrower lower portion. In such an embodiment, the wide upper portion has a greater germanium content than the narrower lower portion. In other embodiments, the silicon germanium alloy fin has a narrow upper portion and a wider lower portion. In this embodiment, the narrow upper portion of the silicon germanium alloy fin has a greater germanium content than the wider lower portion of the silicon germanium alloy fin.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: December 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Hong He, Juntao Li
  • Patent number: 11081386
    Abstract: A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA-nitrides, semiconductor oxides, and any combination thereof.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: August 3, 2021
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Srikanth Kommu, Gang Wang, Shawn George Thomas
  • Patent number: 11031483
    Abstract: A method includes providing a first layer of epitaxial silicon carbide supported by a silicon carbide substrate, providing a second layer of epitaxial silicon carbide on the first layer, forming a plurality of semiconductor devices in the second layer, and separating the substrate from the second layer at the first layer. The first layer includes a plurality of voids.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: June 8, 2021
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Roland Rupp, Francisco Javier Santos Rodriguez
  • Patent number: 11024545
    Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Kuo-Cheng Ching, Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu
  • Patent number: 10991755
    Abstract: Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 27, 2021
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Eric Ladizinsky, Geordie Rose, Jeremy P. Hilton, Eugene Dantsker, Byong Hyop Oh
  • Patent number: 10903349
    Abstract: An electronic component with multiple quantum islands is provided, including a substrate on which rests a nanowire made of semiconductor material not intentionally doped; two main control gates resting on the nanowire so as to form respective qubits in the nanowire, the two main control gates being separated by a groove, and bottom and lateral faces of the groove are covered by a dielectric layer; an element made of conductive material formed on the dielectric layer in the groove; a carrier reservoir that is offset with respect to the nanowire, the element made of the conductive material being separated from the carrier reservoir by another dielectric layer such that the element made of the conductive material is coupled to the carrier reservoir by field effect. A method of fabricating an electronic component with multiple quantum islands is also provided.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: January 26, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Louis Hutin, Sylvain Barraud, Benoit Bertrand, Maud Vinet
  • Patent number: 10896887
    Abstract: A semiconductor device includes a semiconductor body, a stress relieving layer or layer stack disposed over at least part of the semiconductor body, the stress relieving layer or layer stack comprising a plurality of openings which yield a patterned surface topography for the stress relieving layer or layer stack, and a metal layer or layer stack formed on the stress relieving layer or layer stack and occupying the plurality of openings in the stress relieving layer or layer stack. The patterned surface topography of the stress relieving layer or layer stack is transferred to a surface of the metal layer or layer stack facing away from the semiconductor body. The stress relieving layer or layer stack has a different elastic modulus than the metal layer or layer stack over a temperature range.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: January 19, 2021
    Assignee: Infineon Technologies AG
    Inventors: Marius Aurel Bodea, Terry Richard Heidmann, Marianne Mataln, Claudia Sgiarovello
  • Patent number: 10879080
    Abstract: A method for forming a polycrystalline semiconductor layer includes forming a plurality of spacers over a dielectric layer, etching the dielectric layer using the plurality of spacers as an etch mask to form a recess in the dielectric layer, depositing an amorphous semiconductor layer over the plurality of spacers and the dielectric layer to fill the recess, and recrystallizing the amorphous semiconductor layer to form a polycrystalline semiconductor layer.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Cheng-Hsien Wu
  • Patent number: 10868180
    Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Yin Lin, Teng-Chun Tsai, Po-Yu Lin
  • Patent number: 10840328
    Abstract: A semiconductor device includes a charge-absorbing structure disposed over a substrate; an insulating layer disposed over the charge-absorbing structure; a semiconductor layer disposed over the insulating layer; a plurality of first doped regions and a plurality of second doped regions disposed in the semiconductor layer, wherein the first doped regions and second doped regions extend in a first direction and are alternately arranged along a second direction that is different than the first direction, and the plurality of first doped regions and the plurality of second doped regions have different conductivity types; a source and a drain disposed respectively on opposite sides of the plurality of first doped regions and the plurality of second doped regions and extend in the second direction; and a gate disposed on the plurality of first doped regions and the plurality of second doped regions and extends in the second direction.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: November 17, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jui-Chun Chang, Bo-Yuan Su, Chien-Nan Liao
  • Patent number: 10804166
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: October 13, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • Patent number: 10770616
    Abstract: Fabrication of a heterostructure, such as a group III nitride heterostructure, for use in an optoelectronic device is described. The heterostructure can be epitaxially grown on a sacrificial layer, which is located on a substrate structure. The sacrificial layer can be at least partially decomposed using a laser. The substrate structure can be completely removed from the heterostructure or remain attached thereto. One or more additional solutions for detaching the substrate structure from the heterostructure can be utilized. The heterostructure can undergo additional processing to form the optoelectronic device.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 8, 2020
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Alexander Dobrinsky, Maxim S. Shatalov
  • Patent number: 10741590
    Abstract: A peeling method at low cost with high mass productivity is provided. A silicon layer having a function of releasing hydrogen by irradiation with light is formed over a formation substrate, a first layer is formed using a photosensitive material over the silicon layer, an opening is formed in a portion of the first layer that overlaps with the silicon layer by a photolithography method and the first layer is heated to form a resin layer having an opening, a transistor including an oxide semiconductor in a channel formation region is formed over the resin layer, a conductive layer is formed to overlap with the opening of the resin layer and the silicon layer, the silicon layer is irradiated with light using a laser, and the transistor and the formation substrate are separated from each other.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: August 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masataka Sato, Masakatsu Ohno, Seiji Yasumoto, Hiroki Adachi
  • Patent number: 10672911
    Abstract: A thin film transistor array panel device comprises: a base substrate; a barrier layer disposed over the base substrate and comprising a plurality of transparent material layers; and an array of thin film transistors disposed over the barrier layer. A difference between a refractive index of the barrier layer and a refractive index of the base substrate may be within about 6%. The transparent material layers may be arranged such that the transparent material layers having compressive residual stress and the transparent material layers having tensile residual stress are alternately stacked. Each of the transparent material layers may comprise silicon oxynitride (SiON).
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Ho Jung, Chaun Gi Choi, Hye Young Park, Eun Young Lee, Joo Hee Jeon, Eun Jeong Cho, Bo Geon Jeon, Yung Bin Chung
  • Patent number: 10593553
    Abstract: Exemplary methods for etching a germanium-containing material may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a semiconductor processing chamber. The methods may include flowing effluents of the fluorine-containing precursor through apertures defined in a chamber component. The apertures may be coated with a catalytic material. The methods may include reducing a concentration of fluorine radicals in the plasma effluents with the catalytic material. The methods may also include delivering the plasma effluents to a processing region of the semiconductor processing chamber. A substrate having an exposed region of a germanium-containing material may be housed within the processing region. The methods may further include etching the germanium-containing material.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: March 17, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Mikhail Korolik, Nitin Ingle, Dimitri Kioussis
  • Patent number: 10570530
    Abstract: A periodic table Group 13 metal nitride crystals grown with a non-polar or semi-polar principal surface have numerous stacking faults. The purpose of the present invention is to provide a period table Group 13 metal nitride crystal wherein the occurrence of stacking faults of this kind are suppressed. The present invention achieves the foregoing by a periodic table Group 13 metal nitride crystal being characterized in that, in a Qx direction intensity profile that includes a maximum intensity and is derived from an isointensity contour plot obtained by x-ray reciprocal lattice mapping of (100) plane of the periodic table Group 13 metal nitride crystal, a Qx width at 1/300th of peak intensity is 6×10?4 rlu or less.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 25, 2020
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Yuuki Enatsu, Satoru Nagao, Shuichi Kubo, Hirotaka Ikeda, Kenji Fujito
  • Patent number: 10535663
    Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: January 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinwon Ma, Jun-Noh Lee, Dong-Hyun Im, Youngseok Kim, Kongsoo Lee