Abstract: A semiconductor device comprises a substrate that including a frontside comprising an active region and a backside opposite to the frontside, an electronic element on the active region, a frontside wiring structure electrically connected to the electronic element on the frontside of the substrate, and a backside wiring structure electrically connected to the electronic element on the backside of the substrate. The backside wiring structure includes a plurality of backside wiring patterns sequentially stacked on the backside of the substrate, and a super via pattern that intersects and extends through at least one layer of the plurality of backside wiring patterns.

Abstract: A thin-film transistor (TFT), includes: a substrate (202); an organic semiconductor (OSC) layer (210) positioned on the substrate; a dielectric layer (214) positioned on the OSC layer; and a polymeric interlayer (212) disposed in-between the OSC layer and the dielectric layer, such that the dielectric layer is configured to exhibit a double layer capacitance effect. A method of forming a thin-film transistor, includes: providing a substrate; providing a bottom gate layer atop the substrate; disposing consecutively from the substrate, an organic semiconductor (OSC) layer, a dielectric layer, and a top gate layer; and patterning the OSC layer, the dielectric layer, and the top gate layer using a single mask.

Abstract: A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.

Abstract: A method of manufacturing an image display device includes: providing a semiconductor growth substrate comprising a semiconductor layer; providing a circuit substrate comprising: a circuit element, a first wiring layer, and a first insulating film; forming a first metal layer that is located on the first insulating film and is electrically connected to the first wiring layer; bonding the semiconductor growth substrate to the circuit substrate and electrically connecting the first metal layer to the semiconductor layer; etching the semiconductor layer to form a light-emitting element; etching the first metal layer to form a plug electrically connected to the light-emitting element; forming a second insulating film covering the plug, the light-emitting element, and the first insulating film; removing a portion of the second insulating film to expose a light-emitting surface of the light-emitting element; and forming a second wiring layer electrically connected to the light-emitting surface.

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

Abstract: A method for manufacturing an image display device includes: providing a second substrate that includes a first substrate, and a semiconductor layer grown on the first substrate, the semiconductor layer including a light-emitting layer; providing a third substrate including: a circuit including a circuit element formed on a light-transmitting substrate, a first insulating film covering the circuit, and a conductive layer including a light-reflective part formed on the first insulating film; bonding the semiconductor layer to the third substrate; forming a light-emitting element from the semiconductor layer; forming a second insulating film covering the conductive layer, the light-emitting element, and the first insulating film; forming a via extending through the first and second insulating films; and electrically connecting the light-emitting element and the circuit element by the via.

Abstract: Apparatuses and methods are described for laser annealing of a qubit device using a plurality of optical beams. According to an embodiment, a method of tuning a qubit device can comprise generating an optical beam, splitting the optical beam in a plurality of optical beams, and annealing a Josephson junction of the qubit device by projecting the plurality of optical beams onto a region of the qubit device adjacent to the Josephson junction. The disclosed techniques can also be applied for annealing other types of electrical components of various microscale integrated circuit devices.

Abstract: A system and method for shaping a flexible circuit (FC) having a set of conductive traces disposed within a set of insulation layers and a shaped FC, each involve using a non-conductive tool defining complimentary first and second tool portions and a shape therebetween, the tool being configured to receive a portion of the FC therebetween the first and second tool portions, a set of conductive heating elements arranged substantially in parallel with each other and disposed within the first and second tool portions, and a power source configured to provide power to the conductive heating elements causing the conductive heating elements to generate heat energy to shape the FC portion without removing any of the FC portion.

Abstract: A light receiving device includes, on a substrate, a Si waveguide core provided in a dielectric layer, a first i-type waveguide clad, an i-type core layer, a second i-type waveguide clad, p-type layers disposed on one side of a side surface of a layered structure in a light waveguide direction, the layered structure including the first i-type waveguide clad, the i-type core layer, and the second i-type waveguide clad, n-type layers disposed on the other side, and an electrode on a surface of each of the n-type layers. A width of the Si waveguide core is set to be able to suppress absorption of light in a vicinity of an input edge of the i-type core layer.

Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. Spacings among adjacent peaks of the oscillating function change from wide to narrow with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.

Abstract: A semiconductor device structure is provided. The device includes a dielectric layer over a substrate. The substrate has a fin structure, and the dielectric layer has a trench exposing a portion of the fin structure. The includes a gate material layer in the trench. The gate material has a topmost surface that is highly planar.

Abstract: There is provided a passive electronic component that achieves proper recognition of a marker portion thereof that indicates a winding start position and a winding direction of a coil conductor as well as a posture and an orientation of the component. The passive electronic component is a laminated type electronic component and has an insulator portion, a terminal electrode electrically connected to a conductor portion provided inside the insulator portion and formed on a surface of the insulator portion, and a marker portion for indicating a winding start position and a winding direction of a conductor or a posture and an orientation of the component. The marker portion is disposed in a recessed portion on the surface of the insulator portion.

Abstract: A semiconductor structure comprises a semiconductor substrate including a first silicon substrate component having a first crystalline orientation and a second silicon substrate component over the first silicon substrate and having a second crystalline orientation different from the first crystalline orientation. The semiconductor substrate defines a trench extending through the second silicon substrate component and at least partially within the first silicon substrate component. A gallium nitride structure is disposed within the trench of the semiconductor substrate.

Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.

Abstract: A method for separating a portion from a sheet glass element having a thickness of at least 2 millimeters along an intended separation line that divides the sheet glass element into the portion and a remaining main part is provided. The method includes producing filamentary damages comprising sub-micrometer hollow channels in a volume of the glass sheet element adjacently aligned along the separation line; and heating and/or cooling the glass sheet element to cause expansion and/or contraction so that the portion detaches from the main part along the separation line. The portion and the remaining main part each remain intact as a whole. The step of producing the filamentary damages includes generating a plasma within the volume with laser pulses of an ultrashort pulse laser; and displacing points of incidence of the laser pulses over a surface of the glass sheet element along the separation line.

Abstract: A high electron mobility transistor (HEMT) is disclosed. The HEMT includes a substrate, a first epitaxial layer disposed on the substrate, a second epitaxial layer disposed on the first epitaxial layer, a third epitaxial layer disposed on the second epitaxial layer, and a gate disposed on the third epitaxial layer. An upper portion of the first epitaxial layer has a plurality of first recesses. The second epitaxial layer partially fills the first recesses and surrounding a plurality of first air slits in the first recesses.

Abstract: A thin film transistor (TFT) liquid crystal display (LCD) comprises a plurality of image pixels demarcated between an overlying liquid crystal display layer and an underlying glass substrate. Each image pixel comprises a dedicated top-gate TFT disposed over the glass substrate. Each top-gate thin film transistor comprises a process sensitive semiconductor layer disposed over the glass substrate, and a source electrode and a drain electrode disposed over the process sensitive semiconductor layer. The process sensitive semiconductor layer forms a process sensitive semiconductor active layer between the source electrode and the drain electrode and an active layer protection film is disposed over the process sensitive semiconductor active layer. A gate dielectric layer is disposed over the active layer protection film between the source electrode and the drain electrode and a gate electrode is disposed over the gate dielectric layer.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory opening fill structures vertically extending through the alternating stack. An insulating liner overlies stepped surfaces of the alternating stack in a staircase region. A plurality of discrete dielectric plates can be formed over the insulating liner. In one embodiment, the plurality of discrete dielectric plates can function as etch stop structures for formation of contact via structures that contact underlying portions of the electrically conductive layers. In another embodiment, the plurality of discrete dielectric plates may be replaced with a metallic material that forms extensions of the electrically conductive layers, and can be employed as etch stop structures during formation of contact via structures.

Abstract: Semiconductor nanowire devices having (111)-plane channel sidewalls and methods of fabricating semiconductor nanowire devices having (111)-plane channel sidewalls are described. For example, an integrated circuit structure includes a first semiconductor device including a plurality of vertically stacked nanowires disposed above a substrate, each of the nanowires comprising a discrete channel region having <111> lateral sidewalls along a <110> carrier transport direction. The integrated circuit structure also includes a second semiconductor device including a semiconductor fin disposed above the substrate, the semiconductor fin having a channel region with a top and side surfaces, the channel region having <111> lateral sidewalls along a <110> carrier transport direction.

Abstract: A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material; introducing dopants into a portion of the filling material; and applying a first thermal processing to the semiconductor body to spread the dopants in the filling material along a vertical direction of the filling material by a diffusion process. The vertical doping profile of the dopants within the doped filling material is shaped during the first thermal processing. Additionally, the dopants are substantially confined to within the trench and substantially do not diffuse from the doped filling material into the semiconductor body during the first thermal processing. A second thermal processing is applied to the semiconductor body after the first thermal processing to cause diffusion of the dopants from the doped filling material into the semiconductor body adjoining the trench.

Abstract: A method of producing gallium-doped zinc oxide films with enhanced conductivity. The method includes depositing a gallium-doped zinc oxide film on a substrate using a pulsed laser and subjecting the deposited gallium-dope zinc oxide film to a post-treatment effecting recrystallization in the deposited film, wherein the recrystallization enhances the conductivity of the film. Another method of producing gallium-doped zinc oxide films with enhanced conductivity. The method includes the steps of depositing a gallium-doped zinc oxide film on a substrate using a pulsed laser and subjecting the deposited gallium-dope zinc oxide film to an ultraviolet laser beam resulting in recrystallization in the film, wherein the recrystallization enhances the conductivity of the film. A film comprising gallium-doped zinc oxide wherein the film contains a recrystallized grain structure on its surface.

Abstract: The preparation method for a nano composite coating having a shell-simulated multi-arch structure includes: constructing a discontinuous metal seed layer using a vacuum plating technology; and inducing the deposition of a continuous multi-arch structure layer utilizing the discontinuous metal seed layer, thereby realizing the controllable orientated growth of the nano composite coating having the shell-simulated multi-arch structure.

Abstract: A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.

Abstract: A method of removing a phosphorus-doped silicon film doped with phosphorus, includes: forming a silicon oxide film by oxidizing the phosphorus-doped silicon film in a substrate including the phosphorus-doped silicon film and an undoped silicon film which is not been doped with the phosphorus, wherein at least the phosphorus-doped silicon film is exposed to a surface of the substrate; and selectively etching and removing the silicon oxide film from the silicon oxide film and the undoped silicon film.

Abstract: An additive manufacturing system includes at least two photoconductor plates attached to a substrate. Each photoconductor plate can include separate the Linear Electro layers and transparent conductive oxide layers.

Abstract: A display device includes: a substrate including a display region and a peripheral region, wherein the peripheral region is adjacent to the display region; a first transistor disposed on the peripheral region, wherein the first transistor includes a first semiconductor layer and the first semiconductor layer is a silicon semiconductor layer; and a second transistor disposed on the display region, wherein the second transistor includes a second semiconductor layer and the second semiconductor layer is an oxide semiconductor layer, wherein the first transistor is electrically connected to the second transistor.

Abstract: A semiconductor memory device comprises: a plurality of first conductive layers arranged separated from each other in a first direction; a plurality of second conductive layers arranged, electrically insulated from the plurality of first conductive layers, at a different position in a second direction intersecting the first direction with respect to the first conductive layers; a plurality of memory structures; and a source structure. Respective one ends of the plurality of memory structures and one end of the source structure are electrically connected. The respective other ends of the plurality of memory structures are respectively electrically connected to different first wirings of a plurality of first wirings formed in the same layer in the first direction. The other end of the source structure is electrically connected to a second wiring formed in a different layer from the plurality of first wirings in the first direction.

Abstract: Methods of synthesizing Bi2S3—CdS particles in the form of spheres as well as properties of these Bi2S3—CdS particles are described. Methods of photocatalytic degradation of organic pollutants employing these Bi2S3—CdS particles and methods of preventing or reducing microbial growth on a surface by applying these Bi2S3—CdS particles in the form of a solution or an antimicrobial product onto the surface are also specified.

Abstract: Techniques are disclosed for a hybrid undo/redo for text editing, where non-linear undo and redo operations are performed across dynamic regions in a document and linear undo and redo operations are performed within the dynamic regions in the document. In an example, the hybrid undo/redo may be achieved by maintaining respective region offset values for the dynamic regions created in a document by the edits made to the document. In operation, the respective region offset values associated with the dynamic regions can be used to negate or otherwise counteract the effect of edits made in the dynamic regions.

Abstract: A technique relates to a semiconductor device. A first epitaxial material is formed under a bottom surface of a set of fins, the first epitaxial material being under fin channel regions of the set of fins. A second epitaxial material is formed adjacent to the first epitaxial material and remote from the fin channel regions, a combination of the first epitaxial material and the second epitaxial material forming a bottom source or drain (source/drain) layer. A top source/drain layer is formed on an upper portion of the set of fins, gate material being disposed around the set of fins between the top source/drain layer and the bottom source/drain layer.

Abstract: A method of making a semiconductor arrangement includes forming a first layer of molecular ions in a first wafer interface region of a first wafer, forming a second layer of molecular ions in a second wafer interface region of a second wafer, forming a first molecular bond connecting the first wafer interface region to the second wafer interface region by applying pressure to at least one of the first wafer or the second wafer in a direction toward the first wafer interface region and the second wafer interface region, and annealing the first wafer and the second wafer to form a second molecular bond connecting the first wafer interface region to the second wafer interface region.

Abstract: Embodiments of the present application provide an array substrate, a fabrication method for an array substrate, and a display panel. The array substrate includes a substrate, a gate, a gate insulating layer, a seed layer, and a semiconductor layer that are sequentially stacked. A surface of the semiconductor layer away from the seed layer has a concave-convex structure formed by growth of nanocrystalline grains, which enhances light absorption of the semiconductor layer and solves the problems of poor light sensitivity and slow response speed of semiconductor devices.

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.

Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

Abstract: The invention discloses an optical system for generating arbitrary-order optical vortex arrays and finite optical lattices with defects, comprising a laser, a collimating and beam-expanding system, a spatial light modulator, a 4-f lens system, and an image detector which are disposed according to a light path. After passing through the collimating and beam-expanding system, the linearly-polarized Gaussian beam emitted by the laser is radiated to the spatial light modulator to be modulated in complex amplitude; the first-order diffraction beam of the emergent light generates an arbitrary-order alternating optical vortex array on the back focal plane of the first 2-f lens system, and an adjustable finite optical lattice with defects on the back focal plane of the second 2-f lens system. The topological charge value of each vortex and the spacing between vortices, in the generated arbitrary-order alternating optical vortex array, can be precisely controlled.

Abstract: A method of forming polysilicon comprises forming a first polysilicon-comprising material over a substrate, with the first polysilicon-comprising material comprising at least one of elemental carbon and elemental nitrogen at a total of 0.1 to 20 atomic percent. A second polysilicon-comprising material is formed over the first polysilicon-comprising material. The second polysilicon-comprising material comprises less, if any, total elemental carbon and elemental nitrogen than the first polysilicon-comprising material. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

Abstract: A projector includes a laser source, a light modulation element configured to modulate light emitted from the laser source in accordance with image information, and a light transmissive member disposed in a light path between the laser source and the light modulation element, and configured to transmit the light emitted from the laser source, wherein the laser source and the light modulation element are bonded to the light transmissive member, the laser source includes a substrate, and a laminated structure provided to the substrate, and having a light emitting layer configured to emit light, and the laminated structure constitutes a photonic crystal structure configured to confine the light emitted by the light emitting layer in an in-plane direction of the substrate, and emit the light emitted by the light emitting layer in a normal direction of the substrate.

Abstract: The yield of a separation process is improved. The mass productivity of a display device which is formed through a separation process is improved. A layer is formed over a substrate with use of a material including a resin or a resin precursor. Next, a resin layer is formed by performing heat treatment on the layer. Next, a layer to be separated is formed over the resin layer. Then, the layer to be separated and the substrate are separated from each other. The heat treatment is performed in an atmosphere containing oxygen or while supplying a gas containing oxygen.

Abstract: A film forming method includes: forming a laminated film, in which an interface layer, a bulk layer, and a surface layer are laminated in this order, on a base; and crystallizing the laminated film, wherein the bulk layer is formed of a film that is easier to crystallize than the interface layer in crystallizing the laminated film, and wherein the surface layer is formed of a film that is easier to crystallize than the bulk layer in crystallizing the laminated film.

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Abstract: Increasing transparency of one or more micro-displays. A method includes attaching a transparent cover to at least a portion of a semiconductor wafer. The at least a portion of the semiconductor wafer includes the one or more micro-displays. The one or more micro-displays include one or more active silicon areas. The method further includes, after the transparent cover has been attached to the at least a portion of the semiconductor wafer, removing silicon between one or more of the active silicon areas.

Abstract: A method and apparatus for reducing as-deposited and metastable defects relative to amorphous silicon (a-Si) thin films, its alloys and devices fabricated therefrom that include heating an earth shield positioned around a cathode in a parallel plate plasma chemical vapor deposition chamber to control a temperature of a showerhead in the deposition chamber in the range of 350° C. to 600° C. An anode in the deposition chamber is cooled to maintain a temperature in the range of 50° C. to 450° C. at the substrate that is positioned at the anode. In the apparatus, a heater is embedded within the earth shield and a cooling system is embedded within the anode.

Abstract: Embodiments of the present invention are directed to lightweight, portable spectrograph systems configured for applications in high-throughput crop phenotyping and plant health assessment, and associated methods.

Abstract: A method for forming a transfer gate includes (i) forming a dielectric pillar on a surface of a semiconductor substrate and (ii) growing an epitaxial layer on the semiconductor substrate and surrounding the dielectric pillar. The dielectric pillar has a pillar height that exceeds an epitaxial-layer height of the epitaxial layer relative to the surface. The method also includes removing the dielectric pillar to yield a trench in the epitaxial layer. A pixel includes a doped semiconductor substrate having a front surface opposite a back surface. The front surface forms a trench extending a depth zT with respect to the front surface within the doped semiconductor substrate along a direction z perpendicular to the front surface and the back surface. The pixel has a dopant concentration profile, a derivative thereof with respect to direction z being discontinuous at depth zT.

Abstract: A semiconductor device which has favorable electrical characteristics is provided. A method for manufacturing a semiconductor device with high productivity is provided. A method for manufacturing a semiconductor device with a high yield is provided.

Abstract: A portion of a buffer layer on a backside of a substrate of a photomask assembly may be removed prior to formation of one or more capping layers on the backside of the substrate. The one or more capping layers may be formed directly on the backside of the substrate where the buffer layer is removed from the substrate, and a hard mask layer may be formed directly on the one or more capping layers. The one or more capping layers may include a low-stress material to promote adhesion between the one or more capping layers and the substrate, and to reduce and/or minimize peeling and delamination of the capping layer(s) from the substrate. This may reduce the likelihood of damage to the pellicle layer and/or other components of the photomask assembly and/or may increase the yield of an exposure process in which the photomask assembly is used.

Abstract: The invention provides a bifacial photovoltaic cell comprising: a semiconductor substrate, the substrate comprising an n+ layer on a first surface, and a p+ layer on a second surface. The n+ layer comprises an n-dopant and the p+ layer comprises a p-dopant. The cell further comprises a passivating and/or antireflective coating on the doped first and second surfaces. The cell is characterized in that the second surface of the semiconductor substrate has an area substantially devoid of the p-dopant on an edge of the second surface having a width in the range of 0.1-0.5 mm; wherein the area is formed by etching the semiconductor substrate.

Abstract: A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.