On Insulating Substrate Or Layer Patents (Class 438/479)
  • Patent number: 10804166
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: October 10, 2019
    Date of Patent: October 13, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • Patent number: 10770616
    Abstract: Fabrication of a heterostructure, such as a group III nitride heterostructure, for use in an optoelectronic device is described. The heterostructure can be epitaxially grown on a sacrificial layer, which is located on a substrate structure. The sacrificial layer can be at least partially decomposed using a laser. The substrate structure can be completely removed from the heterostructure or remain attached thereto. One or more additional solutions for detaching the substrate structure from the heterostructure can be utilized. The heterostructure can undergo additional processing to form the optoelectronic device.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 8, 2020
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Alexander Dobrinsky, Maxim S. Shatalov
  • Patent number: 10741590
    Abstract: A peeling method at low cost with high mass productivity is provided. A silicon layer having a function of releasing hydrogen by irradiation with light is formed over a formation substrate, a first layer is formed using a photosensitive material over the silicon layer, an opening is formed in a portion of the first layer that overlaps with the silicon layer by a photolithography method and the first layer is heated to form a resin layer having an opening, a transistor including an oxide semiconductor in a channel formation region is formed over the resin layer, a conductive layer is formed to overlap with the opening of the resin layer and the silicon layer, the silicon layer is irradiated with light using a laser, and the transistor and the formation substrate are separated from each other.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: August 11, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masataka Sato, Masakatsu Ohno, Seiji Yasumoto, Hiroki Adachi
  • Patent number: 10672911
    Abstract: A thin film transistor array panel device comprises: a base substrate; a barrier layer disposed over the base substrate and comprising a plurality of transparent material layers; and an array of thin film transistors disposed over the barrier layer. A difference between a refractive index of the barrier layer and a refractive index of the base substrate may be within about 6%. The transparent material layers may be arranged such that the transparent material layers having compressive residual stress and the transparent material layers having tensile residual stress are alternately stacked. Each of the transparent material layers may comprise silicon oxynitride (SiON).
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seung Ho Jung, Chaun Gi Choi, Hye Young Park, Eun Young Lee, Joo Hee Jeon, Eun Jeong Cho, Bo Geon Jeon, Yung Bin Chung
  • Patent number: 10593553
    Abstract: Exemplary methods for etching a germanium-containing material may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a semiconductor processing chamber. The methods may include flowing effluents of the fluorine-containing precursor through apertures defined in a chamber component. The apertures may be coated with a catalytic material. The methods may include reducing a concentration of fluorine radicals in the plasma effluents with the catalytic material. The methods may also include delivering the plasma effluents to a processing region of the semiconductor processing chamber. A substrate having an exposed region of a germanium-containing material may be housed within the processing region. The methods may further include etching the germanium-containing material.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: March 17, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Mikhail Korolik, Nitin Ingle, Dimitri Kioussis
  • Patent number: 10570530
    Abstract: A periodic table Group 13 metal nitride crystals grown with a non-polar or semi-polar principal surface have numerous stacking faults. The purpose of the present invention is to provide a period table Group 13 metal nitride crystal wherein the occurrence of stacking faults of this kind are suppressed. The present invention achieves the foregoing by a periodic table Group 13 metal nitride crystal being characterized in that, in a Qx direction intensity profile that includes a maximum intensity and is derived from an isointensity contour plot obtained by x-ray reciprocal lattice mapping of (100) plane of the periodic table Group 13 metal nitride crystal, a Qx width at 1/300th of peak intensity is 6×10?4 rlu or less.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: February 25, 2020
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Yuuki Enatsu, Satoru Nagao, Shuichi Kubo, Hirotaka Ikeda, Kenji Fujito
  • Patent number: 10535663
    Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: January 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinwon Ma, Jun-Noh Lee, Dong-Hyun Im, Youngseok Kim, Kongsoo Lee
  • Patent number: 10522562
    Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: December 31, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwang Soo Kim, Shin Hwan Kang, Jae Hoon Jang, Kohji Kanamori
  • Patent number: 10319754
    Abstract: Certain electronic applications, such as OLED display back panels, require small islands of high-quality semiconductor material distributed over a large area. This area can exceed the areas of crystalline semiconductor wafers that can be fabricated using the traditional boule-based techniques. This specification provides a method of fabricating a crystalline island of an island material, the method comprising depositing particles of the island material abutting a substrate, heating the substrate and the particles of the island material to melt and fuse the particles to form a molten globule, and cooling the substrate and the molten globule to crystallize the molten globule, thereby securing the crystalline island of the island material to the substrate. The method can also be used to fabricate arrays of crystalline islands, distributed over a large area, potentially exceeding the areas of crystalline semiconductor wafers that can be fabricated using boule-based techniques.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: June 11, 2019
    Assignee: DIFTEK LASERS, INC.
    Inventor: Douglas R. Dykaar
  • Patent number: 10229857
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • Patent number: 10211210
    Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: February 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinwon Ma, Jun-Noh Lee, Dong-Hyun Im, Youngseok Kim, Kongsoo Lee
  • Patent number: 10186521
    Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending through the stacked body in a stacking direction of the stacked body, and a charge storage portion provided between the semiconductor body and the electrode layers. The semiconductor body includes a first semiconductor film, and a second semiconductor film provided between the first semiconductor film and the charge storage portion. An average grain size of a crystal of the second semiconductor film is larger than an average grain size of a crystal of the first semiconductor film.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: January 22, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Fukumoto, Fumiki Aiso, Hajime Nagano, Takuo Ohashi
  • Patent number: 10181398
    Abstract: A solution for fabricating a group III nitride heterostructure and/or a corresponding device is provided. The heterostructure can include a nucleation layer, which can be grown on a lattice mismatched substrate using a set of nucleation layer growth parameters. An aluminum nitride layer can be grown on the nucleation layer using a set of aluminum nitride layer growth parameters. The respective growth parameters can be configured to result in a target type and level of strain in the aluminum nitride layer that is conducive for growth of additional heterostructure layers resulting in strains and strain energies not exceeding threshold values which can cause relaxation and/or dislocation formation.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 15, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Wenhong Sun, Alexander Dobrinsky, Maxim S. Shatalov, Michael Shur, Remigijus Gaska
  • Patent number: 10079170
    Abstract: A high resistivity single crystal semiconductor handle structure for use in the manufacture of SOI structure is provided. The handle structure comprises an intermediate semiconductor layer between the handle substrate and the buried oxide layer. The intermediate semiconductor layer comprises a polycrystalline, amorphous, nanocrystalline, or monocrystalline structure and comprises a material selected from the group consisting of Si1-xGex, Si1-xCx, Si1-x-yGexSny, Si1-x-y-zGexSnyCz, Ge1-xSnx, group IIIA- nitrides, semiconductor oxides, and any combination thereof.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: September 18, 2018
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Srikanth Kommu, Gang Wang, Shawn George Thomas
  • Patent number: 10056253
    Abstract: Embodiments described herein include a method for forming a vertical hetero-stack and a device including a vertical hetero-stack. An example method is used to form a vertical hetero-stack of a first nanostructure and a second nanostructure arranged on an upper surface of the first nanostructure. The first nanostructure is formed by a first transition metal dichalcogenide, TMDC, material and the second nanostructure is formed by a second TMDC material. The example method includes providing the first nanostructure on a substrate. The method also includes forming a reactive layer of molecules on the first nanostructure along a periphery of the upper surface. The method further includes forming the second nanostructure by a vapor deposition process. The second TMDC material nucleates on the reactive layer of molecules along the periphery and grows laterally therefrom to form the second nanostructure on the upper surface.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: August 21, 2018
    Assignee: IMEC VZW
    Inventors: Annelies Delabie, Silvia Armini
  • Patent number: 10049945
    Abstract: The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and a tensile strained layer on the same wafer. A lower epitaxial layer may be formed adjacent to a tensile strained layer. An upper epitaxial layer may be formed over a portion of the lower epitaxial layer. Thermal oxidation may convert the upper epitaxial layer to an upper oxide layer, and thermal condensation may causes a portion of the lower epitaxial layer to become a compressive strained layer. The upper oxide layer and a remaining portion of the lower epitaxial layer may be removed, leaving the tensile strained layer and the compressive strained layer.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10043674
    Abstract: Exemplary methods for etching a germanium-containing material may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a semiconductor processing chamber. The methods may include flowing effluents of the fluorine-containing precursor through apertures defined in a chamber component. The apertures may be coated with a catalytic material. The methods may include reducing a concentration of fluorine radicals in the plasma effluents with the catalytic material. The methods may also include delivering the plasma effluents to a processing region of the semiconductor processing chamber. A substrate having an exposed region of a germanium-containing material may be housed within the processing region. The methods may further include etching the germanium-containing material.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: August 7, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Mikhail Korolik, Nitin Ingle, Dimitri Kioussis
  • Patent number: 9954037
    Abstract: The present disclosure discloses a display device, a method of manufacturing the same, a display method, and a wearable device. The display includes a first base substrate; a low-temperature polysilicon (LTPS) back plate formed on the first base substrate and provided with a switch control circuit; and a micro-electro-mechanical system (MEMS) microlens array formed at a non-display region of the first base substrate, wherein the MEMS microlens array is configured to reflect light emitted by a light-emitting structure at the display region, and the switch control circuit is configured to control the MEMS microlens array to be turned on and off; and the light-emitting structure formed at the display region of the first base substrate.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: April 24, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhidong Wang, Jing Yu, Yue Long
  • Patent number: 9929060
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • Patent number: 9887276
    Abstract: Disclosed is a method to manufacture a thin film transistor having an oxide semiconductor as a channel formation region. The method includes; forming an oxide semiconductor layer over a gate insulating layer; forming a source and drain electrode layers over and in contact with the oxide semiconductor layer so that at least portion of the oxide semiconductor layer is exposed; and forming an oxide insulating film over and in contact with the oxide semiconductor layer. The exposed portion of the oxide semiconductor may be exposed to a gas containing oxygen in the presence of plasma before the formation of the oxide insulating film. The method allows oxygen to be diffused into the oxide semiconductor layer, which contributes to the excellent characteristics of the thin film transistor.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: February 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Kenichi Okazaki, Hotaka Maruyama
  • Patent number: 9876101
    Abstract: A semiconductor substrate including a substrate, a buffer layer having a nitride-based semiconductor containing carbon provided on the substrate, a high-resistance layer having a nitride-based semiconductor containing carbon provided on the buffer layer, and a channel layer having a nitride-based semiconductor provided on the high-resistance layer, the high-resistance layer including a first region having carbon concentration lower than that of the buffer layer, and a second region which is provided between the first region and the channel layer, and has the carbon concentration higher than the first region.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: January 23, 2018
    Assignees: SANKEN ELECTRIC CO., LTD., SHIN-ETSU HANDOTAI CO., LTD
    Inventors: Ken Sato, Hiroshi Shikauchi, Hirokazu Goto, Masaru Shinomiya, Kazunori Hagimoto, Keitaro Tsuchiya
  • Patent number: 9876142
    Abstract: An optoelectronic device including a support having a first face; a first set of first light-emitting diodes having first wire-like, conical or frustoconical semiconductor elements, each resting on a second face of a first contact stud, each first contact stud including, in addition, a third face opposite the second face; and a first conductive layer connecting the first contact studs and extending at least over part of the second face or the third face of each first contact stud, the first conductive layer and/or the first contact studs resting on the support.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 23, 2018
    Assignee: Aledia
    Inventors: Christophe Bouvier, Erwan Dornel
  • Patent number: 9806084
    Abstract: A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: October 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Chengwen Pei, Geng Wang
  • Patent number: 9679776
    Abstract: A method for the selective implantation of a workpiece is disclosed. In place of conventional photoresist, a two layer structure is used. The first layer, referred to as the protective layer, is applied directly to the workpiece and protects the workpiece from harmful etching processes. Additionally, the protective layer has limited ability to stop ions from impacting the workpiece. The second layer, referred to as the blocking layer, which is formed on a portion of the protective layer, is used to block ions from impacting the underlying workpiece. Advantageously, the blocking layer may be selectively etched without affecting the protective layer. Additionally, the protective layer can be removed without affecting the underlying workpiece. Through the use of this two layer technique, high temperature selective implants may be performed on a variety of different semiconductor devices.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: June 13, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Andrew M. Waite, Naushad Variam
  • Patent number: 9659964
    Abstract: After forming a plurality of first semiconductor fins having a first spacing in a logic device region and a plurality of second semiconductor fins having a second spacing in a memory device region, sacrificial spacers are formed on sidewalls of the plurality of the first semiconductor fins and the plurality of the second semiconductor fins to completely fill spaces between the plurality of first semiconductor fins, but only partially fill spaces between second semiconductor fins. Next, dielectric barrier layer portions are formed in gaps between the sacrificial spacers. After removal of the sacrificial spacers, an entirety of the plurality of first semiconductor fins is laterally enclosed by a corresponding pair of neighboring dielectric barrier layers, while each of the plurality of second semiconductor fins is laterally enclosed by a corresponding pair of neighboring dielectric barrier layer portions.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: May 23, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz
  • Patent number: 9640537
    Abstract: A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: May 2, 2017
    Assignee: Intel Corporation
    Inventors: Niti Goel, Robert S. Chau, Jack T. Kavalieros, Benjamin Chu-Kung, Matthew V. Metz, Niloy Mukherjee, Nancy M. Zelick, Gilbert Dewey, Willy Rachmady, Marko Radosavljevic, Van H. Le, Ravi Pillarisetty, Sansaptak Dasgupta
  • Patent number: 9634044
    Abstract: Embodiments of the invention provides a method for fabricating an array substrate comprising: forming, on a substrate, at least two semiconductor active islands, first patterns positioned on both sides of each of the semiconductor active islands, second patterns positioned at outer side of a part of the first patterns, and third patterns positioned at outer side of the rest of the first patterns, through a single patterning process; doping a semiconductor at the second patterns for once to form a semiconductor of a first conductivity type; and doping a semiconductor at the third patterns for once to form a semiconductor of a second conductivity type.
    Type: Grant
    Filed: April 22, 2013
    Date of Patent: April 25, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Fangzhen Zhang
  • Patent number: 9620625
    Abstract: A method for manufacturing a submicron semiconductor structure on a substrate, including: forming at least one template layer over a support substrate; forming one or more template structures, including one or more recesses and/or mesas, in the template layer, the one or more template structures including one or more edges extending into or out of the top surface of the template layer; coating at least part of the one or more template structures with a liquid semiconductor precursor; and, annealing and/or exposing the liquid semiconductor precursor coated template structures to light, wherein during the annealing and/or light exposure a part of the liquid semiconductor precursor accumulates by capillary forces against at least part of the one or more edges, the annealing and/or light exposure transforming the accumulated liquid semiconductor precursor into a submicron semiconductor structure extending along at least part of the one or more edges.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: April 11, 2017
    Assignee: TECHNISCHE UNIVERSITEIT DELFT
    Inventors: Ryoichi Ishihara, Michiel Van Der Zwan, Miki Trifunovic
  • Patent number: 9559120
    Abstract: A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana
  • Patent number: 9530696
    Abstract: A method of fabricating a semiconductor device is provided. A plurality of sacrificial gates and a plurality of sacrificial gate dielectric layers thereunder are formed on a substrate. An interlayer dielectric layer is filled between the sacrificial gates. A protective layer is formed on the interlayer dielectric layer. The sacrificial gates and the sacrificial gate dielectric layers are removed to form an opening, wherein the interlayer dielectric layer is protected by the protective layer from recessing. A stacked gate structure is formed in the opening, wherein the protective layer is removed.
    Type: Grant
    Filed: October 23, 2015
    Date of Patent: December 27, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Wei-Hsin Liu, Fu-Yu Tsai, Bin-Siang Tsai, Wei-Lun Hsu, Shang-Yi Yang, Pi-Hsuan Lai
  • Patent number: 9515068
    Abstract: A compound semiconductor integrated circuit comprising a first substrate; a first electronic component formed on top of said first substrate; a layer of a first dielectric material formed on top of said first substrate and including said first electronic component, said layer of a first dielectric material comprising a recess exposing a first region of said first substrate; and a layer of a second dielectric material attached to said first substrate on top of said first region of said first substrate after manufacturing of said layer of a second dielectric material, said layer of a second material comprising a second electronic component.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: December 6, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Pamela R. Patterson, Keisuke Shinohara, Hasan Sharifi, Wonill Ha, Tahir Hussain, James Chingwei Li, Dana C. Wheeler
  • Patent number: 9494679
    Abstract: The invention relates to a radar-transparent component comprising a plastic body. Said component is characterized in that at least parts of the surface have a coating with a thickness of between 10 nm and 100 nm that comprises a semiconductor. Said coating gives the plastic body the desired metallic appearance without the body losing the characteristic of a radar-transparent component.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: November 15, 2016
    Assignee: OERLIKON SURFACE SOLUTIONS AG, PFAFFIKON
    Inventors: Antal Keckes, Peter Schuler, Carlos Ribeiro
  • Patent number: 9490330
    Abstract: Initiation conditions and strain techniques are described that enable forming high quality GaAsP semiconductor material on an SiGe semiconductor material with low threading defect density. Suitable initiation conditions include exposing the SiGe semiconductor material to a gas comprising arsenic. A tensilely-strained region may be formed in the semiconductor structure between regions of GaAsP semiconductor material and SiGe semiconductor material.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: November 8, 2016
    Assignee: Massachusetts Institute of Technology
    Inventors: Eugene A. Fitzgerald, Prithu Sharma, Timothy Milakovich
  • Patent number: 9478559
    Abstract: A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes: a memory cell structure formed over a semiconductor substrate; a channel portion formed in the semiconductor substrate; a through-hole formed to pass through the memory cell structure; a first channel region formed over sidewalls of the through-hole; and a second channel region formed at a center part of the through-hole, and spaced apart from the first channel region, wherein each of the first channel region and the second channel region is coupled to the channel portion.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: October 25, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jae Eun Jeon, Sung Lae Oh
  • Patent number: 9472621
    Abstract: A method of forming CMOS structures with selective tensile strained NFET fins and relaxed PFET fins includes performing a first, partial fin etch on a tensile strained silicon layer of a semiconductor substrate; selectively oxidizing bottom surfaces of the tensile strained silicon layer in a PFET region of the semiconductor substrate, thereby causing PFET silicon fins defined in the PFET region to become relaxed; and performing a second fin etch to define NFET silicon fins in an NFET region of the semiconductor substrate, wherein the NFET silicon fins remain tensile strained.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Hong He, Ali Khakifirooz, Joshua M. Rubin
  • Patent number: 9437428
    Abstract: To provide a method for manufacturing a semiconductor device including an oxide semiconductor film having conductivity, or a method for manufacturing a semiconductor device including an oxide semiconductor film having a light-transmitting property and conductivity. The method for manufacturing a semiconductor device includes the steps of forming an oxide semiconductor film over a first insulating film, performing first heat treatment in an atmosphere where oxygen contained in the oxide semiconductor film is released, and performing second heat treatment in a hydrogen-containing atmosphere, so that an oxide semiconductor film having conductivity is formed.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: September 6, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Oota, Noritaka Ishihara, Motoki Nakashima, Yoichi Kurosawa, Shunpei Yamazaki, Yasuharu Hosaka, Toshimitsu Obonai, Junichi Koezuka
  • Patent number: 9425322
    Abstract: A highly reliable semiconductor device having stable electric characteristics is provided by suppressing, in a transistor including an oxide semiconductor film, diffusion of indium into an insulating film in contact with the oxide semiconductor film and improving the characteristics of the interface between the oxide semiconductor film and the insulating film. In an oxide semiconductor film containing indium, the indium concentration at a surface is decreased, thereby preventing diffusion of indium into an insulating film on and in contact with the oxide semiconductor film. By decreasing the indium concentration at the surface of the oxide semiconductor film, a layer which does not substantially contain indium can be formed at the surface. By using this layer as part of the insulating film, the characteristics of the interface between the oxide semiconductor film and the insulating film in contact with the oxide semiconductor film are improved.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: August 23, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kosei Noda, Noriyoshi Suzuki
  • Patent number: 9397003
    Abstract: A method includes forming a first confined raised source/drain region between an adjacent pair of first dummy gate structures and a second confined raised source/drain region between an adjacent pair of second dummy gate structures during a same first epitaxial growth process, the first and second confined raised source/drain regions including a first semiconductor material. Thereafter, a replacement metal gate process is performed to replace the pairs of first and second dummy gate structures with respective pairs of first and second replacement gate structures. After the replacement metal gate process is performed, a first contact element is formed to the first confined raised source/drain region, a second epitaxial growth process is performed to form a layer of a second semiconductor material above the second confined raised source/drain region, and a second contact element is formed to the layer of second semiconductor material layer.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: July 19, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hiroaki Niimi, Ruilong Xie
  • Patent number: 9385222
    Abstract: A cavity is formed in a first semiconductor layer that is formed on a semiconducting base layer. The cavity extends from a process surface of the first semiconductor layer to the base layer. A recessed mask liner is formed on a portion of a sidewall of the cavity distant to the process surface or a mask plug is formed in a portion of the cavity distant do the process surface. A second semiconductor layer is grown by epitaxy on the process surface. The second semiconductor layer spans the cavity.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: July 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Hans-Joachim Schulze, Anton Mauder, Erich Griebl
  • Patent number: 9379262
    Abstract: A wafer with high rupture resistance includes a plurality of surfaces, wherein the surfaces include a largest surface having a largest area than others and a side surface connected to the fringe of the largest surface. The side surface forms a nanostructured layer thereon to assist the stress dispersion of the wafer. Accordingly, the wafer is provided with a high rupture resistance so as to prevent the wafer from damages during semiconductor or other processes.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: June 28, 2016
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventor: Jer-Liang Yeh
  • Patent number: 9362379
    Abstract: A field effect transistor includes a substrate, a first graphene (Gr) layer on the substrate, a second graphene (Gr) layer on the substrate, a fluorographene (GrF) layer on the substrate and between the first and second graphene layers, a first ohmic contact on the first graphene layer, a second ohmic contact on the second graphene layer, a gate aligned over the fluorographene layer, and a gate dielectric between the gate and the fluorographene layer and between the gate and the first and second ohmic contacts.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: June 7, 2016
    Assignee: HRL Laboratories, LLC
    Inventor: Jeong-Sun Moon
  • Patent number: 9356128
    Abstract: A semiconductor power device, comprising: a substrate; a first semiconductor layer with a first lattice constant formed on the substrate; a first grading layer formed on the first semiconductor layer and comprising a first portion; a second grading layer formed on the first grading layer; a second semiconductor layer with a second lattice constant formed on the second grading layer; a first interlayer formed in the first grading layer and adjacent to the first portion of the first grading layer; and a second interlayer formed in the second grading layer; wherein the first interlayer comprises a first superlattice including a series of Alx1Ga1-x1N/Aly1Ga1-y1N alternate layers, (x1-y1)?0.2, and the second interlayer comprises a second superlattice including a series of Alx2Ga1-x2N/Aly2Ga1-y2N alternate layers, (x2-y2)?0.2, wherein the average of x1 and y1 is larger than that of x2 and y2.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: May 31, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Heng-Kuang Lin, Yih-Ting Kuo, Tsung-Cheng Chang
  • Patent number: 9355840
    Abstract: A method of producing a template material for growing semiconductor materials and/or devices, comprises the steps of: (a) providing a substrate with a dielectric layer on the substrate; and (b) forming a pixelated pattern on the dielectric layer, the pattern comprising a plurality of discrete groups of structures.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: May 31, 2016
    Assignee: NANOGAN LIMITED
    Inventor: Wang Nang Wang
  • Patent number: 9343343
    Abstract: A method for transporting a substrate using an end effector which mechanically clamps a periphery of the substrate includes: before transporting the substrate, depositing a compressive film only on, at, or in a bevel portion of the substrate; and transporting the substrate whose bevel portion is covered by the compressive film as the outermost film, using an end effector while mechanically clamping the periphery of the substrate.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: May 17, 2016
    Assignee: ASM IP Holding B.V.
    Inventor: Yukihiro Mori
  • Patent number: 9318866
    Abstract: A plasmonic laser device has resonant nanocavities filled with a gain medium containing an organic dye. The resonant plasmon frequencies of the nanocavities are tuned to align with both the absorption and emission spectra of the dye. Variables in the system include the nature of the dye and the wavelength of its absorption and emission, the wavelength of the pumping radiation, and the resonance frequencies of the nanocavities. In addition the pumping frequency of the dye is selected to be close to the absorption maximum.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: April 19, 2016
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Mihail Bora, Tiziana C. Bond
  • Patent number: 9276132
    Abstract: A nonvolatile memory device includes an insulating pattern extending in a first direction, a conductive pattern on the insulating pattern, and an electrode structure extending in the first direction. The electrode structure is adjacent the insulating pattern and conductive pattern, and includes an alternating pattern of gate electrodes and interlayer insulating films. A protection film adjacent a side surface of the electrode structure has a shorter length in the first direction than a length of the electrode structure.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: March 1, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woo-Sung Lee, Kyong-Won An
  • Patent number: 9269820
    Abstract: A manufacturing method of a polysilicon layer and a manufacturing method of a polysilicon thin film transistor. The manufacturing method of the polysilicon layer includes: providing a substrate; forming a barrier layer and a buffer layer on the substrate; disposing a plurality of grooves in the buffer layer by a patterning process, and forming crystal seeds on the buffer layer; forming an amorphous silicon layer on the buffer layer provided with the grooves and on the crystal seeds; transferring the amorphous silicon layer into a polysilicon layer using a thermal treatment process.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: February 23, 2016
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zuqiang Wang
  • Patent number: 9263512
    Abstract: A method including forming an oxide layer on a top of a substrate; forming a deep trench capacitor in the substrate; bonding a III-V compound semiconductor to a top surface of the oxide layer; and forming a III-V device in the III-V compound semiconductor.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Effendi Leobandung
  • Patent number: 9249012
    Abstract: A method for fabricating an integrated MEMS device and the resulting structure therefore. A control process monitor comprising a MEMS membrane cover can be provided within an integrated CMOS-MEMS package to monitor package leaking or outgassing. The MEMS membrane cover can separate an upper cavity region subject to leaking from a lower cavity subject to outgassing. Differential changes in pressure between these cavities can be detecting by monitoring the deflection of the membrane cover via a plurality of displacement sensors. An integrated MEMS device can be fabricated with a first and second MEMS device configured with a first and second MEMS cavity, respectively. The separate cavities can be formed via etching a capping structure to configure each cavity with a separate cavity volume. By utilizing an outgassing characteristic of a CMOS layer within the integrated MEMS device, the first and second MEMS cavities can be configured with different cavity pressures.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: February 2, 2016
    Assignee: mCube, Inc.
    Inventor: Te-Hsi “Terrence” Lee
  • Patent number: 9246005
    Abstract: Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: January 26, 2016
    Assignees: International Business Machines Corporation, KABUSHIKI KAISHA TOSHIBA
    Inventors: Veeraraghavan S. Basker, Akira Hokazono, Hiroshi Itokawa, Tenko Yamashita, Chun-chen Yeh