Abstract: A nitride-based group III-V semiconductor substrate has an as-grown surface on the surface thereof; and a flat surface on the back surface of the substrate. The c-axis of a nitride-based group III-V semiconductor crystal composing the substrate is substantially perpendicular to the surface of the substrate or inclined at a predetermined angle to the surface of the substrate.

Abstract: A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. Also, a transistor source/drain region 80, 90 having a SiGe source/drain extension 90 that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.

Abstract: A fabrication method of a semiconductor luminescent device includes forming a compound semiconductor layer having a structure in which a first conductivity-type clad layer, an active layer, a second conductivity-type clad layer are layered in order on a substrate, the second conductivity-type being different from the first conductivity-type and forming a low-refractive-index region in a waveguide in an area to be an end face from which an output light from the waveguide in the compound semiconductor layer is emitted, the low-refractive-index region having an equivalent refractive-index lower than that of another area in the waveguide. The step of forming the low-refractive-index region includes determining a width of the low-refractive-index region in a longitudinal direction of the waveguide so that an emission angle of the output light of the semiconductor luminescent device is controlled to be a desirable value, and forming the low-refractive-index region having the width.

Abstract: A method of fabricating a plurality of freestanding GaN wafers includes mounting a GaN substrate in a reactor, forming a GaN crystal growth layer on the GaN substrate through crystal growth, performing surface processing of the GaN crystal growth layer to form a GaN porous layer having a predetermined thickness on the GaN crystal growth layer, repeating the forming of the GaN crystal growth layer and the forming of the GaN porous layer a plurality of times to form a stack of alternating GaN crystal growth layers and GaN porous layers on the GaN substrate, and cooling the stack such that the GaN layers self-separate to form the freestanding GaN wafers. The entire process of forming a GaN porous layer and a thick GaN layer is performed in-situ in a single reactor. The method is very simplified compared to the prior art. In this way, the entire process is performed in one chamber, and in particular, GaN surface processing and growth proceed using an HVPE process gas such that costs are greatly reduced.

Abstract: Growth of multilayer films is carried out in a manner which allows close control of the strain in the grown layers and complete release of the grown films to allow mounting of the released multilayer structures on selected substrates. A layer of material, such as silicon-germanium, is grown onto a template layer, such as silicon, of a substrate having a sacrificial layer on which the template layer is formed. The grown layer has a lattice mismatch with the template layer so that it is strained as deposited. A top layer of crystalline material, such as silicon, is grown on the alloy layer to form a multilayer structure with the grown layer and the template layer. The sacrificial layer is preferentially etched away to release the multilayer structure from the sacrificial layer, relaxing the grown layer and straining the crystalline layers interfaced with it.

Abstract: A semiconductor structure, comprising: a substrate; a first aluminum nitride (AlN) layer having an aluminum/reactive nitride (Al/N) flux ratio less than 1 disposed on the substrate; and a second AlN layer having an Al/reactive N flux ratio greater than 1 disposed on the first AlN layer. The substrate is a compound of silicon wherein the first AlN layer is substantially free of silicon.

Abstract: In order to reduce dislocation pile-ups in a virtual substrate, a buffer layer 32 is provided, between an underlying Si substrate 34 and an uppermost constant composition SiGe layer 36, which comprises alternating graded SiGe layers 38 and uniform SiGe layers 40. During the deposition of each of the graded SiGe layers 38 the Ge fraction x is linearly increased from a value corresponding to the Ge composition ratio of the preceding layer to a value corresponding to the Ge composition ratio of the following layer. Furthermore the Ge fraction x is maintained constant during deposition of each uniform SiGe layer 40, so that the Ge fraction x varies in step-wise fashion through the depth of the buffer layer. After the deposition of each pair of graded and uniform SiGe layers 38 and 40, the wafer is annealed at an elevated temperature greater than the temperature at which the layers have been deposited.

Abstract: A high temperature non-aqueous synthetic procedure for the preparation of substantially monodisperse IV-VI semiconductor nanoparticles is provided. The procedure includes introducing a first precursor selected from the group consisting of a molecular precursor of a Group IV element and a molecular precursor of a Group VI element into a reaction vessel that comprises at least an organic solvent to form a mixture. Next, the mixture is heated and thereafter a second precursor of a molecular precursor of a Group IV element or a molecular precursor of a Group VI element that is different from the first is added. The reaction mixture is then mixed to initiate nucleation of IV-VI nanocrystals and the temperature of the reaction mixture is controlled to provide nanoparticles having a diameter of about 20 nm or less.

Abstract: Nitride-based film is grown using multiple precursor fluxes. Each precursor flux is pulsed one or more times to add a desired element to the nitride-based film at a desired time. The quantity, duration, timing, and/or shape of the pulses is customized for each element to assist in generating a high quality nitride-based film.

Abstract: A doping method for forming quantum dots is disclosed, which includes following steps: providing a first precursor solution for a group II element and a second precursor solution for a group VI element; heating and mixing the first precursor solution and the second precursor solution for forming a plurality of II–VI compound cores of the quantum dots dispersing in a melting mixed solution; and injecting a third precursor solution for a group VI element and a forth precursor solution with at least one dopant to the mixed solution in turn at a fixed time interval in order to form quantum dots with multi-shell dopant; wherein the dopant described here is selected from a group consisting of transitional metal and halogen elements. This method of the invention can dope the dopants in the inner quantum dot and enhance the emission intensity efficiently.

Abstract: A method for controlling dislocation position in a silicon germanium buffer layer located on a substrate includes depositing a strained silicon germanium layer on the substrate and irradiating one or more regions of the silicon germanium layer with a dislocation inducing agent. The dislocation inducing agent may include ions, electrons, or other radiation source. Dislocations in the silicon germanium layer are located in one or more of the regions. The substrate and strained silicon germanium layer may then be subjected to an annealing process to transform the strained silicon germanium layer into a relaxed state. A top layer of strained silicon or silicon germanium may be deposited on the relaxed silicon germanium layer. Semiconductor-based devices may then be fabricated in the non-damaged regions of the strained silicon or silicon germanium layer. Threading dislocations are confined to damaged areas which may be transformed into SiO2 isolation regions.

Abstract: A structure and method for making includes adjacent pMOSFET and nMOSFET devices in which the gate stacks are each overlain by a stressing layer that provides compressive stress in the channel of the PMOSFET device and tensile stress in the channel of the nMOSFET device. One of the PMOSFET or nMOSFET device has a height shorter than that of the other adjacent device, and the shorter of the two devices is delineated by a discontinuity or opening in the stressing layer overlying the shorter device. In a preferred method for forming the devices a single stressing layer is formed over gate stacks having different heights to form a first type stress in the substrate under the gate stacks, and forming an opening in the stressing layer at a distance from the shorter gate stack so that a second type stress is formed under the shorter gate stack.

Abstract: In a method of manufacturing a silicon carbide substance, such as a film, a layer, a semiconductor, which is doped with an impurity, a carbonization process is executed after formation of a doped silicon substance which is obtained by carrying out a silicon deposition process and by a doping process of the impurity. Both the silicon deposition and the doping processes may be simultaneously or separately carried out prior to the carbonization process or may be continued during the carbonization process also. At any rate, the carbonization process is intermittently carried out. A unit process of composed of a combination of the silicon deposition process, the doping process, and the carbonization process may be repeated a plurality times, for example, 2000 times.

Abstract: On a processed substrate having an engraved region as a depressed portion formed thereon, a nitride semiconductor thin film is laid. The sectional area occupied by the nitride semiconductor thin film filling the depressed portion is 0.8 times the sectional area of the depressed portion or less.

Abstract: Commercially viable methods of manufacturing p-type group II–VI semiconductor materials are disclosed. A thin film of group II–VI semiconductor atoms is deposited on a self supporting substrate surface. The semiconductor material includes atoms of group II elements, group VI elements, and one or more p-type dopants. The semiconductor material may be deposited on the substrate surface under deposition conditions in which the group II atoms, group VI atoms, and p-type dopant atoms are in a gaseous phase prior to combining as the thin film. Alternatively, a liquid deposition process may be used to deposit the group II atoms, group VI atoms, and p-type dopant atoms in a predetermined orientation to result in the fabrication of the group II–VI semiconductor material. The resulting semiconductor thin film is a persistent p-type semiconductor, and the p-type dopant concentration is greater than about 1016 atoms·cm?3. The semiconductor resistivity is less than about 0.5 ohm·cm.

Abstract: A method of fabricating a compound semiconductor layer has steps of forming a first layer made of an oxidizable material on a substrate, forming a second layer made of a compound semiconductor on the first layer, oxidizing the first layer made of the oxidizable material to an oxide layer and forming a third layer made of compound semiconductor that constitutes a semiconductor element on the second layer.

Abstract: A method for fabricating a short channel field-effect transistor is presented. A sublithographic gate sacrificial layer is formed, as are spacers at the side walls of the gate sacrificial layer. The gate sacrificial layer is removed to form a gate recess and a gate dielectric and a control layer are formed in the gate recess. The result is a short channel field-effect transistor with minimal fluctuations in the critical dimensions in a range below 100 nanometers.

Abstract: A method of forming a high germanium concentration, low defect density silicon germanium film and its associated structures is described, comprising forming a dielectric layer on a substrate, patterning the dielectric layer to form a silicon region and at least one dielectric region, and forming a low defect silicon germanium layer on at least one dielectric region.

Abstract: The vertical diffusion of dopants from the gate into the channel region, and the lateral diffusion of dopants from the source and drain regions into the channel region resulting from thermal cycling during the fabrication of a MOS transistor is minimized by forming the source and drain regions in a layer of silicon germanium carbon.

Abstract: A method of forming a substantially relaxed SiGe-on-insulator substrate in which the consumption of the sidewalls of SiGe-containing island structures during a high temperature relaxation annealing is substantially prevented or eliminated is provided. The method serves to maintain the original lateral dimensions of the patterned SiGe-containing islands, while providing a uniform and homogeneous Ge fraction of the islands that is independent of each island size. The method includes forming an oxidation mask on at least sidewalls of a SiGe-containing island structure that is located on a barrier layer that is resistant to Ge diffusion. A heating step is then employed to cause at least relaxation within the SiGe-containing island structure. The presence of the oxidation mask substantially prevents consumption of at least the sidewalls of the SiGe-containing island structure during the heating step.

Abstract: A method of forming a relaxed silicon-germanium layer for accommodation of an overlying silicon layer formed with tensile strain, has been developed. The method features growth of multiple composite layers on a semiconductor substrate, with each composite layer comprised of an underlying silicon-germanium-carbon layer and of an overlying silicon-germanium layer, followed by the growth of an overlying thicker silicon-germanium layer. A hydrogen anneal procedure performed after growth of the multiple composite layers and of the thicker silicon-germanium layer, results in a top composite layer now comprised with an overlying relaxed silicon-germanium layer, exhibiting a low dislocation density.

Abstract: This invention provides a method of depositing high-quality Si or SiGe epitaxial layers on SiGe substrates. By first depositing a thin Si seed layer on the SiGe substrate, the quality of the seed layer and of the subsequently deposited layers is greatly improved over what is obtained from depositing SiGe directly onto the SiGe substrate. Indeed, whereas the RMS surface roughness of the deposition of SiGe directly on SiGe, as measured by atomic-force microscopy (AFM), was 3–4 nm, it was more than an order of magnitude better when a thin Si seed layer was employed. This work was performed on an ultra-high-vacuum chemical vapor deposition (UHV/CVD) system; however, the same method would apply to other deposition systems such as atmospheric-pressure, low-pressure and rapid-thermal CVD.

Abstract: An apparatus is directed to increasing the resolution of digital color imaging that includes a photosensing semiconductor structure. The apparatus provides a monocrystalline silicon substrate, a first buffer layer epitaxially formed and overlying the monocrystalline silicon substrate, and a first photodiode layer overlying the first buffer layer and operable to provide a first signal indicative of a color associated with a first wavelength of light. The apparatus may further provide a second buffer layer overlying the first photodiode layer and a second photodiode layer overlying the second buffer layer operable to provide a second signal indicative of a color associated with a second wavelength of light.

Abstract: One method includes epitaxially growing a layer of group III-nitride semiconductor under growth conditions that cause a growth surface to be rough. The method also includes performing an epitaxial growth of a second layer of group III-nitride semiconductor on the first layer under growth conditions that cause the growth surface to become smooth. The two-step growth produces a lower density of threading defects.

Abstract: A method of forming a relaxed silicon—germanium layer for use as an underlying layer for a subsequent overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon—germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon—germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon—germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon—germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon—germanium layer progresses.

Abstract: Disclosed herein are (1) a light-emitting semiconductor device that uses a gallium nitride compound semiconductor (AlxGa1?xN) in which the n-layer of n-type gallium nitride compound semiconductor (AlxGa1?xN) is of double-layer structure including an n-layer of low carrier concentration and an n+-layer of high carrier concentration, the former being adjacent to the i-layer of insulating gallium nitride compound semiconductor (AlxGa1?xN); (2) a light-emitting semiconductor device of similar structure as above in which the i-layer is of double-layer structure including an iL-layer of low impurity concentration containing p-type impurities in comparatively low concentration and an iH-layer of high impurity concentration containing p-type impurities in comparatively high concentration, the former being adjacent to the n-layer; (3) a light-emitting semiconductor device having both of the above-mentioned features and (4) a method of producing a layer of an n-type gallium nitride compound semiconductor (AlxGa1?xN) ha

Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/post. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, from a top surface of the post and a sidewall/sidewalls of the trench serving as a nucleus for epitaxial growth, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. As a result, a region having less threading dislocations is formed at the buried trench.

Abstract: A sample stand is set in a chamber provided with an observation window on its upper surface and a heater for heating a sample is provided in the vicinity of the sample stand. Then, a microscope, a camera and a television monitor are connected and mounted outside the observation window of the chamber. The microscope is mounted such that a specific layer of the sample is focused on and can be observed. According to a manufacturing method of the preset invention, oxidation treatment is performed in such equipment while an oxidation process of the specific layer (semiconductor layer for selective oxidation) of the sample is observed.

Abstract: The invention relates to a device comprising a process chamber which is arranged in a reaction housing and which can be heated especially by supplying heat to a substrate holder, comprising a gas inlet for the admission of gaseous starting material, whereby the decomposition products thereof are deposited on a substrate maintained by a substrate holder to form a layer, also comprising at least one sensor acting upon the inside of the process chamber for determining layer properties further comprising an electronic control unit for controlling the heating of the process chamber, mass controllers for controlling the flow of the starting materials and a pump for controlling the pressure of the process chamber, characterized in that the electronic control unit forms modified process parameters from deviation values obtained upon growth of the calibrating layer with the aid of stored calibrating parameters, thereby controlling the heating of the process chamber, the flow controllers and the pump upon growth of the

Abstract: A wide-slit lateral growth projection mask, projection system, and corresponding crystallization process are provided. The mask includes an opaque region with at least one a transparent slit in the opaque region. The slit has a width in the range of 10X to 50X micrometers, with respect to a X:1 demagnification system, and a triangular-shaped slit end. The triangular-shaped slit end has a triangle height and an aspect ratio in the range of 0.5 to 5. The aspect ratio is defined as triangle height/slit width. In some aspects, the triangular-shaped slit end includes one or more opaque blocking features. In another aspect, the triangular-shaped slit end has stepped-shaped sides. The overall effect of the mask is to promote uniformly oriented grain boundaries, even in the film areas annealed under the slit ends.

Abstract: A photodetector device includes a plurality of Ge epilayers that are grown on a substrate and annealed in a defined temperature range. The Ge epilayers form a tensile strained Ge layer that allows the photodetector device to operate efficiently in the C-band and L-band.

Abstract: A low defect density (Ga,Al,In)N material. The (Ga, Al, In)N material may be of large area, crack-free character, having a defect density as low as 3×106 defects/cm2 or lower. Such (Ga,Al,In)N material is useful as a substrate for epitaxial growth of Group III-V nitride device structures thereon.

Abstract: When a p-type MgxZn1-xO-type layer is grown based on a metal organic vapor-phase epitaxy process, the p-type MgxZn1-xO-type layer is annealed in an oxygen-containing atmosphere during and/or after completion of the growth of the p-type MgxZn1-xO-type layer. In addition, a vapor-phase epitaxy process of a semiconductor layer is proceed while irradiating ultraviolet light to the surface of a substrate to be grown and source gasses. In addition, when a MgxZn1-xO-type buffer layer that is oriented so as to align the c-axis thereof to a thickness-wise direction is formed by an atomic layer epitaxy process, a metal monoatomic layer is grown at first. In addition, a ZnO-base semiconductor active layer is formed by using a semiconductor material mainly composed of ZnO containing Se or Te. A light emitting device is formed by using these techniques.

Abstract: According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors.

Abstract: A semiconductor device includes a single crystal substrate and a dielectric layer overlying the substrate. The dielectric layer includes at least one opening having a first portion and an overlying second portion. The first portion has a depth and width, such that an aspect ratio of the depth to width is greater than one. The semiconductor device further includes a first material having a first portion and a second portion, the first portion of the first material filling the first portion of the at least one opening. Defects for relaxing strain at an interface between the first material and the substrate material exist only within the first portion of the first material due to the aspect ratio being greater than one. The second portion of the first material is substantially defect free. Furthermore, the second portion of the first material and an overlying second material different than the first material fill the overlying second portion of the at least one opening.

Abstract: A method of forming a light emitting device includes providing a sapphire substrate, growing an Al1?xGaxN first layer by vapor deposition on the substrate at a temperature between about 1000° C. and about 1180° C., and growing a III-nitride second layer overlying the first layer. The first layer may have a thickness between about 500 angstroms and about 5000 angstroms. In some embodiments, reaction between the group V precursor and the substrate is reduced by starting with a low molar ratio of group V precursor to group III precursor, then increasing the ratio during growth of the first layer, or by using nitrogen as an ambient gas.

Abstract: An Al0.15Ga0.85N layer 2 is formed on a silicon substrate 1 in a striped or grid pattern. A GaN layer 3 is formed in regions A where the substrate 1 is exposed and in regions B which are defined above the layer 2. At this time, the GaN layer grows epitaxially and three-dimensionally (not only in a vertical direction but also in a lateral direction) on the Al0.15Ga0.85N layer 2. Since the GaN layer grows epitaxially in the lateral direction as well, a GaN compound semiconductor having a greatly reduced number of dislocations is obtained in lateral growth regions (regions A where the substrate 1 is exposed).

Abstract: A method for manufacturing a semiconductor thin film having high carrier mobility, and a magnetoelectric conversion element provided with the semiconductor thin film manufactured by the aforementioned method are provided. The temperature of the Si single crystal substrate is raised to 270° C. to 320° C., and an In buffer layer is formed by an electron beam heating type vacuum evaporation method. Subsequently, an initial seed layer made of Sb and In is formed. The temperature of the Si single crystal substrate is raised to 460° C. to 480° C., and thereafter, a retention time approximated by a predetermined function of the temperature of the Si single crystal substrate is provided. Then, a main growth layer made of Sb and In is formed.

Abstract: In a method for fabricating a nitride-based semiconductor laser which forms, by a selective deposition, a current narrowing structure and a structure confining a light in a horizontal direction in parallel to a substrate, when the nitride-based semiconductor is selectively deposited by a metal organic chemical vapor deposition, silicon generated by decomposition of the silicon oxide film used as the mask for the selective deposition is prevented from being deposited on a re-growth boundary. For this purpose, a silicon nitride film is used as the mask for the selective deposition, and when the nitride-based semiconductor is selectively deposited by the metal organic chemical vapor deposition, a V-group material of the nitride-based semiconductor, namely, a nitrogen material, for example, ammonia, is supplied so that the decomposition of the silicon nitride film used as the mask for the selective deposition, is prevented.

Abstract: A method and system for growing a layer of semiconductor material is disclosed. The method can be used to grow a layer of a semiconducting material comprising at least one Group III element, nitrogen and at least one other Group V element as constituent elements thereof, the method comprising providing a reactor and supplying precursors to the reactor. The precursors include a precursor for each of the at least one Group III element, a precursor for the nitrogen, a precursor for each of the at least one Group V element other than nitrogen, and a precursor for an element having a stronger bond strength with nitrogen than each of the at least one Group III element has with nitrogen. The method can be implemented in, for example, a metal organic chemical vapor deposition (MOCVD) reactor.

Abstract: An opaque, low resistivity silicon carbide and a method of making the opaque, low resistivity silicon carbide. The opaque, low resistivity silicon carbide is a free-standing bulk material that may be machined to form furniture used for holding semi-conductor wafers during processing of the wafers. The opaque, low resistivity silicon carbide is opaque at wavelengths of light where semi-conductor wafers are processed. Such opaqueness provides for improved semi-conductor wafer manufacturing. Edge rings fashioned from the opaque, low resistivity silicon carbide can be employed in RTP chambers.

Abstract: The method of fabricating a nitride semiconductor device of this invention includes plural steps of respectively growing plural nitride semiconductor layers on a substrate; and between a step of growing one nitride semiconductor layer and a step of growing another nitride semiconductor layer adjacent to the one nitride semiconductor layer among the plural steps, a step of changing a growth ambient pressure from a first growth ambient pressure to a second growth ambient pressure different from the first growth ambient pressure.

Abstract: A method for fabricating a III-V Group compound semiconductor comprising a step of epitaxially growing on an AlxGa1-xAs layer of lower Al content an AlxGa1-xAs layer of higher Al content, in which step a growth rate of the AlxGa1-xAs layer of higher Al content is made slower than a growth rate of the AlxGa1-xAs layer of lower Al content, thereby effectively inhibiting the occurrence of starting points of abnormal growth at the interface between the two layers.

Abstract: A substrate includes non-gallium nitride posts that define trenches therebetween, wherein the non-gallium nitride posts include non-gallium nitride sidewalls and non-gallium nitride tops and the trenches include non-gallium floors. Gallium nitride is grown on the non-gallium nitride posts, including on the non-gallium nitride tops. Preferably, gallium nitride pyramids are grown on the non-gallium nitride tops and gallium nitride then is grown on the gallium nitride pyramids. The gallium nitride pyramids preferably are grown at a first temperature and the gallium nitride preferably is grown on the pyramids at a second temperature that is higher than the first temperature. The first temperature preferably is about 1000° C. or less and the second temperature preferably is about 1100° C. or more. However, other than temperature, the same processing conditions preferably are used for both growth steps. The grown gallium nitride on the pyramids preferably coalesces to form a continuous gallium nitride layer.

Abstract: A nitride semiconductor substrate including (a) a supporting substrate, (b) a first nitride semiconductor layer having a periodical T-shaped cross-section, having grown from periodically arranged stripe-like, grid-like or island-like portions on the supporting substrate, and (c) a second nitride semiconductor substrate covering said supporting substrate, having grown from the top and side surfaces of said first nitride semiconductor layer, wherein a cavity is formed under the second nitride semiconductor layer. A protective layer having a periodically arranged stripe-like, grid-like or island-like apertures is formed on the supporting substrate. The first nitride semiconductor layer is laterally grown from the exposed portion of the substrate. The growth is stopped before the first nitride semiconductor layer covers the supporting substrate. Thus, the first nitride semiconductor layer has a periodical T-shaped cross-section.

Abstract: Disclosed herein are (1) a light-emitting semiconductor device that uses a gallium nitride compound semiconductor (AlxGa1−xN) in which the n-layer of n-type gallium nitride compound semiconductor (AlxGa1−xN) is of double-layer structure including an n-layer of low carrier concentration and an n+-layer of high carrier concentration, the former being adjacent to the i-layer of insulating gallium nitride compound semiconductor (AlxGa1−xN); (2) a light-emitting semiconductor device of similar structure as above in which the i-layer is of double-layer structure including an iL-layer of low impurity concentration containing p-type impurities in comparatively low concentration and an iH-layer of high impurity concentration containing p-type impurities in comparatively high concentration, the former being adjacent to the n-layer; (3) a light-emitting semiconductor device having both of the above-mentioned features and (4) a method of producing a layer of an n-type gallium nitride compound semic

Abstract: In a separation layer removing process &agr;, temperature in a reaction chamber (heat treatment temperature TX) is raised to about 1000° C. and a separation layer A is evaporated through thermal decomposition, to thereby separate about 10 &mgr;m in thickness of protection layer B from a base substrate side (a sapphire substrate 101 comprising a buffer layer 102). Because decomposition temperature of the separation layer A is higher than growth temperature of the protection layer B (about 650° C.) and lower than growth temperature of the semiconductor crystal C (about 1000° C.), the separation layer A vanishes (evaporates) by thermal decomposition, which generates this separation process. Accordingly, a semiconductor crystal having a cross sectional structure shown in FIG. 2B is obtained.

Abstract: A method of this invention includes annealing at least one region of a substrate with a short pulse of particles. The particles can be electrons, protons, alpha particles, other atomic or molecular ions or neutral atoms and molecules. The substrate can be composed of a semiconductor material, for example. The particles can include dopant atoms such as p-type dopant atoms such as boron (B), aluminum (Al), gallium (Ga), or indium (In), and n-type dopant atomic species including arsenic (As), phosphorus (P), or antimony (Sb). The particles can also include silicon (Si) or germanium (Ge) atoms or ionized gas atoms including those of hydrogen (He), oxygen (O), nitrogen (N), neon (Ne), argon (Ar), or krypton (Kr). The particles can be used to anneal dopant atoms previously implanted into the substrate.

Abstract: A manufacturing method for a silicon substrate having a strained layer, has steps of forming a plurality of atomic steps having a height of 0.1 nm or more on the surface of a silicon substrate, forming a plurality of terraces having a width of 0.1 &mgr;m or more between the plurality of atomic steps and forming a SiGe layer or a SiGe layer and a Si layer on the silicon substrate.

Abstract: Includes the step of crystal-growing a group III-V compound semiconductor layer containing at least nitrogen and arsenic as group V elements on a single crystal substrate. The step of crystal-growing the compound semiconductor layer includes the stop of supplying a nitrogen source material to the single crystal substrate so that the nitrogen source material interacts with aluminum at least on a crystal growth surface of the compound semiconductor layer. Thus, a method is provided for forming a group III-V compound semiconductor layer containing a group III-V compound semiconductor containing arsenic as a group V element and also containing nitrogen mix-crystallized therewith, which has superb light emission characteristics.