Amorphous Semiconductor Patents (Class 438/482)
  • Patent number: 10403497
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes, in order: polishing a silicon carbide semiconductor base body from a second main surface side thus forming unevenness on a second main surface; forming a thin metal film made of metal capable of forming a metal carbide on the second main surface of the silicon carbide semiconductor base body; irradiating a laser beam which falls within a visible region or within an infrared region to the thin metal film so as to heat the thin metal film thus forming a metal carbide on a boundary face between the silicon carbide semiconductor base body and the thin metal film; etching a metal containing byproduct layer possibly formed on a surface side of the metal carbide by a non-oxidizing chemical solution thus exposing a surface of the metal carbide; and forming a cathode electrode on the metal carbide.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: September 3, 2019
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Yusuke Fukuda, Yoshiyuki Watanabe, Shunichi Nakamura
  • Patent number: 10119193
    Abstract: Provided is a method of manufacturing an epitaxial wafer, which includes vapor-phase growing an epitaxial layer on a substrate W placed on a susceptor 3 in a state where an upper surface 4b1 of a lift pin 4 inserted in a through-hole H of the susceptor 3 retracts or projects with respect to an upper opening H1a of the through-hole H. A level difference D from the upper surface 4b1 of the lift pin 4 to the opening H1a of the through-hole H is measured with laser light, and outputs, during epitaxial growth, of heaters 9 located above and beneath the susceptor 3 are adjusted on the basis of the measured level difference D. Thus, a method of manufacturing an epitaxial wafer, which facilitates adjustment of the outputs of the heat sources during epitaxial growth, is provided.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: November 6, 2018
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventor: Hideki Hariya
  • Patent number: 10062771
    Abstract: The present disclosure relates to a low temperature poly-silicon thin film transistor and a method of preparing the same. The low temperature poly-silicon thin film transistor includes a substrate, a metal induction layer formed on the substrate, a barrier layer formed on the metal induction layer, and an amorphous silicon film layer formed on the barrier layer, the amorphous silicon film layer being converted into a poly-silicon film layer under the inducing effect of the metal induction layer, and the poly-silicon film layer being an active layer. In the present disclosure, although the active layer is obtained by using the metal induction method, the metal induction layer is provided below the amorphous silicon film layer, and a barrier layer is provided between the metal induction layer and the amorphous silicon film layer.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: August 28, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Jinming Li
  • Patent number: 9922800
    Abstract: Embodiments of a method for generating ions in an ion source are provided. The method for generating ions in an ion source includes introducing a dopant gas and a diluent gas into an ion source arc chamber. The method for generating ions in an ion source further includes generating plasma in the ion source arc chamber based on the dopant gas and the diluent gas. In addition, the dopant gas includes carbon monoxide, and the diluent gas includes xenon and hydrogen.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Ming-Hui Li, Stanley Chang, Po-Yi Tseng, Chia-Cheng Liu, Chang-Chun Wu, Shen-Han Lin, Chih-Wen Huang, Ming-Hsien Wu
  • Patent number: 9887213
    Abstract: The present disclosure provides a method for forming an active layer with a pattern. The method includes forming an amorphous silicon layer and forming a function layer on the amorphous silicon layer. The function layer has a same pattern as the active layer. The method further includes performing a crystallization process for converting the amorphous silicon layer to a poly-silicon layer. The poly-silicon layer has first portions covered by the function layer and second portions not covered by the function layer, and grain sizes of the poly-silicon in the first portions are larger than grain sizes of the poly-silicon in the second portions.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: February 6, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zuqiang Wang, Chien Hung Liu, Yu Cheng Chan, Lujiang Huangfu
  • Patent number: 9871197
    Abstract: A semiconductor memory device according to an embodiment includes: a plurality of first conductive lines stacked in a first direction above a semiconductor substrate and extending in a second direction; a second conductive line extending in the first direction; semiconductor layers arranged between the first conductive lines and the second conductive line and extending in the first direction; a conductive layer in contact with a bottom surface of the semiconductor layer with a first impurity of a first conductivity type; and variable resistance films arranged at intersections between the first conductive lines and the semiconductor layer, the semiconductor layer having a first semiconductor part arranged from the bottom surface of the semiconductor layer to a position equal to or lower than a bottom surface of the first conductive line at a lowermost layer in the first direction with a second impurity of a second conductivity type.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: January 16, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hikari Tajima, Takashi Izumida
  • Patent number: 9825196
    Abstract: The present invention relates to a microcrystalline silicon thin film solar cell and the manufacturing method thereof, using which not only the crystallinity of a microcrystalline silicon thin film that is to be formed by the manufacturing method can be controlled and adjusted at will and the defects in the microcrystalline silicon thin film can be fixed, but also the device characteristic degradation due to chamber contamination happening in the manufacturing process, such as plasma enhanced chemical vapor deposition (PECVD), can be eliminated effectively.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: November 21, 2017
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN
    Inventors: Min-Chuan Wang, Tian-You Liao, Chih-Pong Huang, Der-Jun Jan
  • Patent number: 9786807
    Abstract: A method to fabricate thin-film photovoltaic devices including a photovoltaic Cu(In,Ga)Se2 or equivalent ABC absorber layer, such as an ABC2 layer, deposited onto a back-contact layer characterized in that the method includes at least five deposition steps, during which the pair of third and fourth steps are sequentially repeatable, in the presence of at least one C element over one or more steps. In the first step at least one B element is deposited, followed in the second by deposition of A and B elements at a deposition rate ratio Ar/Br, in the third at a ratio Ar/Br lower than the previous, in the fourth at a ratio Ar/Br higher than the previous, and in the fifth depositing only B elements to achieve a final ratio A/B of total deposited elements.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: October 10, 2017
    Assignees: EMPA, FLISOM AG
    Inventors: Adrian Chirila, Ayodhya Nath Tiwari, Patrick Bloesch, Shiro Nishiwaki, David Bremaud
  • Patent number: 9780114
    Abstract: The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposit inhibiting patterns, each deposit inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: October 3, 2017
    Assignee: SK Hynix Inc.
    Inventor: Young Jin Lee
  • Patent number: 9685455
    Abstract: The technique described herein can form a semiconductor device having a favorable characteristic over a flash memory with a 3D structure. Provided is a method of manufacturing a semiconductor device, including: (a) forming a stacked structure having an insulating film and a sacrificial film stacked therein by performing a combination a plurality of times, the combination including: (a-1) forming the insulating film on a substrate; (a-2) forming the sacrificial film on the insulating film; and (a-3) modifying at least one of the insulating film and the sacrificial film to reduce a difference between stresses of the insulating film and the sacrificial film.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 20, 2017
    Assignee: Hitachi Kokusai Electric, Inc.
    Inventors: Satoshi Shimamoto, Takashi Nakagawa
  • Patent number: 9663405
    Abstract: An oxide sintered compact made of indium (In), gallium (Ga), zinc (Zn) and oxygen (O) and represented by a formula of InxGayZnzOa [wherein x/(x+y) is 0.2 to 0.8, z/(x+y+z) is 0.1 to 0.5, and a=(3/2)x+(3/2)y+z], wherein the concentration of volatile impurities contained in the oxide sintered compact is 20 ppm or less. Provided is technology for application to the production of an IGZO target capable of achieving high densification and low bulk resistance of the sputtering target, preventing swelling and cracks of the target during the production process, minimizing the generation of nodules, inhibiting abnormal discharge, and enabling DC sputtering.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: May 30, 2017
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Masakatsu Ikisawa, Masataka Yahagi, Kozo Osada, Takashi Kakeno, Hideo Takami
  • Patent number: 9607830
    Abstract: There is provided a method of forming a germanium (Ge) film on a surface of a target object, which includes: supplying an aminosilane-based gas into a processing chamber in which the target object is loaded; supplying a high-order silane-based gas of disilane or higher into the processing chamber; and supplying a Ge source gas into the processing chamber. A process temperature in supplying the Ge source gas is set to fall within a range from a temperature, at which the Ge source gas is thermally decomposed or higher, to 300 degrees C. or less.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: March 28, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Mitsuhiro Okada
  • Patent number: 9496510
    Abstract: A flexible substrate, a method of manufacturing the same, and an organic light emitting diode display, the flexible substrate including a first flexible layer; a polysilicon layer on the first flexible layer, the polysilicon layer having a plurality of protrusions on a surface thereof; and a second flexible layer on the polysilicon layer.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: November 15, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yong-Jin Kim, Sang-Hyun Jun
  • Patent number: 9461263
    Abstract: The organic light emitting display apparatus includes a substrate; a buffer film on the substrate, the buffer film including a via hole, a thin film transistor (TFT) on the buffer film, the TFT including an active layer, a gate electrode, a source electrode, and a drain electrode, a first electrode electrically connected to one of the source electrode and the drain electrode and corresponding to the via hole; an intermediate layer on the first electrode, the intermediate layer including an organic emission layer, and a second electrode on the intermediate layer.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: October 4, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Chun-Gi You, Joon-Hoo Choi, Jong-Hyun Park, Kyung-Hoon Park, Jeong-Hwan Kim, Seong-Kweon Heo
  • Patent number: 9431402
    Abstract: A method for fabricating a semiconductor device includes: forming an insulation layer over a semiconductor substrate; forming a first conductive layer over the insulation layer; forming a plurality of buried bit lines and insulation layer patterns isolated by a plurality of trenches, wherein the plurality of trenches are formed by etching the first conductive layer and the insulation layer; forming a sacrificial layer to gap-fill the trenches; forming a second conductive layer over the buried bit lines and the sacrificial layer; and forming a plurality of pillars over each of the buried bit lines by etching the second conductive layer.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: August 30, 2016
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yun-Hyuck Ji, Kwan-Woo Do, Beom-Yong Kim, Seung-Mi Lee, Woo-Young Park
  • Patent number: 9378953
    Abstract: Disclosed is a method for preparing a polycrystalline metal oxide pattern, characterized by comprising: annealing a predetermined region of an amorphous metal oxide film by laser, so as to convert the amorphous metal oxide in the predetermined region into a polycrystalline metal oxide; and etching the amorphous metal oxide outside of the predetermined region so as to remove it. By the method according to the present invention, firstly, the predetermined region of an amorphous metal oxide film is annealed by laser so as to convert the amorphous metal oxide into a polycrystalline metal oxide, and then, the amorphous metal oxide outside of the predetermined region is etched away, thereby a polycrystalline metal oxide pattern is formed. The method for preparing a polycrystalline metal oxide pattern according to the present invention is simple, and can effectively shorten the production period and save production costs.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: June 28, 2016
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Liangliang Li, Zongjie Guo, Huibin Guo, Shoukun Wang, Yuchun Feng, Xiaowei Liu
  • Patent number: 9305752
    Abstract: A method for operating a substrate processing apparatus is provided which can contain generation of particles by generating plasma in a stable manner. After a substrate is disposed in an evacuated vacuum chamber, a rare gas is initially supplied into the vacuum chamber, a voltage is applied to a plasma generating means, and plasma of the rare gas is generated. Subsequently, a reaction gas is supplied into the vacuum chamber, the reaction gas is brought into contact with the plasma of the rare gas, and plasma of the reaction gas is generated. The plasma of the reaction gas is brought into contact with the substrate; and the substrate is processed. Plasma is stably generated not by turning the reaction gas into plasma but by first turning the rare gas into plasma by the plasma generating means, and generation of particles is subsequently suppressed.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: April 5, 2016
    Assignee: ULVAC, INC.
    Inventors: Yutaka Kokaze, Masahisa Ueda, Yoshiaki Yoshida
  • Patent number: 9287108
    Abstract: The present invention relates to the field of liquid crystal displaying techniques, and in particular to a preparation method of low-temperature polysilicon thin film, including: growing a buffer layer and then an amorphous silicon layer on the substrate; heating up an amorphous silicon layer to reach a temperature higher than room temperature, and performing pre-cleaning on the amorphous silicon layer; and using excimer laser annealing (ELA) to radiate on the pre-cleaned amorphous silicon layer in previous step to transform the amorphous silicon into polysilicon. The present invention further provides a manufacturing system of low-temperature polysilicon thin film. By improving the manufacturing system of the low-temperature polysilicon thin film and pre-cleaning method, the present invention improves thickness non-uniformity of the amorphous silicon layer and the uniformity of the polysilicon layer transformed in the subsequent step of ELA radiation.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 15, 2016
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Longxian Zhang
  • Patent number: 9243318
    Abstract: A sintered body which includes at least indium oxide and gallium oxide and comprises voids each having a volume of 14000 ?m3 or more in an amount of 0.03 vol % or less.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: January 26, 2016
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu Tomai, Shigeo Matsuzaki, Koki Yano, Makoto Ando, Kazuaki Ebata, Masayuki Itose
  • Patent number: 9230806
    Abstract: The present invention relates to a method for forming a crystallized silicon layer made up of grains having an average size of no less than 20 ?m, including at least the steps that comprise: (1) providing a layer of silicon to be (re)crystallized, the average grain size of which is less than 10 ?m; (2) placing said layer of silicon to be (re)crystallized in contact with a liquid composition at least partially made up of a metal solvent; and (3) exposing the assembly to a thermal treatment suitable for (re)crystallizing said layer of silicon with the expected grain size, characterized in that said thermal treatment includes heating the assembly made up of the layer of silicon in contact with said liquid composition to a temperature that is lower than 1410° C. and at least equal to the eutectic temperature in the solvent-silicon phase diagram.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: January 5, 2016
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, S'Tile
    Inventors: Jean-Paul Garandet, Virginie Brize, Etienne Pihan, Alain Straboni, Florent Dupont
  • Patent number: 9212045
    Abstract: A micro mechanical structure includes a substrate and a functional structure arranged at the substrate. The functional structure includes a functional region which is deflectable with respect to the substrate responsive to a force acting on the functional region. The functional structure further includes a conductive base layer having a conductive base layer material. The conductive base layer material includes sectionally in a stiffening section a carbon material such that a carbon concentration of the carbon material in the conductive base layer material is at least 1014 per cubic cm and at least higher by a factor of 103 than in the conductive base layer material adjacent to the stiffening section.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: December 15, 2015
    Assignee: Infineon Technologies AG
    Inventors: Ulrich Schmid, Tobias Frischmuth, Peter Irsigler, Thomas Grille, Daniel Maurer, Ursula Hedenig, Markus Kahn, Guenter Denifl
  • Patent number: 9171938
    Abstract: An object is to provide a thin film transistor and a method for manufacturing the thin film transistor including an oxide semiconductor with a controlled threshold voltage, high operation speed, a relatively easy manufacturing process, and sufficient reliability. An impurity having influence on carrier concentration in the oxide semiconductor layer, such as a hydrogen atom or a compound containing a hydrogen atom such as H2O, may be eliminated. An oxide insulating layer containing a large number of defects such as dangling bonds may be formed in contact with the oxide semiconductor layer, such that the impurity diffuses into the oxide insulating layer and the impurity concentration in the oxide semiconductor layer is reduced. The oxide semiconductor layer or the oxide insulating layer in contact with the oxide semiconductor layer may be formed in a deposition chamber which is evacuated with use of a cryopump whereby the impurity concentration is reduced.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: October 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Akiharu Miyanaga, Masayuki Sakakura, Junichi Koezuka, Tetsunori Maruyama, Yuki Imoto
  • Patent number: 9147710
    Abstract: The present disclosure relates to a method the present disclosure relates to an active pixel sensor having a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the active pixel sensor has a photodetector disposed within a semiconductor substrate. A transfer transistor having a first gate structure is located on a first gate dielectric layer disposed above the semiconductor substrate. A reset transistor having a second gate structure is located on the first gate dielectric layer. A gate dielectric protection layer is disposed onto the gate oxide at a position extending between the first gate structure and the second gate structure and over the photodetector. The gate dielectric protection layer protects the first gate dielectric layer from etching procedures during fabrication of the active pixel sensor.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: September 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hsien Chou, Wen-I Hsu, Tsun-Kai Tsao, Chih-Yu Lai, Jiech-Fun Lu, Yeur-Luen Tu
  • Patent number: 9111897
    Abstract: A method of forming a polysilicon layer includes providing a silicon precursor onto an object loaded in a process chamber to form a seed layer. The silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor. The method further includes providing a silicon source on the seed layer.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: August 18, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Geun Jee, Jin-Gyun Kim, Ji-Hoon Choi, Ki-Hyun Hwang
  • Publication number: 20150147871
    Abstract: Described herein are precursors and methods for forming silicon-containing films.
    Type: Application
    Filed: June 2, 2014
    Publication date: May 28, 2015
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: Manchao Xiao, Xinjian Lei, Daniel P. Spence
  • Publication number: 20150126021
    Abstract: A film is formed on a substrate by performing a cycle at least twice, the cycle including a nucleus formation process for forming nuclei on the substrate and a nucleus growth suppression process for suppressing growth of the nuclei. A time required for the nucleus growth suppression process is less than or equal to a time required for the nucleus formation process. Alternatively, the nucleus formation process is further performed after the cycle is repeatedly performed a plurality of times.
    Type: Application
    Filed: January 15, 2015
    Publication date: May 7, 2015
    Inventors: Yasunobu KOSHI, Keigo NISHIDA, Kiyohiko MAEDA
  • Patent number: 9012307
    Abstract: A method of forming a two terminal device. The method includes forming a first dielectric material overlying a surface region of a substrate. A bottom wiring material is formed overlying the first dielectric material and a switching material is deposited overlying the bottom wiring material. The bottom wiring material and the switching material is subjected to a first patterning and etching process to form a first structure having a top surface region and a side region. The first structure includes at least a bottom wiring structure and a switching element having a first side region, and a top surface region including an exposed region of the switching element. A second dielectric material is formed overlying at least the first structure including the exposed region of the switching element. The method forms an opening region in a portion of the second dielectric layer to expose a portion of the top surface region of the switching element.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: April 21, 2015
    Assignee: Crossbar, Inc.
    Inventors: Sung Hyun Jo, Scott Brad Herner
  • Patent number: 9012912
    Abstract: Glass treatment methods, wafer, panels, and semiconductor devices are disclosed. In some embodiments, a method of treating a glass substrate includes forming a first film on the glass substrate, the first film having a first porosity. The method includes forming a second film on the first film, the second film comprising an electrically insulating material and having a second porosity. The first porosity is lower than the second porosity.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wen-Shiang Liao
  • Patent number: 9012295
    Abstract: In one embodiment a method of forming a compressive polycrystalline semiconductive material layer is disclosed. The method comprises forming a polycrystalline semiconductive seed layer over a substrate and forming a silicon layer by depositing silicon directly on the polycrystalline silicon seed layer under amorphous process conditions at a temperature below 600 C.
    Type: Grant
    Filed: October 25, 2012
    Date of Patent: April 21, 2015
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Lehnert, Stefan Pompl, Markus Meyer
  • Publication number: 20150104933
    Abstract: Systems and methods are provided for annealing a semiconductor device structure using microwave radiation. For example, a semiconductor device structure is provided. An interfacial layer is formed on the semiconductor device structure. A high-k dielectric layer is formed on the interfacial layer. Microwave radiation is applied to anneal the semiconductor device structure for fabricating semiconductor devices.
    Type: Application
    Filed: October 16, 2013
    Publication date: April 16, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: CHUN-HSIUNG TSAI, XIONG-FEI YU, KUO-FENG YU
  • Patent number: 9000440
    Abstract: There is provided a thin film transistor including an active layer on a substrate (the active layer including polysilicon and a metal catalyst dispersed in the polysilicon, a source area, a drain area, and a channel area), a gate electrode disposed on the channel area of the active layer, a source electrode electrically connected to the source area, and a drain electrode electrically connected to the drain area, wherein the gate electrode, the source area, and the drain area of the active layer include metal ions, the source area and the drain area are separate from each other, and the channel is disposed between the source area and the drain area.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: April 7, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yun-Mo Chung, Jin-Wook Seo, Tak-Young Lee
  • Patent number: 8993415
    Abstract: In a method, a gate dielectric film is formed on a semiconductor substrate. A gate electrode is formed on the gate dielectric film. Impurities of a first conduction-type are introduced into a drain-layer formation region. The impurities of the first conduction-type in the drain-layer formation region are activated by performing heat treatment. Single crystals of the semiconductor substrate in a source-layer formation region are amorphized by introducing inert impurities into the source-layer formation region. Impurities of a second conduction-type is introduced into the source-layer formation region. At least an amorphous semiconductor in the source-layer formation region is brought into a single crystal semiconductor and the impurities of the second conduction-type in the source-layer formation region is activated by irradiating the semiconductor substrate with microwaves.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiyotaka Miyano, Toshitaka Miyata
  • Publication number: 20150087139
    Abstract: Described herein are precursors and methods for forming silicon-containing films. In one aspect, the precursor comprises a compound represented by one of following Formulae A through E below: In one particular embodiment, the organoaminosilane precursors are effective for a low temperature (e.g., 350° C. or less), atomic layer deposition (ALD) or plasma enhanced atomic layer deposition (PEALD) of a silicon-containing film. In addition, described herein is a composition comprising an organoaminosilane described herein wherein the organoaminosilane is substantially free of at least one selected from the amines, halides (e.g., Cl, F, I, Br), higher molecular weight species, and trace metals.
    Type: Application
    Filed: September 11, 2014
    Publication date: March 26, 2015
    Applicant: AIR PRODUCTS AND CHEMICALS, INC.
    Inventors: Mark Leonard O'Neill, Manchao Xiao, Xinjian Lei, Richard Ho, Haripin Chandra, Matthew R. MacDonald, Meiliang Wang
  • Publication number: 20150079772
    Abstract: The present invention relates to a method for forming a crystallised silicon layer made up of grains having an average size of no less than 20 ?m, including at least the steps that comprise: (1) providing a layer of silicon to be (re)crystallised, the average grain size of which is less than 10 ?m; (2) placing said layer of silicon to be (re)crystallised in contact with a liquid composition at least partially made up of a metal solvent; and (3) exposing the assembly to a thermal treatment suitable for (re)crystallising said layer of silicon with the expected grain size, characterised in that said thermal treatment includes heating the assembly made up of the layer of silicon in contact with said liquid composition to a temperature that is lower than 1410° C. and at least equal to the eutectic temperature in the solvent-silicon phase diagram.
    Type: Application
    Filed: April 8, 2013
    Publication date: March 19, 2015
    Inventors: Jean-Paul Garandet, Virginie Brize, Etienne Pihan, Alain Straboni, Florent Dupont
  • Patent number: 8969182
    Abstract: A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a transistor including an oxide semiconductor film, an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a first crystalline oxide semiconductor film) is formed; oxygen is added to the oxide semiconductor film to amorphize at least part of the oxide semiconductor film, so that an amorphous oxide semiconductor film containing an excess of oxygen is formed; an aluminum oxide film is formed over the amorphous oxide semiconductor film; and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that an oxide semiconductor film containing a crystal having a c-axis which is substantially perpendicular to a top surface thereof (also called a second crystalline oxide semiconductor film) is formed.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Naoto Yamade, Yuhei Sato, Yutaka Okazaki, Shunpei Yamazaki
  • Patent number: 8957416
    Abstract: Disclosed herein is a thin film transistor including: a channel layer made of a crystalline oxide semiconductor having a bixbyte structure, in which (222) planes of the channel layer are roughly parallel to the carrier travel direction.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 17, 2015
    Assignee: Sony Corporation
    Inventor: Mikihiro Yokozeki
  • Patent number: 8946025
    Abstract: A method for forming a thin film according to an exemplary embodiment of the present invention includes forming the thin film at a power density in the range of approximately 1.5 to approximately 3 W/cm2 and at a pressure of an inert gas that is in the range of approximately 0.2 to approximately 0.3 Pa. This process results in an amorphous metal thin film barrier layer that prevents undesired diffusion from adjacent layers, even when this barrier layer is thinner than many conventional barrier layers.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: February 3, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byeong-Beom Kim, Je-Hyeong Park, Jae-Hyoung Youn, Jean-Ho Song, Jong-In Kim
  • Patent number: 8946065
    Abstract: Provided is a method of forming a seed layer for forming a thin film, which is capable of further improving a thickness uniformity of the thin film. The method of forming a seed layer that is a seed of the thin film on a base includes adsorbing at least silicon included in an aminosilane-based gas on the base, by using the aminosilane-based gas; and depositing at least silicon included in a higher-order silane-based gas having an order that is equal to or higher than disilane on the base, on which at least the silicon included in the aminosilane-based gas is adsorbed, by using the higher-order silane-based gas having an order that is equal to or higher than the disilane.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: February 3, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Mitsuhiro Okada, Akinobu Kakimoto, Kazuhide Hasebe
  • Patent number: 8941112
    Abstract: A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: January 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8940625
    Abstract: An embodiment of the present invention relates to a low temperature polysilicon thin film and a manufacturing method thereof. The manufacturing method comprises: forming a buffer layer on a substrate (S11); forming a seed layer comprising a plurality of uniformly distributed crystal nuclei on the buffer layer by using a patterning process (S12); forming an amorphous silicon layer on the seed layer (S13); and performing an excimer laser annealing process on the amorphous silicon layer (S14).
    Type: Grant
    Filed: December 10, 2012
    Date of Patent: January 27, 2015
    Assignee: Boe Technology Group Co., Ltd.
    Inventors: Xueyan Tian, Chunping Long, Jiangfeng Yao
  • Patent number: 8921821
    Abstract: Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: December 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shuichiro Yasuda, Noel Rocklein, Scott E. Sills, D. V. Nirmal Ramaswamy, Qian Tao
  • Patent number: 8921205
    Abstract: Chemical vapor deposition methods are used to deposit amorphous silicon-containing films over various substrates. Such methods are useful in semiconductor manufacturing to provide a variety of advantages, including uniform deposition over heterogeneous surfaces, high deposition rates, and higher manufacturing productivity. Preferably, the deposited amorphous silicon-containing film is annealed to produce crystalline regions over all or part of an underlying substrate.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: December 30, 2014
    Assignee: ASM America, Inc.
    Inventor: Michael A. Todd
  • Patent number: 8921206
    Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below ?30° C.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: December 30, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chan-Lon Yang, Ching-I Li, Ger-Pin Lin, I-Ming Lai, Yun-San Huang, Chin-I Liao, Chin-Cheng Chien
  • Patent number: 8912071
    Abstract: A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 8906789
    Abstract: The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: December 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Yi-Fang Pai, Chien-Chang Su, Tzu-Chun Tseng, Meng-Yueh Liu
  • Patent number: 8906756
    Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. In a manufacturing process of a bottom-gate transistor including an oxide semiconductor layer, heat treatment in an atmosphere containing oxygen and heat treatment in vacuum are sequentially performed for dehydration or dehydrogenation of the oxide semiconductor layer. In addition, irradiation with light having a short wavelength is performed concurrently with the heat treatment, whereby elimination of hydrogen, OH, or the like is promoted. A transistor including an oxide semiconductor layer on which dehydration or dehydrogenation treatment is performed through such heat treatment has improved stability, so that variation in electrical characteristics of the transistor due to light irradiation or a bias-temperature stress (BT) test is suppressed.
    Type: Grant
    Filed: May 18, 2011
    Date of Patent: December 9, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Ryosuke Watanabe, Suzunosuke Hiraishi, Junichiro Sakata
  • Patent number: 8906771
    Abstract: Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Mikhalev, Jim Fulford, Yongjun Jeff Hu, Gordon A. Haller, Lequn Liu
  • Publication number: 20140346436
    Abstract: Silicon based nanoparticle inks are formulated with viscous polycyclic alcohols to control the rheology of the inks. The inks can be formulated into pastes with non-Newtonian rheology and good screen printing properties. The inks can have low metal contamination such that they are suitable for forming semiconductor structures. The silicon based nanoparticles can be elemental silicon particles with or without dopant.
    Type: Application
    Filed: May 20, 2014
    Publication date: November 27, 2014
    Applicant: NanoGram Corporation
    Inventors: Weidong Li, Masaya Soeda, Gina Elizabeth Pengra-Leung, Shivkumar Chiruvolu
  • Patent number: 8895414
    Abstract: A method of forming an amorphous silicon film includes: forming a seed layer on a surface of a base by heating the base and supplying an amino silane-based gas to the heated base, forming the amorphous silicon film with thickness for layer growth on the seed layer by heating the base and supplying a silane-based gas containing no amino group to the seed layer on the surface of the heated base, and decreasing a film thickness of the amorphous silicon film by etching the amorphous silicon film formed with thickness for layer growth.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: November 25, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Akinobu Kakimoto, Satoshi Takagi, Kazumasa Igarashi
  • Patent number: 8895415
    Abstract: The method and apparatus disclosed herein relate to preparing a stack structure for an electronic device on a semiconductor substrate. A particularly beneficial application of the method is in reduction of internal stress in a stack containing multiple layers of silicon. Typically, though not necessarily, the internal stress is a compressive stress, which often manifests as wafer bow. In some embodiments, the method reduces the internal stress of a work piece by depositing phosphorus doped silicon layers having low internal compressive stress or even tensile stress. The method and apparatus disclosed herein can be used to reduce compressive bow in stacks containing silicon.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: November 25, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Keith Fox, Dong Niu, Joseph L. Womack