Differential Etching Patents (Class 438/498)
  • Patent number: 9984881
    Abstract: Methods of fabricating a semiconductor device include forming a first semiconductor layer of a first conductivity type and having a first dopant concentration, and forming a second semiconductor layer on the first semiconductor layer. The second semiconductor layer has a second dopant concentration that is less than the first dopant concentration. Ions are implanted into the second semiconductor layer to form an implanted region of the first conductivity type extending through the second semiconductor layer to contact the first semiconductor layer. A first electrode is formed on the implanted region of the second semiconductor layer, and a second electrode is formed on a non-implanted region of the second semiconductor layer. Related devices are also discussed.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: May 29, 2018
    Assignee: Cree, Inc.
    Inventors: Scott T. Sheppard, Alexander V. Suvorov
  • Publication number: 20150125976
    Abstract: A method of producing a bulk semiconductor material comprises the steps of providing a base comprising a substantially planar substrate having a plurality of etched nano/micro-structures located thereon, each structure having an etched, substantially planar sidewall, wherein the plane of each said etched sidewall is arranged at an oblique angle to the substrate, and selectively growing the bulk semiconductor material onto the etched sidewall of each nano/micro-structure using an epitaxial growth process. A layered semiconductor device may be grown onto the bulk semiconductor material.
    Type: Application
    Filed: June 7, 2013
    Publication date: May 7, 2015
    Inventor: Wang Nang Wang
  • Patent number: 9023733
    Abstract: The present disclosure relates to a method (10) for block-copolymer lithography. This method comprises the step of obtaining (12) a self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, and the steps of applying at least once each of first plasma etching (14) of said self-organizing block-copolymer layer using a plasma formed from a substantially ashing gas, and second plasma etching (16) of said self-organizing block-copolymer layer using plasma formed from a pure inert gas or mixture of inert gases in order to selectively remove a first polymer phase. A corresponding intermediate product also is described.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 5, 2015
    Assignees: IMEC, Tokyo Electron Limited
    Inventors: Boon Teik Chan, Shigeru Tahara
  • Patent number: 9006713
    Abstract: In one aspect, an organic light-emitting display apparatus is provided including a first sub-pixel, a second sub-pixel, and a third sub-pixel that are each a different color, the apparatus including: a substrate; a first electrode disposed on the substrate; a second electrode disposed on the first electrode so as to face the first electrode; an organic emission layer disposed between the first electrode and the second electrode and comprising a first organic emission layer, a second organic emission layer, and a third organic emission layer; a hole transport layer disposed between the first electrode and the organic emission layer; and an electron accepting layer disposed between the first electrode and the second electrode. The organic light-emitting display apparatus has improved image quality and lifetime.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: April 14, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Woo Park, Myung-Jong Jung, Sung-Woo Cho, Sang-Woo Pyo, Hyo-Yeon Kim
  • Patent number: 8946032
    Abstract: A power device manufacturing method is provided. The power device manufacturing method may perform patterning of regions on which a source electrode and a drain electrode are to be formed, may regrow n+-gallium nitride (GaN) and p+-GaN in the patterned regions and thus, a thin film crystal may not be damaged. Also, a doping concentration of n+-GaN or p+-GaN may be adjusted, an ohmic resistance in the source electrode region and the drain electrode region may decrease, and a current density may increase. The power device manufacturing method may regrow n+-GaN and p+-GaN at a high temperature after an n-GaN layer and a p-GaN layer are patterned. Accordingly, a thin film crystal may not be damaged and thus, a reliability may be secured, and an annealing process may not be additionally performed and thus, a process may be simplified and a cost may be reduced.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: February 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae Hoon Lee
  • Publication number: 20140363954
    Abstract: A mask layer is formed on a Ga polarity surface of the GaN substrate as a growth substrate. Subsequently, a protective film PF is formed on a N polarity surface of the GaN substrate. Then, a plurality of concave portions is formed from the mask layer extending to the GaN substrate, to thereby form a seed crystal. The seed crystal is etched in a Na melt, and a plurality of concave portions having a facet plane exposed. The seed crystal and the raw materials are placed in a crucible, and the pressure and temperature inside the crucible are increased. Thus, a target GaN layer is grown in the upward direction on the surface of the mask layer and the lateral direction over the concave portions.
    Type: Application
    Filed: June 10, 2014
    Publication date: December 11, 2014
    Inventors: Shohei Kumegawa, Yasuhide Yakushi, Seiji Nagai, Miki Moriyama
  • Patent number: 8664056
    Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain\-inducing semiconductor material, superior uniformity may be achieved by using an implantation process so as to selectively modify the etch behavior of exposed portions of the active region. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility, while at the same time the dependence on pattern loading effect may be reduced. Consequently, a significantly reduced variability of transistor characteristics may be achieved.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Wirbeleit, Andy Wei
  • Patent number: 8597992
    Abstract: A transistor is manufactured by a method including: forming a first wiring layer; forming a first insulating film to cover the first wiring layer; forming a semiconductor layer over the first insulating film; forming a conductive film over the semiconductor layer; and performing at least two steps of etching on the conductive film to form second wiring layers which are apart from each other, wherein the two steps of etching include at least a first etching process performed under the condition that the etching rate for the conductive film is higher than the etching rate for the semiconductor layer, and a second etching process performed under the condition that the etching rates for the conductive film and the semiconductor layer are higher than those of the first etching process.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: December 3, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Masashi Tsubuku, Hitoshi Nakayama, Daigo Shimada
  • Patent number: 8557689
    Abstract: An extrusion head is disposed over a substrate, and material is extruded through an oblique (e.g., semi-circular or tapered) outlet orifice of the extrusion head to form an associated extruded structure having an equilibrium shape that resists settling after being deposited on the substrate. The extrusion head includes fluidic channels having a flat surface formed by a flat first (e.g., metal) sheet, and an oblique (e.g., substantially semi-cylindrical) surface formed by elongated oblique trenches that are etched or otherwise formed in a second sheet. The fluidic channel communicates with the outlet orifice, which has a flat edge formed by the first sheet, and an oblique edge formed by an end of the oblique trench. The material is extruded through the outlet orifice such that its flat lower surface contacts the substrate, and its oblique upper surface faces away from the substrate. Two materials are co-extruded to form high aspect-ratio gridlines.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: October 15, 2013
    Assignee: Solarworld Innovations GmbH
    Inventors: David K Fork, Thomas S. Zimmermann
  • Patent number: 8372708
    Abstract: This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a semiconductor substrate, surrounded by a source region encompassed in a body region near the top surface above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an implanting-ion block disposed above the top surface on a mesa area next to the body region having a thickness substantially larger than 0.3 micron for blocking body implanting ions and source ions from entering into the substrate under the mesa area whereby masks for manufacturing the semiconductor power device can be reduced.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: February 12, 2013
    Inventors: Anup Bhalla, François Hébert, Sung-Shan Tai, Sik K Lui
  • Patent number: 8247312
    Abstract: A method of printing an ink on a wafer surface configured with a set of non-rounded peaks and a set of non-rounded valleys is disclosed. The method includes exposing the wafer including at least some non-rounded peaks and at least some of the non-rounded valleys in a region to an etchant. The method further includes depositing the ink on the region, wherein a set of rounded peaks and a set of rounded valleys are formed.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: August 21, 2012
    Assignee: Innovalight, Inc.
    Inventors: Malcolm Abbott, Maxim Kelman, Karel Vanheusden
  • Patent number: 8183879
    Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Brederlow, Roland Thewes
  • Patent number: 8173462
    Abstract: A manufacturing method of a nitride crystalline film includes following steps. First, a substrate is provided. Next, a first nitride crystalline film is formed on the substrate. A patterned mask is then formed on the first nitride crystalline film. The patterned mask covers a first part of the first nitride crystalline film and exposes a second part of the first nitride crystalline film. Afterwards, the second part is etched, and the first part is maintained. After that, the patterned mask is removed. The first part is then etched to form a plurality of nitride crystal nuclei. Next, a second nitride crystalline film is formed on the substrate, and the second nitride crystalline film is made to cover the nitride crystal nuclei. A nitride film and a substrate structure are also provided.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 8, 2012
    Assignee: National Central University
    Inventors: Cheng-Huang Kuo, Chi-Wen Kuo, Chun-Ju Tun
  • Patent number: 8071481
    Abstract: A multi-step etching process produces trench openings in a silicon substrate that are immediately adjacent transistor structures formed over the substrate surface. The multi-step etching process is a Br-based etching operation with one step including nitrogen and a further step deficient of nitrogen. The etching process does not attack the transistor structure and forms an opening bounded by upper surfaces that extend downwardly from the substrate surface and are substantially vertical, and lower surfaces that bulge outwardly from the upper vertical sections and undercut the transistor structure. The aggressive undercut produces a desirable stress in the etched silicon surface. The openings are then filled with a suitable source/drain material and SSD transistors with desirable Idsat characteristics may then be formed.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: December 6, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Wei Kao, Shiang-Bau Wang, Ming-Jie Huang, Chi-Hsi Wu, Shu-Yuan Ku
  • Patent number: 8062947
    Abstract: The present invention relates to a method of manufacturing a semiconductor device having a shared contact for connection between a source/drain region and a gate electrode. After formation of a gate electrode via a gate insulating film on a semiconductor substrate, a top surface of the substrate is covered with a cover film. After removal of the cover film from at least one of sidewall surface of the gate electrode and a part of the top surface of the substrate adjacent to the sidewall surface, a semiconductor layer is epitaxially grown on a top surface of an exposed substrate to electrically connect the substrate and the at least one sidewall surface of the gate electrode. Then, a source/drain region is formed in a top surface part of the substrate or the semiconductor layer using the gate electrode as a mask.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiichi Iwasa
  • Patent number: 8017504
    Abstract: In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: September 13, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Kai Frohberg
  • Patent number: 8019458
    Abstract: The invention provides a method of processing a wafer using multilayer processing sequences and Multi-Layer/Multi-Input/Multi-Output (MLMIMO) models and libraries that can include one or more measurement procedures, one or more Poly-Etch (P-E) sequences, and one or more metal-gate etch sequences. The MLMIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple process steps. The multiple layers and/or the multiple process steps can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using isotropic and/or anisotropic etch processes.
    Type: Grant
    Filed: August 6, 2008
    Date of Patent: September 13, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Radha Sundararajan, Asao Yamashita, Daniel Prager, Hyung Joo Lee
  • Publication number: 20110079820
    Abstract: A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.
    Type: Application
    Filed: October 2, 2009
    Publication date: April 7, 2011
    Inventors: Kao-Ting Lai, Da-Wen Lin, Hsien-Hsin Lin, Yuan-Ching Peng, Chi-Hsi Wu
  • Patent number: 7902053
    Abstract: Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: March 8, 2011
    Assignees: Sanyo Electric Co., Ltd, Sanyo Semiconductor Co., Ltd
    Inventors: Hiroyasu Ishida, Yasuyuki Sayama
  • Patent number: 7687381
    Abstract: Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selectively etched in sequence using a mask to define an opening therein. This opening, which may be a via hole, exposes inner sidewalls of the hard mask and the electrically insulating layer. The inner sidewall of the hard mask is then recessed relative to the inner sidewall of the electrically insulating layer and a sacrificial reaction layer is formed on the inner sidewall of the electrically insulating layer. This reaction layer operates to recess the inner sidewall of the electrically insulating layer. The reaction layer is then removed to define a wider opening having relatively uniform sidewalls. This wider opening is then filled with an electrical interconnect.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: March 30, 2010
    Assignees: Samsung Electronics Co., Ltd., Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jae-hak Kim, Jing Hui Li, Wu Ping Liu, Johnny Widodo
  • Publication number: 20100001255
    Abstract: Nanotube electronic devices exhibit selective affinity to disparate nanotube types. According to an example embodiment, a semiconductor device exhibits a treated substrate that selectively interacts (e.g., chemically) with nanotubes of a first type, relative to nanotubes of a second type, the respective types including semiconducting-type and metallic-type nanotubes. The selective interaction is used to set device configuration characteristics based upon the nanotube type. This selective-interaction approach can be used to set the type, and/or characteristics of nanotubes in the device.
    Type: Application
    Filed: June 26, 2009
    Publication date: January 7, 2010
    Inventors: Zhenan Bao, Melburne Lemieux, Justin P. Opatkiewicz, Soumendra N. Barman
  • Patent number: 7563711
    Abstract: Manufacturers encounter limitations in forming low resistance ohmic electrical contact to semiconductor material P-type Gallium Nitride (p-GaN), commonly used in photonic applications, such that the contact is highly transparent to the light emission of the device. Carbon nanotubes (CNTs) can address this problem due to their combined metallic and semiconducting characteristics in conjunction with the fact that a fabric of CNTs has high optical transparency. The physical structure of the contact scheme is broken down into three components, a) the GaN, b) an interface material and c) the metallic conductor. The role of the interface material is to make suitable contact to both the GaN and the metal so that the GaN, in turn, will make good electrical contact to the metallic conductor that interfaces the device to external circuitry. A method of fabricating contact to GaN using CNTs and metal while maintaining protection of the GaN surface is provided.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: July 21, 2009
    Assignee: Nantero, Inc.
    Inventors: Jonathan W. Ward, Benjamin Schlatka, Mitchell Meinhold, Robert F. Smith, Brent M. Segal
  • Patent number: 6602793
    Abstract: An improved pre-clean chamber of a semiconductor processing system minimizes the generation of particulates during processing, thereby decreasing contamination levels that can adversely affect plasma vapor deposition film properties while also decreasing operational costs. The pre-clean chamber comprises an insulator collar that insulates the outside diameter surface of a wafer pedestal, thereby mitigating the etching of the wafer pedestal during etching. The pre-clean chamber further comprises a gas trench cover that directs a suitable etching gas from a gas inlet trench into streams that are focused up and towards the center of the chamber to reduce the extent to which gas bombards the chamber cover. The pre-clean chamber also comprises a bellows cover which protects the bellows of a wafer lift during etching, further reducing the dislodgment of particulates during etching.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: August 5, 2003
    Assignee: Newport Fab, LLC
    Inventor: Sean Masterson
  • Patent number: 6475884
    Abstract: In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided.
    Type: Grant
    Filed: August 8, 2001
    Date of Patent: November 5, 2002
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui
  • Patent number: 6100172
    Abstract: The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an implant. By conformally depositing the resist over a substrate having both vertical and horizontal surfaces, implanting the resist, and developing the resist, the resist is removed from the vertical surfaces while remaining on the horizontal surfaces. Thus, a self-aligned spacer is formed on the horizontal surfaces while the spacer material is removed from the vertical surfaces. This horizontal-surface spacer can then be used in further fabrication. The preferred method can be used in many different processes where there is exists a need to differentially process the vertical and horizontal surfaces of a substrate.
    Type: Grant
    Filed: October 29, 1998
    Date of Patent: August 8, 2000
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Paul A. Rabidoux
  • Patent number: 6083520
    Abstract: The present invention relates to a bioactive feed pellet comprising besides commonly used nutritionally valuable components, a biologically active ingredient such as a therapeutically or prophylactically active compound, a vaccine, a pigment, a vitamin, and/or an enzyme, whereby the bioactive ingredient has been applied to the pellet in the form of a primary coating dispersion and/or emulsion and/or solution in a fatty component or a mixture of dietary oil, said component or dietary oil comprising a triglyceride, and/or fatty acid thereof, having a melting point of above 35.degree. C. in an amount of at least 0.05% by weight of the total weight of the pellet, and in an amount comprising at least 0.2% by weight of said coating, and that a further, second coating layer of an oily product has been applied after said coating dispersion, and/or emulsion and/or solution comprising the bioactive ingredient.
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: July 4, 2000
    Assignee: Ewos Aktiebolag
    Inventor: Mark Toneby
  • Patent number: 6033995
    Abstract: The invention relates to a method for integrating semiconductor device epilayers with arbitrary host substrates, where an indium gallium arsenide etch-stop layer (34) is deposited on an indium phosphide growth substrate (32) and device epilayers (36, 38) are grown on the etch-stop layer in inverse order from their final orientation. The device epilayers are then joined to an aluminum nitride host substrate (42) by inverting the growth substrate and device epilayers. The epilayers are bonded to the host substrate using mono-molecular layer forming bonding material and the growth substrate is selectively etched away from the device epilayers. As a result of the inverse epilayer growth, the epilayers are not removed from the growth substrate prior to bonding to the host substrate, thus protecting the device epilayers and reducing processing steps. Additionally, by mono-molecular bonding, sturdy semiconductor devices are formed with low thermal impedance.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: March 7, 2000
    Assignee: TRW Inc.
    Inventor: Heinrich G. Muller
  • Patent number: 5918128
    Abstract: An integrated circuit fabrication process is provided in which a transistor having an ultra short channel length is formed by multiple etchings of a gate conductor layer. After formation of the gate conductor using a photolithographic process, the lateral length of the gate conductor is reduced by forming a masking layer upon the gate conductor such that only a portion of the gate conductor is covered by the masking layer. The unmasked portion of the gate conductor is then removed to reduce the lateral length of the gate conductor. In this manner, a gate conductor having a lateral length that is significantly less than a lateral length attainable using a photolithographic process may be obtained.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: June 29, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark I. Gardner, John J. Bush