Fluid Growth From Liquid Combined With Preceding Diverse Operation Patents (Class 438/497)
  • Patent number: 10202543
    Abstract: Quantum dot delivery methods are described. In a first example, a method of delivering or storing a plurality of nano-particles involves providing a plurality of nano-particles. The method also involves forming a dispersion of the plurality of nano-particles in a medium for delivery or storage, wherein the medium is free of organic solvent. In a second example, a method of delivering or storing a plurality of nano-particles involves providing a plurality of nano-particles in an organic solvent. The method also involves drying the plurality of nano-particles for delivery or storage, the drying removing entirely all of the organic solvent.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: February 12, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Georgeta Masson, Kari N. Haley, Brian Theobald, Benjamin Daniel Mangum, Juanita N. Kurtin
  • Patent number: 10002789
    Abstract: A method for formation of multi-level contact structures with reduced contact resistance is provided. The contact resistance of the multi-level contact structures can be reduced by selectively removing portions of a contact liner layer that are formed along sidewalls and bottom portions of contact openings located in each contact level from the bottom portions of the contact openings.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: June 19, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 9502639
    Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory includes: a seed layer including conductive hafnium silicate; a first magnetic layer formed over the seed layer; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: November 22, 2016
    Assignee: SK hynix Inc.
    Inventors: Won-Joon Choi, Ki-Seon Park, Cha-Deok Dong, Bo-Mi Lee, Guk-Cheon Kim, Seung-Mo Noh
  • Patent number: 9252323
    Abstract: A first nitride semiconductor layer laminating step includes a first step and a second step. In the first step, an entire upper surface of the sapphire substrate is coated with a first nitride semiconductor layer, while supplying oxygen. In the second step, crystals of the first nitride semiconductor layer are grown by supplying oxygen at a smaller flow rate than that of oxygen supplied in the first step, or without supplying the oxygen.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: February 2, 2016
    Assignee: NICHIA CORPORATION
    Inventor: Atsuo Michiue
  • Publication number: 20150144883
    Abstract: A damascene approach is used to form a recessed structure in a substrate for receiving liquid-deposited solution, such as a carbon nanotube (CNT) solution. The liquid-deposited solution is built-up in the recessed structure, simplifying the coating process and providing a more uniform thickness of the liquid-deposited layer.
    Type: Application
    Filed: November 22, 2013
    Publication date: May 28, 2015
    Applicant: Atmel Corporation
    Inventor: Bryan D. Sendelweck
  • Patent number: 9000449
    Abstract: A semiconductor substrate that includes a semiconductor layer that exhibits high crystallinity includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine, and a semiconductor layer that is grown on the surface of the graphite layer, or includes a substrate that includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine on its surface, a buffer layer that is grown on the surface of the graphite layer, and a semiconductor layer that is grown on the surface of the buffer layer.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 7, 2015
    Assignees: The University of Tokyo, Tokai Carbon Co., Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Hiroshi Fujioka, Tetsuro Hirasaki, Hitoshi Ue, Junya Yamashita, Hiroaki Hatori
  • Patent number: 8993418
    Abstract: The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: March 31, 2015
    Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, STMicroelectronics, Inc.
    Inventors: Vincent Destefanis, Nicolas Loubet
  • Publication number: 20140322901
    Abstract: A method for preparing semiconductor nanocrystals includes adding a non-protonated surface modification agent to semiconductor nanocrystal cores in a liquid medium to form a mixture; adding one or more precursors for forming a shell including a semiconductor material to the mixture under conditions for forming the shell over at least a portion of an outer surface of the cores, and adding an acid ligand to the mixture after addition of at least a portion of the one or more precursors. Semiconductor nanocrystals, other methods of making semiconductor nanocrystals, compositions and products including semiconductor nanocrystals are also disclosed.
    Type: Application
    Filed: February 28, 2014
    Publication date: October 30, 2014
    Applicant: QD VISION, INC.
    Inventors: DIYUN HUANG, CHUNMING WANG, ZHIMING WANG, JONATHAN S. STECKEL
  • Patent number: 8865574
    Abstract: A method for electrodepositing nanoparticles onto a substrate, including heating a nonaqueous polar suspension of a plurality of semiconducting nanoparticles to a temperature between about 30 degrees Celsius and about 100 degrees Celsius, placing a substrate into the suspension, imparting opposite surface charges onto the plurality of semiconducting particles and onto the substrate, establishing an electric field in the suspension, depositing a film of semiconducting particles onto the substrate to define a coated substrate, removing the coated substrate from the suspension into air, and coating the film of semiconducting particles with an electrically conducting metal layer.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: October 21, 2014
    Inventor: Michael Haag
  • Patent number: 8823143
    Abstract: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: September 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw, Devendra K. Sadana, Katherine L. Saenger
  • Publication number: 20140147996
    Abstract: Solvent mixtures useful for processing bulk heterojunction materials and methods for selecting the same are disclosed, wherein Hansen solubility parameters are utilized to select the solvent mixture. A solvent system using a fully nonhalogenated solvent mixture is disclosed. Also disclosed is a solvent mixture containing 20 vol. % acetophenone (AP) in mesitylene (MS), wherein the performance of the solvent system is comparable to dichlorobenzene.
    Type: Application
    Filed: November 28, 2011
    Publication date: May 29, 2014
    Applicant: Arizon Board of Regents Acting for and on Behalf Arizona State University
    Inventors: Bryan D. Vogt, Jian Li, Choong-Do Park
  • Patent number: 8728951
    Abstract: A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 20, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Xianfeng Lu, Deepak A. Ramappa
  • Patent number: 8729672
    Abstract: To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: May 20, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Takanao Shimodaira, Takayuki Hirao, Katsuhiro Imai
  • Patent number: 8652950
    Abstract: A carbon-rich carbon boron nitride dielectric film having a dielectric constant of equal to, or less than 3.6 is provided that can be used as a component in various electronic devices. The carbon-rich carbon boron nitride dielectric film has a formula of CxByNz wherein x is 35 atomic percent or greater, y is from 6 atomic percent to 32 atomic percent and z is from 8 atomic percent to 33 atomic percent.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Son Van Nguyen, Alfred Grill, Thomas J. Haigh, Jr., Sanjay Mehta
  • Publication number: 20140017884
    Abstract: In the present invention, copper(I) selenide (Cu2-xSe) nanoparticles are fabricated by pyrolysis in an inert atmosphere. Uniformly dispersed Cu2-xSe particles are synthesized by altering Cu/Se ratio, the concentration of Se Precursors (TOP Se), reaction time and temperature. Analysis by inductively coupled plasma atomic emission spectroscopy (ICP-AES) of said Cu2-xSe nanoparticles reveals that the composition of the nanoparticles is Cu 1.95Se, wherein x=0.05. In addition, Cu2-xSe is dissolved in ethanol to deposit thin films by electrophoretical deposition (EPD) in an inert atmosphere, wherein a positive electrode and a negative electrode are employed. The positive electrode is made of stainless steel plate and the negative electrode is made of indium tin oxide on a glass substrate. Investigations on properties and surface morphology thereof in different electrophoretical conditions are carried out. The rate of EPD is found to significantly influence the quality of thin films.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: National Chung Cheng University
    Inventors: Chu-Chi Ting, Wen-Yuan Lee
  • Patent number: 8557648
    Abstract: Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: October 15, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn, Chung-Hsun Lin, Jeffrey W. Sleight
  • Patent number: 8506827
    Abstract: Methods for forming a metal grating include providing a first grating including a plurality of grating lines formed from a dielectric material, each grating having a pair of sidewalls, facing sidewalls of adjacent grating lines being separated by corresponding trenches, the grating lines and trenches forming a grating surface; forming a layer of a metal on the grating surface, where the metal layer has a constant thickness and conforms to the grating surface; and removing portions of the metal layer between sidewalls of adjacent grating lines of the first grating to form a metal grating having grating lines formed from the metal, the grating lines of the metal grating corresponding to the portions of the metal layer adjacent the sidewalls of the grating lines of the first grating. The metal grating has a pitch of 200 nm or less, a depth of 50 nm or more, and the grating lines of the metal grating have an aspect ratio of 10-to-1 or more.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: August 13, 2013
    Assignee: Polarization Solutions, LLC
    Inventors: Qihong Wu, Sheng Liu, Xu Zhang, Shiaw-wen Tai, Xiaohua Du, Thomas Tombler
  • Patent number: 8440017
    Abstract: To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: May 14, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Takanao Shimodaira, Takayuki Hirao, Katsuhiro Imai
  • Patent number: 8420456
    Abstract: An object is to provide a semiconductor device with improved reliability in which a defect stemming from an end portion of a semiconductor layer provided in an island shape is prevented, and a manufacturing method thereof. Over a substrate having an insulating surface, an island-shaped semiconductor layer is formed, a first alteration treatment is performed, a first insulating film is formed on a surface of the island-shaped semiconductor layer, the first insulating film is removed, a second alteration treatment is performed on the island-shaped semiconductor from which the first insulating film is removed, a second insulating film is formed on a surface of the island-shaped semiconductor layer, and a conductive layer is formed over the second insulating film. An upper end portion of the island-shaped semiconductor layer has curvature by the first alteration treatment and the second alteration treatment.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: April 16, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Satoru Okamoto
  • Patent number: 8420515
    Abstract: A method for manufacturing a solar cell is disclosed. A conductive layer is introduced into a mold having an interior defining a shape of a solar cell. A planar capillary space is formed along the conductive layer. A measure of silicon is placed in fluid communication with the capillary space. The silicon is melted and allowed to flow into the capillary space. The melted silicon is then cooled within the capillary space such that the silicon forms a p-n junction along the conductive layer.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: April 16, 2013
    Assignee: Mossey Creek Solar, LLC
    Inventor: John Carberry
  • Patent number: 8404045
    Abstract: An underlying film 2 of a group III nitride is formed on a substrate 1 by vapor phase deposition. The substrate 1 and the underlying film 2 are subjected to heat treatment in the present of hydrogen to remove the underlying film 2 so that the surface of the substrate 1 is roughened. A seed crystal film 4 of a group III nitride single crystal is formed on a surface of a substrate 1A by vapor phase deposition. A group III nitride single crystal 5 is grown on the seed crystal film 4 by flux method.
    Type: Grant
    Filed: January 8, 2010
    Date of Patent: March 26, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Yoshitaka Kuraoka, Shigeaki Sumiya, Makoto Miyoshi, Minoru Imaeda
  • Patent number: 8334221
    Abstract: This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is provided. An antireflective coating is formed over the semiconductor substrate. The antireflective coating has an outer surface. The outer surface is treated with a basic fluid. A positive photoresist is applied onto the outer surface which has been treated with the basic treating fluid. The positive photoresist is patterned and developed effective to form a patterned photoresist layer having increased footing at a base region of said layer than would otherwise occur in the absence of said treating the outer surface. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: December 18, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Jon P. Daley
  • Patent number: 8313969
    Abstract: The present invention comprises a method for preparing a nanocrystal having (i) a core comprising a semiconductor comprising A representing a metal or metalloid in the +III oxidation state and B representing an element in the ?III oxidation state, coated with (ii) a shell in which the outer portion comprises a semiconductor having the formula ZnS1-xEx, where E represents an element in the ?II oxidation state and x is a decimal number such that 0?x<1, said method comprising a step consisting of heating a mixture of at least one precursor of A, at least one precursor of B, at least one precursor of zinc, at least one precursor of sulphur and, optionally, at least one precursor of E, from a temperature T1 to a temperature T2 greater than T1 in an increasing manner and so as to form, firstly, said core then said shell. The present invention also concerns a nanocrystal obtainable by the invention method and uses thereof.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: November 20, 2012
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Peter Reiss, Li Liang
  • Patent number: 8314015
    Abstract: A process of silicon (Si) surface modification is provided for the electrochemical synthesis of Si particles in suspension. The process begins with a Si first substrate with a surface, and forms Si particles attached to the surface. Hydrogen-terminated Si particles are created and the first substrate is immersed in a hexane/1-octene (1/1 volume ratio) solution with a catalytic amount of chloroplatinic acid (H2PtCl6). 1-octene is bonded with the hydrogen-terminated Si particles, creating modified Si particles, with octane capping ligands, attached to the substrate surface. The first substrate is then exposed to ultrasonication, separating the modified Si particles from the first substrate. After removing the first substrate, a suspension is created of modified Si particles suspended in excess hexane/1-octene.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: November 20, 2012
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Chang-Ching Tu, Liang Tang, Apostolos T. Voutsas
  • Patent number: 8294267
    Abstract: The present invention provides novel nanostructure composed of at least one elongated structure element, an elongated structure element of said nanostructure bearing a different zone made of metal, metal alloy, conductive polymer or semiconductor and selectively grown onto at least one of the end portions of the elongated structure element. The present invention further provides a selective method for forming in a liquid medium, such nanostructures.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: October 23, 2012
    Assignee: Yissum Research Development Company of the Hebrew University of Jerusalem
    Inventors: Uri Banin, Taleb Mokari
  • Patent number: 8252611
    Abstract: A buffer layer manufacturing method, including the steps of forming a fine particle layer of ZnS, Zn(S, O), and/or Zn(S, O, OH), mixing an aqueous solution (I) which includes a component (Z), an aqueous solution (II) which includes a component (S), and an aqueous solution (III) which includes a component (C) to obtain a mixed solution and mixing an aqueous solution (IV) which includes a component (N) in the mixed solution to prepare a reaction solution in which the concentration of the component (C) is 0.001 to 0.25M, concentration of the component (N) is 0.41 to 1.0M, and the pH before the start of reaction is 9.0 to 12.0, and, using the reaction solution, forming a Zn compound layer of Zn(S, O) and/or Zn(S, O, OH) on the fine particle layer by a liquid phase method with a reaction temperature of 70 to 95° C.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: August 28, 2012
    Assignee: FUJIFILM Corporation
    Inventor: Tetsuo Kawano
  • Patent number: 8247312
    Abstract: A method of printing an ink on a wafer surface configured with a set of non-rounded peaks and a set of non-rounded valleys is disclosed. The method includes exposing the wafer including at least some non-rounded peaks and at least some of the non-rounded valleys in a region to an etchant. The method further includes depositing the ink on the region, wherein a set of rounded peaks and a set of rounded valleys are formed.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: August 21, 2012
    Assignee: Innovalight, Inc.
    Inventors: Malcolm Abbott, Maxim Kelman, Karel Vanheusden
  • Patent number: 8211782
    Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: July 3, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Jurgen H. Daniel, Ana Claudia Arias
  • Patent number: 8183879
    Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Brederlow, Roland Thewes
  • Patent number: 8143118
    Abstract: A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The TFT of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: March 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Atsuo Isobe, Hiromichi Godo
  • Patent number: 8143149
    Abstract: An efficient and low-cost method is intended for forming a flexible nanostructured material suitable for use as an active element of a photovoltaic panel. The method consists of evaporating a colloidal solution, which contains nanoparticles of various sizes and/or masses, from a flat surface of a rotating body on which the solution forms a thin and easily vaporizable layer, and simultaneously releasing the nanoparticles from the solution for their free flight through a gaseous medium toward the flexible substrate. As a result, the particles of different sizes and/or types of material are deposited onto the flexible substrate in a predetermined sequence that corresponds to the magnitude of resistance experienced by the nanoparticles during their free flight.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: March 27, 2012
    Inventor: Boris Gilman
  • Patent number: 8093138
    Abstract: A method of forming an epitaxially grown layer by forming a region of weakness in a support substrate to define a support portion and a remainder portion on opposite sides of the region of weakness, epitaxially growing an epitaxially grown layer on the support portion after forming the region of weakness but prior to detachment of the support portion from the remainder portion; bonding the epitaxially grown layer to an acceptor substrate before detaching the remainder portion from the support portion; and detaching the remainder portion from the support portion at the region of weakness. The epitaxially grown layer may be removed from the support portion as a free-standing structure.
    Type: Grant
    Filed: May 20, 2009
    Date of Patent: January 10, 2012
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Bruce Faure, Lea Di Cioccio
  • Publication number: 20110315954
    Abstract: A semiconductor nanocrystal including a core including ZnSe, ZnTe, ZnS, ZnO, or a combination comprising at least one of the foregoing, wherein the core has a diameter of about 2 nanometers to about 5 nanometers and an emitted light wavelength of about 405 nanometers to about 530 nanometers; and a first layer disposed on the core, the first layer including a Group III-V semiconductor, wherein the semiconductor nanocrystal has a full width at half maximum of an emitted light wavelength of less than or equal to about 60 nanometers.
    Type: Application
    Filed: March 4, 2011
    Publication date: December 29, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eun-Joo JANG, Shin-Ae JUN, Sang-Wook KIM, Sung-Woo KIM
  • Patent number: 8048770
    Abstract: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: November 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo Eguchi, Yohei Monma, Atsuhiro Tani, Misako Hirosue, Kenichi Hashimoto, Yasuharu Hosaka
  • Patent number: 8043944
    Abstract: Processes for enhancing solubility and the reaction rates in supercritical fluids are provided. In preferred embodiments, such processes provide for the uniform and precise deposition of metal-containing films on semiconductor substrates as well as the uniform and precise removal of materials from such substrates. In one embodiment, the process includes, providing a supercritical fluid containing at least one reactant, the supercritical fluid being maintained at above its critical point, exposing at least a portion of the surface of the semiconductor substrate to the supercritical fluid, applying acoustic energy, and reacting the at least one reactant to cause a change in at least a portion of the surface of the semiconductor substrate.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: October 25, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Theodore M. Taylor, Stephen J. Kramer
  • Patent number: 8043936
    Abstract: An object is to suppress discharge due to static electricity generated by peeling, when an element formation layer including a semiconductor element is peeled from a substrate. Over the substrate, the release layer and the element formation layer are formed. The support base material which can be peeled later is fixed to the upper surface of the element formation layer. The element formation layer is transformed through the support base material, and peeling is generated at an interface between the element formation layer and the release layer. Peeling is performed while the liquid is being supplied so that the element formation layer and the release layer which appear sequentially by peeling are wetted with the liquid such as pure water. Electric charge generated on the surfaces of the element formation layer and the release layer can be diffused by the liquid, and discharge by peeling electrification can be eliminated.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: October 25, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shingo Eguchi, Yohei Monma, Atsuhiro Tani, Misako Hirosue, Kenichi Hashimoto, Yasuharu Hosaka
  • Patent number: 8030191
    Abstract: Disclosed herein are a method of producing microstructure and a method of producing mold, the methods permitting production of much smaller pores than before in an atmosphere where impurities are negligible and also permitting production of microstructures having a smaller size and a higher crystallinity than before with the help of the pores. The method of producing microstructure comprises a step of making pores (4) in a substrate (1) to become a mold (5) by irradiation with a focused energy beam (3) and a step of growing a microstructure (8) in the thus made pores (4). The method of producing a mold includes a step of making pores (4) by irradiating a substrate (1) to become a mold (5) with a focused energy beam (3).
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: October 4, 2011
    Assignee: Sony Corporation
    Inventors: Koji Kadono, Yosuke Murakami
  • Patent number: 7998789
    Abstract: A method and a system for forming a copper indium gallium sulfur selenide (CIGSSe) absorption layer and a cadmium sulfide (CdS) buffer layer under non-vacuum condition is disclosed. A coating layer is formed on the back electrode layer on the substrate by mixing the slurry on the back electrode layer, and the coating layer formed on the back electrode layer is densified by a densification device after initially dried, and then a primary selenization/sulfurization reaction process is carried out to form a primary CIGSSe layer, and then a thermal process is carried out to improve the lattice match of the primary CIGSSe layer, and then an impurity cleaning process is carried out by using potassium cyanide or bromide to remove the impurities of cuprous selenide and copper sulfide, and then a rear-stage selenization/sulfurization reaction process is carried out to produce the required rear-stage CIGSSe absorption layer.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: August 16, 2011
    Assignee: Jenn Feng New Energy Co., Ltd.
    Inventor: Chuan-Lung Chuang
  • Patent number: 7985698
    Abstract: This invention comprises methods of forming patterned photoresist layers over semiconductor substrates. In one implementation, a semiconductor substrate is provided. An antireflective coating is formed over the semiconductor substrate. The antireflective coating has an outer surface. The outer surface is treated with a basic fluid. A positive photoresist is applied onto the outer surface which has been treated with the basic treating fluid. The positive photoresist is patterned and developed effective to form a patterned photoresist layer having increased footing at a base region of said layer than would otherwise occur in the absence of said treating the outer surface. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: July 5, 2006
    Date of Patent: July 26, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Jon P. Daley
  • Patent number: 7915151
    Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: March 29, 2011
    Assignee: President and Fellows of Harvard College
    Inventors: Charles M. Lieber, Yi Cui, Xiangfeng Duan, Yu Huang
  • Patent number: 7842588
    Abstract: A method for forming a group-III metal nitride material film attached to a substrate including subjecting the substrate to an ambient pressure of no greater than 0.01 Pa, and heating the substrate to a temperature of between approximately 500° C.-800° C. The method further includes introducing a group III metal vapor to the surface of the substrate at a base pressure of at least 0.01 Pa, until a plurality of group III metal drops form on the surface, and introducing active nitrogen to the surface at a working pressure of between 0.05 Pa and 2.5 Pa, until group III metal nitride molecules form on the group III metal drops.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: November 30, 2010
    Assignee: Mosaic Crystals
    Inventor: Moshe Einav
  • Patent number: 7785982
    Abstract: Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Hariklia Deligianni, Qiang Huang, Lubomyr T. Romankiw, Devendra K. Sadana, Katherine L. Saenger
  • Patent number: 7776709
    Abstract: A method (and apparatus) of replicating a pattern on a structure, includes using imprint lithography to replicate a pattern formed on a first structure onto a portion of a second structure.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: Matthew E. Colburn, Yves C. Martin, Theodore G. van Kessel, Hematha K. Wickramasinghe
  • Patent number: 7741198
    Abstract: A method for fabricating a probing pad is disclosed. A substrate having thereon a dielectric layer is provided. An inlaid metal wiring is formed in the dielectric layer. The inlaid metal wiring and the dielectric layer are covered with a passivation dielectric film. A portion of the passivation dielectric film is then etched away to form a reinforcement pattern on the inlaid metal wiring. The reinforcement pattern has inter-space that exposes a portion of the underlying inlaid metal wiring. A conductive pad is formed over the reinforcement pattern and the passivation dielectric film. The conductive pad fills the inter-space of the reinforcement pattern.
    Type: Grant
    Filed: June 29, 2008
    Date of Patent: June 22, 2010
    Assignee: United Microelectronics Corp.
    Inventor: Chien-Ming Lan
  • Patent number: 7704863
    Abstract: Chemical bath deposition (CBD) has proved top be the most favorable method for application of a buffer layer to semiconductor substrates, for example, chalcopyrite thin-film solar cells, whereby previously cadmium sulphide (CdS) was deposited and as cadmium is a highly toxic heavy metal, alternatives have been required. According to the invention, the semiconductor substrate is dipped in a solution for approximately 10 minutes, produced by the dissolution of zinc sulphate (0.05-0.5 mol/l) and thiourea (0.2 to 1.5 mol/l) in distilled water at a temperature being held essentially constant throughout said period. For the first time, the ZnS layer permits comparable or higher efficiencies than conventionally only achieved with toxic cadmium compounds. The method is hence much more environmentally-friendly with the same result.
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: April 27, 2010
    Assignee: Helmholtz-Zentrum Berlin fuer Materialien und Energie GmbH
    Inventors: Ahmed Ennaoui, Timo Kropp, Martha Christina Lux-Steiner
  • Patent number: 7687378
    Abstract: A fabricating method of nitride semiconductor substrate is provided. First, a first substrate including a first base material, a nitride semiconductor template layer stacked on the first base material, and a first dielectric layer stacked on the nitride semiconductor template layer is provided. Then, the first dielectric layer and the nitride semiconductor template layer are patterned, and a second substrate including a second base material and a second dielectric layer stacked on the second base material is provided. Next, the nitride semiconductor template layer and the first dielectric layer of the first substrate are transferred onto the second dielectric layer of the second substrate through bonding and transferring processes, and then a nitride semiconductor thick film is grown from the nitride semiconductor template layer through an epitaxy process. After that, the nitride semiconductor thick film and the second substrate are separated.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: March 30, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Po-Chun Liu, Wen-Yueh Liu, Chih-Ming Lai, Yih-Der Guo, Jenq-Dar Tsay
  • Patent number: 7682952
    Abstract: A structure and method of forming same, comprising a low threading density alloy graded layer, deposited according to a deposition temperature profile in correspondence with increasing alloy composition. In one embodiment, a first substantially relaxed alloy graded layer is deposited while varying a deposition temperature according to a first temperature profile. A second substantially relaxed alloy graded layer is deposited over the first graded layer while varying a deposition temperature according to a second temperature profile. Preferably, the minimum signed rate of change of the second temperature profile is less than the maximum signed rate of change of the first temperature profile.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: March 23, 2010
    Assignee: Massachusetts Institute of Technology
    Inventors: David Michael Isaacson, Eugene A. Fitzgerald
  • Patent number: 7674712
    Abstract: A method of patterning a substrate by mechanically locating a first masking film over the substrate; removing one or more first opening portions in first locations in the first masking film to form one or more first masking portions in the first masking film. First materials are deposited over the substrate in the first locations to form first patterned areas before mechanically locating a second masking film over the substrate and first masking portions. One or more second opening portions are removed from second locations, different from the first locations, in both the second masking film and the first masking portions to form one or more second masking portions. Second materials are deposited over the substrate in the second locations to form second patterned areas.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: March 9, 2010
    Inventor: Ronald S. Cok
  • Publication number: 20100041216
    Abstract: The present invention relates to a method of forming a nitride semiconductor substrate. This method includes steps of providing a substrate and then forming an epitaxy layer on the substrate. A patterned mask layer is formed on the epitaxy layer, wherein the patterned mask layer exposes a portion of the epitaxy layer. Next, an oxidation process is performed to oxidize the exposed epitaxy layer so as to form a plurality of dislocation blocking structures. The patterned mask layer is then removed. Further, a nitride semiconductor layer is formed on the epitaxy layer having the dislocation blocking structures.
    Type: Application
    Filed: October 20, 2009
    Publication date: February 18, 2010
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Ming Lai, Jenq-Dar Tsay, Wen-Yueh Liu, Yih-Der Guo
  • Patent number: 7659202
    Abstract: A method performed on a wafer having multiple chips each including a doped semiconductor and substrate involves etching an annulus trench, metalizing an inner and an outer perimeter side wall of the annulus trench, etching a via trench into the wafer, making a length of the via trench electrically conductive, thinning a surface of the substrate.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: February 9, 2010
    Inventor: John Trezza