Fluid Growth From Liquid Combined With Subsequent Diverse Operation Patents (Class 438/500)
  • Patent number: 10224422
    Abstract: Disclosed herein are embodiments of a method to form quantum dot field-effect transistors (QD FETs) having little to no bias-stress effect. Bias-stress effect can be reduced or eliminated through, as an example, the use of a gas or liquid to remove ligands and/or reduce charge trapping on the QD FETs, followed by deposition of an inorganic or organic matrix around the QDs in the FET.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: March 5, 2019
    Assignee: The Regents of the University of California
    Inventors: Matt Law, Jason Tolentino
  • Patent number: 9236265
    Abstract: Methods of selectively etching silicon germanium relative to silicon are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the silicon germanium. The plasmas effluents react with exposed surfaces and selectively remove silicon germanium while very slowly removing other exposed materials. Generally speaking, the methods are useful for removing Si(1-X)GeX (including germanium i.e. X=1) faster than Si(1-Y)GeY, for all X>Y. In some embodiments, the silicon germanium etch selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: January 12, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Mikhail Korolik, Nitin K. Ingle, Anchuan Wang, Jingjing Xu
  • Publication number: 20150144174
    Abstract: A crystalline silicon ingot is produced using a directional solidification process. In particular, a crucible is loaded with silicon feedstock above a seed layer of uniform crystalline orientation. The silicon feedstock and an upper part of the seed layer are melted forming molten material in the crucible. This molten material is then solidified, during which process a crystalline structure based on that of the seed layer is formed in a silicon ingot. The seed layer is arranged such that a {110} crystallographic plane is normal to the direction of solidification and also so that a peripheral surface of the seed layer predominantly also lies in a {110} crystallographic plane. It is found that this arrangement offers a substantial improvement in the proportion of mono-crystalline silicon formed in the ingot as compared to alternative crystallographic orientations.
    Type: Application
    Filed: May 15, 2013
    Publication date: May 28, 2015
    Inventors: Oleg Fefelov, Erik Sauar, Egor Vladimirov
  • Patent number: 9034739
    Abstract: A method of making a semiconductor device comprises: providing a semiconductor wafer having a semiconductor layer; forming a first mask layer over the semiconductor layer; forming a second mask layer over the first mask layer; annealing the second mask layer to form islands; etching through the first mask layer and the semiconductor layer using the islands as a mask to form an array of pillars; and growing semiconductor material between the pillars and then over the tops of the pillars.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: May 19, 2015
    Assignee: Seren Photonics Limited
    Inventor: Tao Wang
  • Patent number: 9020002
    Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: April 28, 2015
    Assignee: The Regents of the University of California
    Inventors: Matthew N. Sysak, John E. Bowers, Alexander W. Fang, Hyundai Park
  • Publication number: 20150064886
    Abstract: Methods for passivating a nanotube fabric layer within a nanotube switching device to prevent or otherwise limit the encroachment of an adjacent material layer are disclosed. In some embodiments, a sacrificial material is implanted within a porous nanotube fabric layer to fill in the voids within the porous nanotube fabric layer while one or more other material layers are applied adjacent to the nanotube fabric layer. Once the other material layers are in place, the sacrificial material is removed. In other embodiments, a non-sacrificial filler material (selected and deposited in such a way as to not impair the switching function of the nanotube fabric layer) is used to form a barrier layer within a nanotube fabric layer. In other embodiments, individual nanotube elements are combined with and nanoscopic particles to limit the porosity of a nanotube fabric layer.
    Type: Application
    Filed: November 7, 2014
    Publication date: March 5, 2015
    Inventors: Thomas RUECKES, H. Montgomery MANNING, Rahul SEN
  • Publication number: 20150011078
    Abstract: A mask for forming a semiconductor pattern includes a first body portion provided with a first through hole for injecting a semiconductor material and a second body portion provided with a second through hole for exhausting a gas. As the result of the gas suction through the second through hole, the semiconductor material may be crystallized to form a semiconductor pattern on a base substrate. A thickness of the semiconductor pattern can be controlled by a space between the mask and the base substrate, and a crystal structure of the semiconductor pattern can be controlled by an amount of the gas to be exhausted through the second through hole.
    Type: Application
    Filed: December 5, 2013
    Publication date: January 8, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventor: Jiwon HAN
  • Patent number: 8907333
    Abstract: Composite of layers which comprises a dielectric layer and a layer which comprises pyrogenic zinc oxide and is bonded to the dielectric layer. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to the dielectric layer in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm, and the zinc oxide layer is dried and then treated at temperatures of less than 200° C. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to a substrate layer or a composite of substrate layers in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm to form a zinc oxide layer, and then the zinc oxide layer and the substrate layer are treated at temperatures of less than 200° C., and then a dielectric layer is applied to the zinc oxide layer. Field-effect transistor which has the composite of layers.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: December 9, 2014
    Assignees: Evonik Degussa GmbH, Forschungszentrum Karlsruhe GmbH
    Inventors: Frank-Martin Petrat, Heiko Thiem, Sven Hill, Andre Ebbers, Koshi Okamura, Roland Schmechel
  • Patent number: 8846505
    Abstract: A method for growing islands of semiconductor monocrystals from a solution on an amorphous substrate includes the procedures of depositing a semiconductor-metal mixture layer, applying lithography and etching for forming at least one platform, heating the at least one platform, and saturating the semiconductor-metal solution until a monocrystal of the semiconductor component is formed. The procedure of depositing a semiconductor-metal mixture layer, includes a semiconductor component and at least one other metal component, is performed on top of the amorphous substrate. The procedure of applying lithography and etching to the semiconductor-metal mixture layer and a portion of the amorphous substrate is performed for forming at least one platform, the at least one platform having a top view shape corresponding to crystal growth direction and habit respective of the semiconductor component.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: September 30, 2014
    Assignee: SKOKIE Swift Corporation
    Inventor: Moshe Einav
  • Patent number: 8841206
    Abstract: A method of forming a polycrystalline silicon layer includes forming a first amorphous silicon layer and forming a second amorphous silicon layer such that the first amorphous silicon layer and the second amorphous silicon layer have different film qualities from each other, and crystallizing the first amorphous silicon layer and the second amorphous silicon layer using a metal catalyst to form a first polycrystalline silicon layer and a second polycrystalline silicon layer. A thin film transistor includes the polycrystalline silicon layer formed by the method and an organic light emitting device includes the thin film transistor.
    Type: Grant
    Filed: August 17, 2011
    Date of Patent: September 23, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Jong-Ryuk Park, Yun-Mo Chung, Tak-Young Lee, Jin-Wook Seo, Ki-Yong Lee, Min-Jae Jeong, Yong-Duck Son, Byung-Soo So, Seung-Kyu Park, Dong-Hyun Lee, Kil-Won Lee, Jae-Wan Jung
  • Patent number: 8815621
    Abstract: A method of forming a p-type gallium nitride based semiconductor without activation annealing is provided, and the method can provide a gallium nitride based semiconductor doped with a p-type dopant. A GaN semiconductor region 17 containing a p-type dopant is formed on a supporting base 13 in a reactor 10. An organometallic source and ammonia are supplied to the reactor 10 to grow the GaN semiconductor layer 17 on a GaN semiconductor layer 15. The GaN semiconductor is doped with a p-type dopant. Examples of the p-type dopant include magnesium. After the GaN semiconductor regions 15 and 17 are grown, an atmosphere 19 containing at least one of monomethylamine and monoethylamine is prepared in the reactor 10. After the atmosphere 19 is prepared, a substrate temperature is decreased from the growth temperature of the GaN semiconductor region 17. When the substrate temperature is lowered to room temperature after this film formation, a p-type GaN semiconductor 17a and an epitaxial wafer E has been fabricated.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: August 26, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Masaki Ueno, Yusuke Yoshizumi, Takao Nakamura
  • Publication number: 20140206126
    Abstract: A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on relatively inexpensive buffered substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films could have widespread application in photovoltaic and display technologies.
    Type: Application
    Filed: March 25, 2014
    Publication date: July 24, 2014
    Applicant: Solar-Tectic LLC
    Inventors: Karin Chaudhari, Pia Chaudhari, Ashok Chaudhari
  • Patent number: 8778708
    Abstract: There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes: providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of ?25 to 80° C. and under a vacuum in the range of 10?6 to 1,000 Torr, for a first period of 1-100 minutes, to form a partially dried layer; heating the partially dried layer to a temperature above 100° C. for a second period of 1-50 minutes to form a dried layer.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: July 15, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Reid John Chesterfield, Justin Butler, Paul Anthony Sant
  • Patent number: 8759199
    Abstract: A method of selectively growing a plurality of semiconductor carbon nanotubes using light irradiation. The method includes disposing a plurality of nanodots, which include a catalyst material, on a substrate; growing a plurality of carbon nanotubes from the plurality of nanodots, and irradiating light onto the nanodot to selectively grow the plurality of semiconductor carbon nanotubes.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: June 24, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-mook Choi, Jae-young Choi, Jin Zhang, Guo Hong
  • Patent number: 8691667
    Abstract: This invention relates to a process for forming a continuous pattern on a substrate with a liquid media. Upon the deposition of the liquid media on the substrate, a portion the continuous pattern is evaporated upon contact with the substrate.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: April 8, 2014
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Charles Douglas MacPherson, Dennis Damon Walker, Matthew Stainer
  • Patent number: 8691404
    Abstract: A method of constructing a solid-state energy-density micro radioisotope power source device. In such embodiments, the method comprises depositing the pre-voltaic semiconductor composition, comprising a semiconductor material and a radioisotope material, into a micro chamber formed within a power source device body. The method additionally includes heating the body to a temperature at which the pre-voltaic semiconductor composition will liquefy within the micro chamber to provide a liquid state composite mixture. Furthermore, the method includes cooling the body and liquid state composite mixture such that liquid state composite mixture solidifies to provide a solid-state composite voltaic semiconductor, thereby providing a solid-state high energy-density micro radioisotope power source device.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: April 8, 2014
    Assignee: The Curators of the University of Missouri
    Inventors: Jae Wan Kwon, Tongtawee Wacharasindhu, John David Robertson
  • Patent number: 8673752
    Abstract: A method of growing an epitaxial semiconductor structure is disclosed. The growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: March 18, 2014
    Assignee: Athenaeum, LLC
    Inventor: Eric Ting-Shan Pan
  • Patent number: 8609520
    Abstract: A carbon ribbon (16) has two faces (20, 22) and two longitudinal ends (34, 36), at least one of the faces of the ribbon (16?) having a central portion (20a, 22a) situated between the two longitudinal ends (34, 36), which central portion is to receive a deposit of a layer of a semiconductor material (30, 32). The ribbon further includes, on at least one of its races (20, 22), at least one longitudinal groove (17) situated between one of said ends (34, 36) and the central portion (20a, 22a), and in that the longitudinal groove (17) is shaped in such a manner that when the layer of the semiconductor material is deposited, the semiconductor material (30, 32) filling the groove (17) forms a protuberance (31) adjacent to one of the longitudinal ends (34, 36) of one of the faces (20, 22) of the carbon ribbon.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: December 17, 2013
    Assignee: Solarforce
    Inventor: Robert Tastevin
  • Publication number: 20130295752
    Abstract: Methods for chemical mechanical planarization of patterned wafers are provided herein. In some embodiments, methods of processing a substrate having a first surface and a plurality of recesses disposed within the first surface may include: depositing a first material into the plurality of recesses to predominantly fill the plurality of recesses with the first material; depositing a second material different from the first material into the plurality of recesses and atop the substrate to fill the plurality of recesses and to form a layer atop the first surface; and planarizing the second material using a first slurry in a chemical mechanical polishing tool until the first surface is reached. In some embodiments, a second slurry, different than the first slurry, is used to planarize the substrate to a first level.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 7, 2013
    Inventors: YI-CHIAU HUANG, GREGORY MENK, ERROL ANTONIO C. SANCHEZ, BINGXI WOOD
  • Patent number: 8557671
    Abstract: A vertical transient voltage suppressing (TVS) device includes a semiconductor substrate of a first conductivity type where the substrate is heavily doped, an epitaxial layer of the first conductivity type formed on the substrate where the epitaxial layer has a first thickness, and a base region of a second conductivity type formed in the epitaxial layer where the base region is positioned in a middle region of the epitaxial layer. The base region and the epitaxial layer provide a substantially symmetrical vertical doping profile on both sides of the base region. In one embodiment, the base region is formed by high energy implantation. In another embodiment, the base region is formed as a buried layer. The doping concentrations of the epitaxial layer and the base region are selected to configure the TVS device as a punchthrough diode based TVS or an avalanche mode TVS.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: October 15, 2013
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla
  • Patent number: 8559478
    Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: October 15, 2013
    Assignee: The Regents of the University of California
    Inventors: Matthew N. Sysak, John E. Bowers, Alexander W. Fang, Hyundai Park
  • Patent number: 8551870
    Abstract: Epitaxially coated semiconductor wafers are produced by minimally the following steps in the order specified: (a) depositing an epitaxial layer on one side of a semiconductor wafer; (b) first polishing the epitaxially coated side of the semiconductor wafer with a polishing pad with fixed abrasive while supplying a polishing solution which is free of solids; (c) CMP polishing of the epitaxially coated side of the semiconductor wafer with a soft polishing pad which contains no fixed abrasive, while supplying a polishing agent suspension; (d) depositing another epitaxial layer on the previously epitaxially coated and polished side of the semiconductor wafer.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: October 8, 2013
    Assignee: Siltronic AG
    Inventors: Juergen Schwandner, Roland Koppert
  • Patent number: 8541294
    Abstract: A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: September 24, 2013
    Assignee: Athenaeum LLC
    Inventor: Eric Ting-Shan Pan
  • Patent number: 8530342
    Abstract: A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: September 10, 2013
    Assignee: Athenaeum, LLC
    Inventor: Eric Ting-Shan Pan
  • Patent number: 8507371
    Abstract: A method of growing an epitaxial semiconductor structure is disclosed. The growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: August 13, 2013
    Assignee: Athenaeum LLC
    Inventor: Eric Ting-Shan Pan
  • Patent number: 8507370
    Abstract: A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: August 13, 2013
    Assignee: Athenaeum LLC
    Inventor: Eric Ting-Shan Pan
  • Patent number: 8486753
    Abstract: Disclosed are a patterning method of a metal oxide thin film using nanoimprinting, and a manufacturing method of a light emitting diode (LED). The method for forming a metal oxide thin film pattern using nanoimprinting includes: coating a photosensitive metal-organic material precursor solution on a substrate; preparing a mold patterned to have a protrusion and depression structure; pressurizing the photosensitive metal-organic material precursor coating layer with the patterned mold; forming a cured metal oxide thin film pattern by heating the pressurized photosensitive metal-organic material precursor coating layer or by irradiating ultraviolet rays to the pressurized photosensitive metal-organic material precursor coating layer while being heated; and removing the patterned mold from the metal oxide thin film pattern, and selectively further includes annealing the metal oxide thin film pattern.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: July 16, 2013
    Assignee: Korea Institute of Machinery and Materials
    Inventors: Hyeong Ho Park, Jun Ho Jeong, Ki Don Kim, Dae Geun Choi, Jun Hyuk Choi, Ji Hye Lee, Soon Won Lee
  • Patent number: 8420515
    Abstract: A method for manufacturing a solar cell is disclosed. A conductive layer is introduced into a mold having an interior defining a shape of a solar cell. A planar capillary space is formed along the conductive layer. A measure of silicon is placed in fluid communication with the capillary space. The silicon is melted and allowed to flow into the capillary space. The melted silicon is then cooled within the capillary space such that the silicon forms a p-n junction along the conductive layer.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: April 16, 2013
    Assignee: Mossey Creek Solar, LLC
    Inventor: John Carberry
  • Patent number: 8415237
    Abstract: A method of manufacturing a semiconductor device includes the steps of loading a substrate into a processing chamber; processing the substrate by supplying plural kinds of reaction substances into the processing chamber multiple number of times; and unloading the processed substrate from the processing chamber, wherein at least one of the plural kinds of reaction substances contains a source gas obtained by vaporizing a liquid source by a vaporizing part; in the step of processing the substrate, vaporizing operation of supplying the liquid source to the vaporizing part and vaporizing the liquid source is intermittently performed, and at least at a time other than performing the vaporizing operation of the liquid source, a solvent capable of dissolving the liquid source is flowed to the vaporizing part at a first flow rate; and at a time other than performing the vaporizing operation of the liquid source and every time performing the vaporizing operation of the liquid source prescribed number of times, the sol
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: April 9, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Sadayoshi Horii, Yoshinori Imai
  • Publication number: 20130058827
    Abstract: A method for producing a mono-crystalline sheet includes providing at least two aperture elements forming a gap in between; providing a molten alloy including silicon in the gap; providing a gaseous precursor medium comprising silicon in the vicinity of the molten alloy; providing a silicon nucleation crystal in the vicinity of the molten alloy; and bringing in contact said silicon nucleation crystal and the molten alloy. A device for producing a mono-crystalline sheet includes at least two aperture elements at a predetermined distance from each other, thereby forming a gap, and being adapted to be heated for holding a molten alloy including silicon by surface tension in the gap between the aperture elements; a precursor gas supply supplies a gaseous precursor medium comprising silicon in the vicinity of the molten alloy; and a positioning device for holding and moving a nucleation crystal in the vicinity of the molten alloy.
    Type: Application
    Filed: May 23, 2011
    Publication date: March 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mikael T. Bjoerk, Heike E. Riel, Heinz Schmid
  • Publication number: 20130045590
    Abstract: A carbon ribbon (16) has two faces (20, 22) and two longitudinal ends (34, 36), at least one of the faces of the ribbon (16?) having a central portion (20a, 22a) situated between the two longitudinal ends (34, 36), which central portion is to receive a deposit of a layer of a semiconductor material (30, 32). The ribbon further includes, on at least one of its races (20, 22), at least one longitudinal groove (17) situated between one of said ends (34, 36) and the central portion (20a, 22a), and in that the longitudinal groove (17) is shaped in such a manner that when the layer of the semiconductor material is deposited, the semiconductor material (30, 32) filling the groove (17) forms a protuberance (31) adjacent to one of the longitudinal ends (34, 36) of one of the faces (20, 22) of the carbon ribbon.
    Type: Application
    Filed: April 8, 2011
    Publication date: February 21, 2013
    Applicant: SOLARFORCE
    Inventor: Robert Tastevin
  • Patent number: 8361891
    Abstract: Methods for consistently reproducing channels of small length are disclosed. An ink composition comprising silver nanoparticles and a surface modification agent is used. The surface modification agent may also act as a stabilizer for the nanoparticles. A first line is printed which forms a modified region around the first line. A second line is printed, which is repelled from the modified region. As a result, a channel between the first line and the second line is formed.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: January 29, 2013
    Assignee: Xerox Corporation
    Inventors: Yiliang Wu, Jason S. Doggart, Ping Liu, Shiping Zhu
  • Patent number: 8314015
    Abstract: A process of silicon (Si) surface modification is provided for the electrochemical synthesis of Si particles in suspension. The process begins with a Si first substrate with a surface, and forms Si particles attached to the surface. Hydrogen-terminated Si particles are created and the first substrate is immersed in a hexane/1-octene (1/1 volume ratio) solution with a catalytic amount of chloroplatinic acid (H2PtCl6). 1-octene is bonded with the hydrogen-terminated Si particles, creating modified Si particles, with octane capping ligands, attached to the substrate surface. The first substrate is then exposed to ultrasonication, separating the modified Si particles from the first substrate. After removing the first substrate, a suspension is created of modified Si particles suspended in excess hexane/1-octene.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: November 20, 2012
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Chang-Ching Tu, Liang Tang, Apostolos T. Voutsas
  • Patent number: 8278134
    Abstract: The production method of a photoelectric conversion device comprises adding a chalcogenide powder of a group-IIIB element to an organic solvent including a single source precursor containing a group-IB element, a group-IIIB element, and a chalcogen element to prepare a solution for forming a semiconductor, and forming a semiconductor containing a group-I-III-VI compound by use of the solution for forming a semiconductor.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: October 2, 2012
    Assignee: Kyocera Corporation
    Inventors: Isamu Tanaka, Seiichiro Inai, Yoshihide Okawa, Daisuke Nishimura, Sentaro Yamamoto
  • Patent number: 8263423
    Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: September 11, 2012
    Assignee: NanoGram Corporation
    Inventors: Henry Hieslmair, Shivkumar Chiruvolu, Hui Du
  • Patent number: 8241421
    Abstract: The epitaxial layer defects generated from voids of a silicon substrate wafer containing added hydrogen are suppressed by a method for producing an epitaxial wafer by: growing a silicon crystal by the Czochralski method comprising adding hydrogen and nitrogen to a silicon melt and growing from the silicon melt a silicon crystal having a nitrogen concentration of from 3×1013 cm?3 to 3×1014 cm?3, preparing a silicon substrate by machining the silicon crystal, and forming an epitaxial layer at the surface of the silicon substrate.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: August 14, 2012
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Timo Mueller, Atsushi Ikari, Wilfried von Ammon, Martin Weber
  • Publication number: 20120175613
    Abstract: The present invention provides a clean and high-purity polycrystalline silicon mass having a small content of chromium, iron, nickel, copper, and cobalt in total, which are heavy metal impurities that reduce the quality of single-crystal silicon. In the vicinity of an electrode side end of a polycrystalline silicon rod obtained by the Siemens method, the total of the chromium, iron, nickel, copper, and cobalt concentrations is high. Accordingly, before a crushing step of a polycrystalline silicon rod 100, a removing step of removing at least 70 mm of a polycrystalline silicon portion from the electrode side end of the polycrystalline silicon rod 100 extracted to the outside of a reactor is provided. Thereby, the polycrystalline silicon portion in which the total of the chromium, iron, nickel, copper, and cobalt concentrations in a bulk is not less than 150 ppta can be removed.
    Type: Application
    Filed: July 21, 2010
    Publication date: July 12, 2012
    Applicant: Shin-Etsu Chemical Co., Ltd.
    Inventors: Shigeyoshi Netsu, Junichi Okada, Fumitaka Kume
  • Publication number: 20120168774
    Abstract: A silicon carbide substrate and a method for manufacturing the silicon carbide substrate are obtained, each of which achieves reduced manufacturing cost of semiconductor devices using the silicon carbide substrate. A method for manufacturing a SiC-combined substrate includes the steps of: preparing a plurality of single-crystal bodies each made of silicon carbide (SiC); forming a collected body; connecting the single-crystal bodies to each other; and slicing the collected body. In the step, the plurality of SiC single-crystal ingots are arranged with a silicon (Si) containing Si layer interposed therebetween, so as to form the collected body including the single-crystal bodies. In the step, adjacent SiC single-crystal ingots are connected to each other via at least a portion of the Si layer, the portion being formed into silicon carbide by heating the collected body. In step, the collected body in which the SiC single-crystal ingots are connected to each other is sliced.
    Type: Application
    Filed: May 19, 2011
    Publication date: July 5, 2012
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Satomi Itoh, Shin Harada, Makoto Sasaki
  • Patent number: 8211782
    Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: July 3, 2012
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Jurgen H. Daniel, Ana Claudia Arias
  • Patent number: 8193078
    Abstract: A method of growing an epitaxial film and transferring it to an assembly substrate is disclosed. The film growth and transfer are made using an epitaxy lateral overgrowth technique. The formed epitaxial film on an assembly substrate can be further processed to form devices such as solar cell, light emitting diode, and other devices and assembled into higher integration of desired applications.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: June 5, 2012
    Assignee: Athenaeum, LLC
    Inventor: Eric Ting-Shan Pan
  • Patent number: 8183879
    Abstract: The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
    Type: Grant
    Filed: March 6, 2009
    Date of Patent: May 22, 2012
    Assignee: Infineon Technologies AG
    Inventors: Ralf Brederlow, Roland Thewes
  • Patent number: 8153512
    Abstract: A method of forming a patterned layer, including the steps of: (i) depositing via a liquid medium a first material onto a substrate to form a first body on said substrate; (ii) depositing via a liquid medium a second material onto said substrate to form a second body, wherein said first body is used to control said deposition of said second material so as to form a patterned structure including said first and second bodies; and (iii) using said patterned structure to control the removal of selected portions of a layer of material in a dry etching process or in a wet etching process using a bath of etchant.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: April 10, 2012
    Assignee: Plastics Logic Limited
    Inventor: Henning Sirringhaus
  • Patent number: 8143118
    Abstract: A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The TFT of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: March 27, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideto Ohnuma, Atsuo Isobe, Hiromichi Godo
  • Publication number: 20120025195
    Abstract: In a structure for crystalline material growth, there is provided a lower growth confinement layer and an upper growth confinement layer that is disposed above and vertically separated from the lower growth confinement layer. A lateral growth channel is provided between the upper and lower growth confinement layers, and is characterized by a height that is defined by the vertical separation between the upper and lower growth confinement layers. A growth seed is disposed at a site in the lateral growth channel for initiating crystalline material growth in the channel. A growth channel outlet is included for providing formed crystalline material from the growth channel. With this growth confinement structure, crystalline material can be grown from the growth seed to the lateral growth channel outlet.
    Type: Application
    Filed: July 27, 2011
    Publication date: February 2, 2012
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Kevin Andrew McComber, Jifeng Liu, Jurgen Michel, Lionel C. Kimerling
  • Publication number: 20110278533
    Abstract: A method of forming a nanoporous film is disclosed. The method comprises forming a coating solution including clusters, surfactant molecules, a solvent, and one of an acid catalyst and a base catalyst. The clusters comprise inorganic groups. The method further comprises aging the coating solution for a time period to select a predetermined phase that will self-assemble and applying the coating solution on a substrate. The method further comprises evaporating the solvent from the coating solution and removing the surfactant molecules to yield the nanoporous film.
    Type: Application
    Filed: November 1, 2007
    Publication date: November 17, 2011
    Applicant: PURDUE RESEARCH FOUNDATION
    Inventors: HUGH W. HILLHOUSE, Vikrant N. Urade, Ta-Chen Wei, Michael P. Tate
  • Patent number: 8030224
    Abstract: A method of manufacturing a semiconductor device including a semiconductor layer and a dielectric layer deposited on the semiconductor layer, including: forming the semiconductor layer; performing a surface treatment for removing a residual carbon compound, on a surface of the semiconductor layer formed; forming a dielectric film under a depositing condition corresponding to a surface state after the surface treatment, on at least a part of the surface of the semiconductor layer on which the surface treatment has been performed; and changing a crystalline state of at least a partial region of the semiconductor layer by performing a heat treatment on the semiconductor layer on which the dielectric film has been formed.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: October 4, 2011
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Hidehiro Taniguchi, Takeshi Namegaya, Etsuji Katayama
  • Patent number: 8026159
    Abstract: A method of manufacturing a semiconductor device includes the steps of loading a substrate into a processing chamber; processing the substrate by supplying plural kinds of reaction substances into the processing chamber multiple number of times; and unloading the processed substrate from the processing chamber, wherein at least one of the plural kinds of reaction substances contains a source gas obtained by vaporizing a liquid source by a vaporizing part; in the step of processing the substrate, vaporizing operation of supplying the liquid source to the vaporizing part and vaporizing the liquid source is intermittently performed, and at least at a time other than performing the vaporizing operation of the liquid source, a solvent capable of dissolving the liquid source is flown to the vaporizing part at a first flow rate; and at a time other than performing the vaporizing operation of the liquid source and every time performing the vaporizing operation of the liquid source prescribed number of times, the solv
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: September 27, 2011
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Sadayoshi Horii, Yoshinori Imai
  • Patent number: 8008173
    Abstract: A III nitride single-crystal manufacturing method in which a liquid layer (3) of 200 ?m or less thickness is formed in between a substrate (1) and a III nitride source-material baseplate (2), and III nitride single crystal (4) is grown onto the face (1s) on the liquid-layer side of the substrate (1). Herein, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side may be formed of a III nitride single crystal, while the III nitride source-material baseplate (2) can be formed of a III nitride polycrystal. Further, the substrate (1) in at least a superficial layer (1a) on the liquid-layer side, and the III nitride source-material baseplate (2) can be formed of a III nitride single crystal, while the face (1s) on the liquid-layer side of the substrate (1) can be made a III-atom surface, and the face (2s) on the liquid-layer side of the III nitride source-material baseplate (2) can be made a nitrogen-atom surface.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: August 30, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Seiji Nakahata
  • Patent number: 7998847
    Abstract: Affords methods of manufacturing bulk III-nitride crystals whereby at least the surface dislocation density is low globally. The present III-nitride crystal manufacturing method includes: a step of preparing an undersubstrate (1) containing a III-nitride seed crystal, the III-nitride seed crystal having a matrix (1s), and inversion domains (1t) in which the polarity in the <0001> directions is inverted with respect to the matrix (1s); and a step of growing a III-nitride crystal (10) onto the matrix (1s) and inversion domains (1t) of the undersubstrate (1) by a liquid-phase technique; and is characterized in that a first region (10s), being where the growth rate of III-nitride crystal (10) growing onto the matrix (1s) is greater, covers second regions (10t), being where the growth rate of III-nitride crystal (10) growing onto the inversion domains (1t) is lesser.
    Type: Grant
    Filed: November 15, 2007
    Date of Patent: August 16, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ryu Hirota, Koji Uematsu, Tomohiro Kawase
  • Patent number: 7993947
    Abstract: Highly uniform silica nanoparticles can be formed into stable dispersions with a desirable small secondary particle size. The silican particles can be surface modified to form the dispersions. The silica nanoparticles can be doped to change the particle properties and/or to provide dopant for subsequent transfer to other materials. The dispersions can be printed as an ink for appropriate applications. The dispersions can be used to selectively dope semiconductor materials such as for the formation of photovoltaic cells or for the formation of printed electronic circuits.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: August 9, 2011
    Assignee: NanoGram Corporation
    Inventors: Henry Hieslmair, Shivkumar Chiruvolu, Hui Du