Heat Treatment Patents (Class 438/502)
  • Patent number: 9935228
    Abstract: A solar cell is discussed, and the solar cell includes: a semiconductor substrate; a tunneling layer on a surface of the semiconductor substrate; a buffer layer on the tunneling layer, wherein the buffer layer is a separate layer from the tunneling layer and includes an intrinsic buffer portion, and wherein at least one of a material, a composition and a crystalline structure of the buffer layer is different from those of the tunneling layer; a conductive type region on the tunneling layer, and including a first conductive type region having a first conductive type and a second conductive type region having a second conductive type; and an electrode connected to the conductive type region. The buffer layer is positioned adjacent to the tunneling layer and is apart from the electrode.
    Type: Grant
    Filed: August 19, 2015
    Date of Patent: April 3, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Youngsung Yang, Junghoon Choi, Chungyi Kim
  • Patent number: 9627488
    Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: April 18, 2017
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Toru Hiyoshi, Kosuke Uchida, Takeyoshi Masuda
  • Patent number: 9543168
    Abstract: A symmetric multicycle rapid thermal annealing (SMRTA) method for annealing a semiconductor material without the material decomposing. The SMRTA method includes a first long-time annealing at a first temperature at which the material is thermodynamically stable, followed by multicycle rapid thermal annealing (MRTA) at temperatures at which the material is not thermodynamically stable, followed in turn by a second long-time annealing at a second temperature at which the material is thermodynamically stable. The SMRTA method can be used to form p-type and n-type semiconductor regions in doped III-nitride semiconductors, SiC, and diamond.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: January 10, 2017
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Boris N. Feigelson, Jordan Greenlee, Travis J. Anderson, Francis J. Kub
  • Patent number: 9082687
    Abstract: A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: July 14, 2015
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGY
    Inventors: Maha M. Khayyat, Devendra K. Sadana, Brent A. Wacaser
  • Publication number: 20150122335
    Abstract: Disclosed are an ink composition for manufacturing a light absorption layer including metal nano particles and a method of manufacturing a thin film using the same, more particularly, an ink composition for manufacturing a light absorption layer including copper (Cu)-enriched Cu—In bimetallic metal nano particles and Group IIIA metal particles including S or Se dispersed in a solvent and a method of manufacturing a thin film using the same.
    Type: Application
    Filed: January 6, 2015
    Publication date: May 7, 2015
    Inventors: Seokhee YOON, Seokhyun YOON, Taehun YOON
  • Patent number: 9020002
    Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: April 28, 2015
    Assignee: The Regents of the University of California
    Inventors: Matthew N. Sysak, John E. Bowers, Alexander W. Fang, Hyundai Park
  • Patent number: 8961685
    Abstract: P-type silicon single crystals from which wafers having high resistivity, good radial uniformity of resistivity and less variation in resistivity can be obtained, are manufactured by the Czochralski method from an initial silicon melt in which boron and phosphorus are present, the boron concentration is not higher than 4E14 atoms/cm3 and the ratio of the phosphorus concentration to the boron concentration is not lower than 0.42 and not higher than 0.50.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: February 24, 2015
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Masamichi Ohkubo
  • Patent number: 8951895
    Abstract: Improved complementary doping methods are described herein. The complementary doping methods generally involve inducing a first and second chemical reaction in at least a first and second portion, respectively, of a dopant source, which has been disposed on a thin film of a semiconductor or semimetal material. The chemical reactions result in the introduction of an n-type dopant, a p-type dopant, or both from the dopant source to each of the first and second portions of the thin film of the semiconductor or semimetal. Ultimately, the methods produce at least one n-type and at least one p-type region in the thin film of the semiconductor or semimetal.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: February 10, 2015
    Assignee: Georgia Tech Research Corporation
    Inventors: Kevin Andrew Brenner, Raghunath Murali
  • Patent number: 8946066
    Abstract: A highly reliable transistor which includes an oxide semiconductor and has high field-effect mobility and in which a variation in threshold voltage is small is provided. By using the transistor, a high-performance semiconductor device, which has been difficult to realize, is provided. The transistor includes an oxide semiconductor film which contains two or more kinds, preferably three or more kinds of elements selected from indium, tin, zinc, and aluminum. The oxide semiconductor film is formed in a state where a substrate is heated. Further, oxygen is supplied to the oxide semiconductor film with an adjacent insulating film and/or by ion implantation in a manufacturing process of the transistor, so that oxygen deficiency which generates a carrier is reduced as much as possible. In addition, the oxide semiconductor film is highly purified in the manufacturing process of the transistor, so that the concentration of hydrogen is made extremely low.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Noda, Shunpei Yamazaki, Tatsuya Honda, Yusuke Sekine, Hiroyuki Tomatsu
  • Patent number: 8946062
    Abstract: A method of manufacturing a polycrystalline silicon film includes: depositing a catalyst layer including nickel and depositing nickel nanoparticles on a substrate; exposing the catalyst layer and the nanoparticles to at least silane gas; and heat treating the substrate coated with the catalyst layer and the nanoparticles during at least part of the exposing to silane gas in growing a silicon based film on the substrate.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: February 3, 2015
    Assignee: Guardian Industries Corp.
    Inventors: Vijayen S. Veerasamy, Martin D. Bracamonte
  • Patent number: 8932954
    Abstract: According to one embodiment, an impurity analysis method comprises performing vapor-phase decomposition on a silicon-containing film formed on a substrate, heating the substrate at a first temperature after vapor phase decomposition, heating the substrate at a second temperature higher than the first temperature after heating at the first temperature, to remove a silicon compound deposited on the surface of the silicon-containing film, dropping a recovery solution onto the substrate surface after heating at the second temperature and moving the substrate surface, to recover metal into the recovery solution, and drying the recovery solution, to perform X-ray fluorescence spectrometry on a dried mark.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: January 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuji Yamada, Makiko Katano, Chikashi Takeuchi, Tomoyo Naito
  • Patent number: 8916457
    Abstract: Nanoparticles may be formed on a substrate by mixing precursor solutions deposited by an inkjet printer. A first solution is deposited on a substrate from a first inkjet print cartridge. Then, a second solution is deposited on the substrate from a second inkjet print cartridge. The solutions may be printed in an array of droplets on the substrate. Nanoparticles form when droplets of the first solution overlap with droplets of the second solution. In one example, the nanoparticles may be gold nanoparticles formed from mixing a first solution of 1,2-dichlorobenzene (DCB) and oleylamine and a second solution of gold chloride trihydrite and dimethyl sulfoxide (DMSO). The nanoparticles may be incorporated into optoelectronic devices.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: December 23, 2014
    Assignee: King Abdullah University of Science and Technology
    Inventors: Mutalifu Abulikemu, Ghassan Jabbour
  • Publication number: 20140370694
    Abstract: A method for the manufacture of at least part of a thin-film device including forming one or more indentations in a substrate, preferably a plastic substrate, an indentation having sidewalls and a base; filling at least one of the one or more indentations with a first ink, the first ink having a first material precursor, preferably a first metal-, semiconductor-, or a metal-oxide precursor; and, annealing at least a portion of the first ink such that a surface of the base inside the indentation is dewetted and a narrowed first structure of the first material inside of the indentation is formed.
    Type: Application
    Filed: September 10, 2012
    Publication date: December 18, 2014
    Inventors: Ryoichi Ishihara, Michiel Van Der Zwan
  • Patent number: 8907333
    Abstract: Composite of layers which comprises a dielectric layer and a layer which comprises pyrogenic zinc oxide and is bonded to the dielectric layer. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to the dielectric layer in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm, and the zinc oxide layer is dried and then treated at temperatures of less than 200° C. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to a substrate layer or a composite of substrate layers in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm to form a zinc oxide layer, and then the zinc oxide layer and the substrate layer are treated at temperatures of less than 200° C., and then a dielectric layer is applied to the zinc oxide layer. Field-effect transistor which has the composite of layers.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: December 9, 2014
    Assignees: Evonik Degussa GmbH, Forschungszentrum Karlsruhe GmbH
    Inventors: Frank-Martin Petrat, Heiko Thiem, Sven Hill, Andre Ebbers, Koshi Okamura, Roland Schmechel
  • Patent number: 8900961
    Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ashima B. Chakravarti, Anthony I. Chou, Toshiharu Furukawa, Steven J. Holmes, Wesley C. Natzle
  • Publication number: 20140335649
    Abstract: A compound semiconductor precursor ink composition includes an ink composition for forming a chalcogenide semiconductor film and a peroxide compound mixed with the ink composition. A method for forming a chalcogenide semiconductor film and a method for forming a photovoltaic device each include using the compound semiconductor precursor ink composition containing peroxide compound to form a chalcogenide semiconductor film.
    Type: Application
    Filed: May 9, 2013
    Publication date: November 13, 2014
    Inventors: Feng-Yu Yang, Ching Ting, Yueh-Chun Liao
  • Patent number: 8883617
    Abstract: One aspect in the present disclosure relates to a method for manufacturing an amorphous metal oxide semiconductor. In an exemplary embodiment, a film is deposited on a substrate from a mixed solution as a starting element. For example, the mixed solution includes at least an indium alkoxide and a zinc alkoxide in a solvent. The film made from the mixed solution on the substrate is cured by thermal-annealing in a water vapor atmosphere, at a temperature range of, for example, 210 to 275 degrees Celsius, inclusive.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: November 11, 2014
    Assignees: Panasonic Corporation, Cambridge Enterprise Ltd.
    Inventors: Yoshihisa Yamashita, Kulbinder Kumar Banger, Henning Sirringhaus
  • Patent number: 8874254
    Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: October 28, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shuji Iwanaga, Nobuyuki Sata
  • Patent number: 8846505
    Abstract: A method for growing islands of semiconductor monocrystals from a solution on an amorphous substrate includes the procedures of depositing a semiconductor-metal mixture layer, applying lithography and etching for forming at least one platform, heating the at least one platform, and saturating the semiconductor-metal solution until a monocrystal of the semiconductor component is formed. The procedure of depositing a semiconductor-metal mixture layer, includes a semiconductor component and at least one other metal component, is performed on top of the amorphous substrate. The procedure of applying lithography and etching to the semiconductor-metal mixture layer and a portion of the amorphous substrate is performed for forming at least one platform, the at least one platform having a top view shape corresponding to crystal growth direction and habit respective of the semiconductor component.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: September 30, 2014
    Assignee: SKOKIE Swift Corporation
    Inventor: Moshe Einav
  • Patent number: 8846507
    Abstract: Compositions and methods for controlled polymerization and/or oligomerization of hydrosilanes compounds including those of the general formulae SinH2n and SinH2n+2 as well as alkyl- and arylsilanes, to produce soluble silicon polymers as a precursor to silicon films having low carbon content.
    Type: Grant
    Filed: May 17, 2013
    Date of Patent: September 30, 2014
    Assignee: Thin Film Electronics ASA
    Inventors: Dmitry Karshtedt, Joerg Rockenberger, Fabio Zurcher, Brent Ridley, Erik Scher
  • Publication number: 20140287572
    Abstract: A manufacturing method of MIS (Metal Insulator Semiconductor)-type semiconductor device includes the steps of; forming a zirconium oxynitride (ZrON) layer; forming an electrode layer containing titanium nitride (TiN) on the zirconium oxynitride (ZrON) layer; and heating the electrode layer.
    Type: Application
    Filed: February 3, 2014
    Publication date: September 25, 2014
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Kiyotaka MIZUKAMI, Takahiro Sonoyama, Toru Oka, Junya Nishii
  • Publication number: 20140264377
    Abstract: According to one embodiment, a photoconductive semiconductor switch includes a structure of nanopowder of a high band gap material, where the nanopowder is optically transparent, and where the nanopowder has a physical characteristic of formation from a sol-gel process. According to another embodiment, a method includes mixing a sol-gel precursor compound, a hydroxy benzene and an aldehyde in a solvent thereby creating a mixture, causing the mixture to gel thereby forming a wet gel, drying the wet gel to form a nanopowder, and applying a thermal treatment to form a SiC nanopowder.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: LAWRENCE LIVERMORE NATIONAL SECURITY, LLC
    Inventors: Richard L. Landingham, Joe Satcher, Jr., Robert Reibold
  • Patent number: 8829652
    Abstract: A light emitting device with graded composition hole tunneling layer is provided. The device comprises a substrate and an n-type semiconductor layer is disposed on the substrate, in which the n-type semiconductor layer comprises a first portion and a second portion. A graded composition hole tunneling layer is disposed on the first portion of the n-type semiconductor layer. An electron blocking layer is disposed on the graded composition hole tunneling layer. A p-type semiconductor layer is disposed on the electron blocking layer. A first electrode is disposed on the p-type semiconductor layer, and a second electrode is disposed on the second portion of the n-type semiconductor layer and is electrical insulated from the first portion of the n-type semiconductor. The graded composition hole tunneling layer is used as the quantum-well to improve the transport efficiency of the holes to increase the light emitting efficiency of the light emitting device.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: September 9, 2014
    Assignee: National Chiao Tung University
    Inventors: Chao-Hsun Wang, Hao-Chung Kuo
  • Patent number: 8778785
    Abstract: There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes the steps of providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of ?25 to 80° C. and under a vacuum in the range of 10?6 to 1,000 Torr, for a first period of 1-100 minutes, to form a partially dried layer; and heating the partially dried layer to a temperature above 100° C. for a second period of 1-50 minutes to form a dried layer.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: July 15, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Reid John Chesterfield, Nugent Truong, Jeffrey A. Merlo, Adam Fennimore, Jonathan M. Ziebarth
  • Patent number: 8778708
    Abstract: There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes: providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of ?25 to 80° C. and under a vacuum in the range of 10?6 to 1,000 Torr, for a first period of 1-100 minutes, to form a partially dried layer; heating the partially dried layer to a temperature above 100° C. for a second period of 1-50 minutes to form a dried layer.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: July 15, 2014
    Assignee: E I du Pont de Nemours and Company
    Inventors: Reid John Chesterfield, Justin Butler, Paul Anthony Sant
  • Patent number: 8759199
    Abstract: A method of selectively growing a plurality of semiconductor carbon nanotubes using light irradiation. The method includes disposing a plurality of nanodots, which include a catalyst material, on a substrate; growing a plurality of carbon nanotubes from the plurality of nanodots, and irradiating light onto the nanodot to selectively grow the plurality of semiconductor carbon nanotubes.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: June 24, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-mook Choi, Jae-young Choi, Jin Zhang, Guo Hong
  • Publication number: 20140170841
    Abstract: The present invention provides a silicon carbide semiconductor device having an ohmic electrode improved in adhesion of a wire thereto by preventing deposition of carbon so as not to form a Schottky contact, as well as a method for manufacturing such a silicon carbide semiconductor device. In the SiC semiconductor device, upon forming the ohmic electrode, a first metal layer made of one first metallic element is formed on one main surface of a SiC layer. Further, a Si layer made of Si is formed on an opposite surface of the first metal layer to its surface facing the SiC layer. The stacked structure thus formed is subjected to thermal treatment. In this way, there can be obtained a silicon carbide semiconductor device having an ohmic electrode adhered well to a wire by preventing deposition of carbon atoms on the surface layer of the electrode and formation of a Schottky contact resulting from Si and SiC.
    Type: Application
    Filed: January 29, 2014
    Publication date: June 19, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Hideto Tamaso
  • Patent number: 8709858
    Abstract: The present invention relates to a method for decreasing or increasing the band gap shift in the production of photovoltaic devices by means of coating a substrate with a formulation containing a silicon compound, e.g., in the production of a solar cell comprising a step in which a substrate is coated with a liquid-silane formulation, the invention being characterized in that the formulation also contains at least one germanium compound. The invention further relates to the method for producing such a photovoltaic device.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: April 29, 2014
    Assignee: Evonik Degussa GmbH
    Inventors: Bernhard Stuetzel, Wolfgang Fahrner
  • Patent number: 8673401
    Abstract: A method for depositing gallium using a gallium ink, comprising, as initial components: a gallium component comprising gallium; a stabilizing component; an additive; and, a liquid carrier; is provided comprising applying the gallium ink on the substrate; heating the applied gallium ink to eliminate the additive and the liquid carrier, depositing gallium on the substrate; and, optionally, annealing the deposited gallium.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: March 18, 2014
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: David Mosley, David Thorsen
  • Publication number: 20140051237
    Abstract: A representative printable composition comprises a liquid or gel suspension of a plurality of substantially spherical semiconductor particles; and a first solvent comprising a polyol or mixtures thereof, such as glycerin; and a second solvent different from the first solvent, the second solvent comprising a carboxylic or dicarboxylic acid or mixtures thereof, such as glutaric acid. The composition may further comprise a third solvent such as tetramethylurea, butanol, or isopropanol. In various embodiments, the plurality of substantially spherical semiconductor particles have a size in any dimension between about 5 nm and about 100?. A representative composition can be printed and utilized to produce diodes, such as photovoltaic diodes or light emitting diodes.
    Type: Application
    Filed: August 16, 2012
    Publication date: February 20, 2014
    Applicant: NTHDEGREE TECHNOLOGIES WORLDWIDE INC.
    Inventors: Vera Nicholaevna Lockett, Mark David Lowenthal, Neil O. Shotton, William Johnstone Ray, Tricia Youngbull, Theodore I. Kamins
  • Publication number: 20140035103
    Abstract: Provided is a high-quality Group III nitride crystal of excellent processability. A Group III nitride crystal is produced by forming a film is composed of an oxide, hydroxide and/or oxyhydroxide containing a Group III element by heat-treating a Group III nitride single crystal at 1000° C. or above, and removing the film.
    Type: Application
    Filed: October 15, 2013
    Publication date: February 6, 2014
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Hajime MATSUMOTO, Kunitada SUZAKI, Kenji FUJITO, Satoru NAGAO
  • Patent number: 8642455
    Abstract: Methods and devices are provided for transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that of the feedstock or precursor materials, even after selective forces settling. In particular, planar particles disperse more easily, form much denser coatings (or form coatings with more interparticle contact area), and anneal into fused, dense films at a lower temperature and/or time than their counterparts made from spherical nanoparticles. These planar particles may be nanoflakes that have a high aspect ratio. The resulting dense films formed from nanoflakes are particularly useful in forming photovoltaic devices.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: February 4, 2014
    Inventors: Matthew R. Robinson, Jeroen K. J. Van Duren, Craig Leidholm, Brian M. Sager
  • Patent number: 8633040
    Abstract: The invention can be used for producing different luminescent materials and as a basis for producing subminiature light-emitting diodes, white light sources, single-electron transistors, nonlinear optical devices and photosensitive and photovoltaic devices. The inventive method for producing semiconductor quantum dots involves synthesizing nanocrystal nuclei from a chalcogen-containing precursor and a precursor containing a group II or IV metal using an organic solvent and a surface modifier. The method is characterized in that (aminoalkyl)trialkoxysilanes are used as the surface modifier, core synthesis is carried out at a permanent temperature ranging from 150 to 250 C for 15 seconds to 1 hour and in that the reaction mixture containing the nanocrystal is additionally treated by UV-light for 1-10 minutes and by ultrasound for 5-15 minutes.
    Type: Grant
    Filed: August 18, 2009
    Date of Patent: January 21, 2014
    Assignee: The “Nanotech-Dubna” Trial Center for Science and Technology
    Inventors: Roman Vladimirovich Novichkov, Maxim Sergeevich Wakstein, Ekaterina Leonidovna Nodova, Aleksey Olegovich Maniashin, Irina Ivanovna Taraskina
  • Patent number: 8617947
    Abstract: A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: December 31, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-kyu Yang, Phil-ouk Nam, Ki-hyun Hwang, Jae-young Ahn, Han-mei Choi, Bi-o Kim
  • Patent number: 8598023
    Abstract: There is disclosed a substrate processing apparatus including a processing chamber housing a substrate, pipes for supplying gas into the processing chamber, and heaters provided in the middle of the pipes, and heating the gas. In the substrate processing apparatus, the heaters heat the gas to a temperature lower than a temperature at which exhaust gas is generated from the pipes to dry the substrate in the heated gas.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 3, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Tomokazu Kawamoto
  • Publication number: 20130312831
    Abstract: Techniques for enhancing energy conversion efficiency in chalcogenide-based photovoltaic devices by improved grain structure and film morphology through addition of urea into a liquid-based precursor are provided. In one aspect, a method of forming a chalcogenide film includes the following steps. Metal chalcogenides are contacted in a liquid medium to form a solution or a dispersion, wherein the metal chalcogenides include a Cu chalcogenide, an M1 and an M2 chalcogenide, and wherein M1 and M2 each include an element selected from the group consisting of: Ag, Mn, Mg, Fe, Co, Cd, Ni, Cr, Zn, Sn, In, Ga, Al, and Ge. At least one organic additive is contacted with the metal chalcogenides in the liquid medium. The solution or the dispersion is deposited onto a substrate to form a layer. The layer is annealed at a temperature, pressure and for a duration sufficient to form the chalcogenide film.
    Type: Application
    Filed: June 1, 2012
    Publication date: November 28, 2013
    Applicant: International Business Machines Corporation
    Inventors: David Brian Mitzi, Xiaofeng Qiu
  • Patent number: 8592243
    Abstract: A method for forming a buffer layer in a dye-sensitized solar cell including a transparent electrode, a counter electrode, an electrolyte layer disposed between the electrodes, and a photocatalyst film disposed between the electrodes and near the transparent electrode, the buffer layer being disposed between the transparent electrode and photocatalyst film, the method including: forming the buffer layer by sintering a mixed solution of an alcohol solution and 0.03% to 5% by mass of metal alkoxide by laser beam irradiation after applying the mixed solution to the surface of the transparent electrode by spin coating, the transparent electrode being rotated by a rotating table.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: November 26, 2013
    Assignee: Hitachi Zosen Corporation
    Inventors: Takeshi Sugiyo, Tetsuya Inoue
  • Patent number: 8559478
    Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: October 15, 2013
    Assignee: The Regents of the University of California
    Inventors: Matthew N. Sysak, John E. Bowers, Alexander W. Fang, Hyundai Park
  • Publication number: 20130252407
    Abstract: Compositions and methods for controlled polymerization and/or oligomerization of hydrosilanes compounds including those of the general formulae SinH2n and SinH2n+2 as well as alkyl- and arylsilanes, to produce soluble silicon polymers as a precursor to silicon films having low carbon content.
    Type: Application
    Filed: May 17, 2013
    Publication date: September 26, 2013
    Inventors: Dmitry KARSHTEDT, Joerg ROCKENBERGER, Fabio ZURCHER, Brent RIDLEY, Erik SCHER
  • Patent number: 8518808
    Abstract: A GaN sample in a sealed enclosure is heated very fast to a high temperature above the point where GaN is thermodynamically stable and is then cooled down very fast to a temperature where it is thermodynamically stable. The time of the GaN exposure to a high temperature range above its thermodynamic stability is sufficiently short, in a range of few seconds, to prevent the GaN from decomposing. This heating and cooling cycle is repeated multiple times without removing the sample from the enclosure. As a result, by accumulating the exposure time in each cycle, the GaN sample can be exposed to a high temperature above its point of thermodynamic stability for a long time but the GaN sample integrity is maintained (i.e., the GaN doesn't decompose) due to the extremely short heating duration of each single cycle.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: August 27, 2013
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Boris N. Feigelson, Travis Anderson, Francis J. Kub
  • Patent number: 8486753
    Abstract: Disclosed are a patterning method of a metal oxide thin film using nanoimprinting, and a manufacturing method of a light emitting diode (LED). The method for forming a metal oxide thin film pattern using nanoimprinting includes: coating a photosensitive metal-organic material precursor solution on a substrate; preparing a mold patterned to have a protrusion and depression structure; pressurizing the photosensitive metal-organic material precursor coating layer with the patterned mold; forming a cured metal oxide thin film pattern by heating the pressurized photosensitive metal-organic material precursor coating layer or by irradiating ultraviolet rays to the pressurized photosensitive metal-organic material precursor coating layer while being heated; and removing the patterned mold from the metal oxide thin film pattern, and selectively further includes annealing the metal oxide thin film pattern.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: July 16, 2013
    Assignee: Korea Institute of Machinery and Materials
    Inventors: Hyeong Ho Park, Jun Ho Jeong, Ki Don Kim, Dae Geun Choi, Jun Hyuk Choi, Ji Hye Lee, Soon Won Lee
  • Publication number: 20130161793
    Abstract: Silicon single crystal substrates having uniform resistance, few BMDs in a surface layer and a moderate number of BMDs in a center of thickness of the substrate are formed from Czochralski silicon single crystals. The substrates have a resistivity in the center of a first main surface not lower than 50 ?·cm and a rate of change in resistivity in the first main surface not higher than 3%, an average density of bulk micro defects in a region between the first main surface and a plane at a depth of 50 ?m of less than 1×108/cm3, and an average density of bulk micro defects in a region lying between a plane at a depth of 300 ?m and a plane at a depth of 400 ?m from the first main surface not lower than 1×108 /cm3 and not higher than 1×109 /cm3.
    Type: Application
    Filed: September 12, 2012
    Publication date: June 27, 2013
    Applicant: SILTRONIC AG
    Inventors: Katsuhiko Nakai, Masamichi Ohkubo, Hikaru Sakamoto
  • Patent number: 8470626
    Abstract: Exemplary embodiments of the present invention relate to a method of fabricating a light emitting diode (LED). According to an exemplary embodiment of the present invention, the method includes growing a first GaN-based semiconductor layer on a substrate at a first temperature by supplying a chamber with a nitride source gas and a first metal source gas, stopping the supply of the first metal source gas and maintaining the first temperature for a first time period after stopping the supply of the first metal source gas, decreasing the temperature of the substrate to the a second temperature after the first time period elapses, growing an active layer of the first GaN-based semiconductor layer at the second temperature by supplying the chamber with a second metal source gas.
    Type: Grant
    Filed: June 1, 2011
    Date of Patent: June 25, 2013
    Assignee: Seoul Opto Device Co., Ltd.
    Inventors: Kwang Joong Kim, Chang Suk Han, Seung Kyu Choi, Ki Bum Nam, Nam Yoon Kim, Kyung Hae Kim, Ju Hyung Yoon
  • Patent number: 8470636
    Abstract: The present invention relates to aqueous processes to make metal chalcogenide nanoparticles that are useful precursors to copper zinc tin sulfide/selenide and copper tin sulfide/selenide. In addition, this invention provides processes for preparing crystalline particles from the metal chalcogenide nanoparticles, as well as processes for preparing inks from both the metal chalcogenide nanoparticles and the crystalline particles.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: June 25, 2013
    Assignee: E I du Pont de Nemours and Company
    Inventors: Daniela Rodica Radu, Lynda Kaye Johnson, Cheng-Yu Lai, Meijun Lu, Irina Malajovich
  • Patent number: 8461031
    Abstract: A method for making a thin-film structure includes a thin film stabilized on a substrate. The structure of the thin film is defined by a material which includes at least one first chemical species. The method includes a step of inputting particles of the first chemical species into the thin film so as to compensate for the flow of vacancies from the surface of the film.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: June 11, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Joël Eymery, Pascal Pochet
  • Patent number: 8460983
    Abstract: Doped semiconductor ink formulations, methods of making doped semiconductor ink formulations, methods of coating or printing thin films, methods of forming electronic devices and/or structures from the thin films, and methods for modifying and controlling the threshold voltage of a thin film transistor using the films are disclosed. A desired dopant may be added to an ink formulation comprising a Group IVA compound and a solvent, and then the ink may be printed on a substrate to form thin films and conductive structures/devices, such as thin film transistors. By adding a customized amount of the dopant to the ink prior to printing, the threshold voltage of a thin film transistor made from the doped semiconductor ink may be independently controlled upon activation of the dopant.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: June 11, 2013
    Assignee: Kovio, Inc.
    Inventors: Wenzhuo Guo, Fabio Zürcher, Arvind Kamath, Joerg Rockenberger
  • Patent number: 8455346
    Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: June 4, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiro Nojiri, Hiroyuki Fukumizu, Shinichi Nakao, Kei Watanabe, Kazuhiko Yamamoto, Ichiro Mizushima, Yoshio Ozawa
  • Patent number: 8426297
    Abstract: A method of manufacturing a silicon wafer, an oxygen concentration in a surface layer to be maintained more than a predetermined value while promoting a defect-free layer. Strength of the surface layer can be made higher than that of an ordinary annealed sample as a COP free zone is secured. A method of manufacturing a silicon wafer doped with nitrogen and oxygen, includes growing a single crystal silicon doped with the nitrogen by Czochralski method, slicing the grown single crystal silicon to obtain a single crystal silicon wafer; heat treating the sliced single crystal silicon wafer in an ambient gas including a hydrogen gas and/or an inert gas; polishing the heat treated single crystal silicon wafer, after the heat treatment, such that an obtained surface layer from which COP defects have been removed by the heat treatment is polished away until an outermost surface has a predetermined oxygen concentration.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: April 23, 2013
    Assignee: Sumco Techxiv Corporation
    Inventor: Shinya Sadohara
  • Patent number: 8372734
    Abstract: Methods and devices are provided for transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that of the feedstock or precursor materials, even after selective forces settling. In particular, planar particles disperse more easily, form much denser coatings (or form coatings with more interparticle contact area), and anneal into fused, dense films at a lower temperature and/or time than their counterparts made from spherical nanoparticles. These planar particles may be nanoflakes that have a high aspect ratio. The resulting dense films formed from nanoflakes are particularly useful in forming photovoltaic devices. In one embodiment, at least one set of the particles in the ink may be inter-metallic flake particles (microflake or nanoflake) containing at least one group IB-IIIA inter-metallic alloy phase.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: February 12, 2013
    Assignee: Nanosolar, Inc
    Inventors: Jeroen K. J. Van Duren, Matthew R. Robinson, Brian M. Sager
  • Patent number: 8372485
    Abstract: A gallium ink is provided, comprising, as initial components: a gallium component comprising gallium; a stabilizing component; an additive; and, a liquid carrier; wherein the gallium ink is a stable dispersion. Also provided are methods of preparing the gallium ink and for using the gallium ink in the preparation of semiconductor films (e.g., in the deposition of a CIGS layer for use in photovoltaic devices).
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: February 12, 2013
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: David Mosley, David Thorsen