Heat Treatment Patents (Class 438/502)
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Patent number: 12090687Abstract: A method of creating a polymer surface with surface structures is disclosed. The method includes creating a mold, forming a metal sheet into the molds, creating a surface structure on a surface of the metal sheet by exposing the surface to laser pulses, and bringing a curable polymer to be in contact with the surface of the metal sheet containing the surface structure, curing the curable polymer, and separating the cured polymer from the metal sheet, resulting in a polymer surface containing the surface structure. The polymer surfaces with the surface structures can be hydrophobic or superhydrophobic depending on the micro and nano features contained by the surface structures.Type: GrantFiled: December 24, 2020Date of Patent: September 17, 2024Assignee: Purdue Research FoundationInventors: Yung C. Shin, Shashank Sarbada
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Patent number: 9935228Abstract: A solar cell is discussed, and the solar cell includes: a semiconductor substrate; a tunneling layer on a surface of the semiconductor substrate; a buffer layer on the tunneling layer, wherein the buffer layer is a separate layer from the tunneling layer and includes an intrinsic buffer portion, and wherein at least one of a material, a composition and a crystalline structure of the buffer layer is different from those of the tunneling layer; a conductive type region on the tunneling layer, and including a first conductive type region having a first conductive type and a second conductive type region having a second conductive type; and an electrode connected to the conductive type region. The buffer layer is positioned adjacent to the tunneling layer and is apart from the electrode.Type: GrantFiled: August 19, 2015Date of Patent: April 3, 2018Assignee: LG ELECTRONICS INC.Inventors: Youngsung Yang, Junghoon Choi, Chungyi Kim
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Patent number: 9627488Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. A silicon carbide substrate is prepared. A first heating step of heating the silicon carbide substrate in an atmosphere of oxygen is performed. A second heating step of heating the silicon carbide substrate to a temperature of 1300° C. or more and 1500° C. or less in an atmosphere of gas containing nitrogen atoms or phosphorus atoms is performed after the first heating step. A third heating step of heating the silicon carbide substrate in an atmosphere of a first inert gas is performed after the second heating step. Thus, the silicon carbide semiconductor device in which threshold voltage variation is small, and a method for manufacturing the same can be provided.Type: GrantFiled: July 14, 2016Date of Patent: April 18, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Toru Hiyoshi, Kosuke Uchida, Takeyoshi Masuda
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Patent number: 9543168Abstract: A symmetric multicycle rapid thermal annealing (SMRTA) method for annealing a semiconductor material without the material decomposing. The SMRTA method includes a first long-time annealing at a first temperature at which the material is thermodynamically stable, followed by multicycle rapid thermal annealing (MRTA) at temperatures at which the material is not thermodynamically stable, followed in turn by a second long-time annealing at a second temperature at which the material is thermodynamically stable. The SMRTA method can be used to form p-type and n-type semiconductor regions in doped III-nitride semiconductors, SiC, and diamond.Type: GrantFiled: February 4, 2016Date of Patent: January 10, 2017Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Boris N. Feigelson, Jordan Greenlee, Travis J. Anderson, Francis J. Kub
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Patent number: 9082687Abstract: A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.Type: GrantFiled: July 23, 2012Date of Patent: July 14, 2015Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, KING ABDULAZIZ CITY FOR SCIENCE AND TECHNOLOGYInventors: Maha M. Khayyat, Devendra K. Sadana, Brent A. Wacaser
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Publication number: 20150122335Abstract: Disclosed are an ink composition for manufacturing a light absorption layer including metal nano particles and a method of manufacturing a thin film using the same, more particularly, an ink composition for manufacturing a light absorption layer including copper (Cu)-enriched Cu—In bimetallic metal nano particles and Group IIIA metal particles including S or Se dispersed in a solvent and a method of manufacturing a thin film using the same.Type: ApplicationFiled: January 6, 2015Publication date: May 7, 2015Inventors: Seokhee YOON, Seokhyun YOON, Taehun YOON
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Patent number: 9020002Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate.Type: GrantFiled: September 13, 2013Date of Patent: April 28, 2015Assignee: The Regents of the University of CaliforniaInventors: Matthew N. Sysak, John E. Bowers, Alexander W. Fang, Hyundai Park
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Patent number: 8961685Abstract: P-type silicon single crystals from which wafers having high resistivity, good radial uniformity of resistivity and less variation in resistivity can be obtained, are manufactured by the Czochralski method from an initial silicon melt in which boron and phosphorus are present, the boron concentration is not higher than 4E14 atoms/cm3 and the ratio of the phosphorus concentration to the boron concentration is not lower than 0.42 and not higher than 0.50.Type: GrantFiled: November 10, 2011Date of Patent: February 24, 2015Assignee: Siltronic AGInventors: Katsuhiko Nakai, Masamichi Ohkubo
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Patent number: 8951895Abstract: Improved complementary doping methods are described herein. The complementary doping methods generally involve inducing a first and second chemical reaction in at least a first and second portion, respectively, of a dopant source, which has been disposed on a thin film of a semiconductor or semimetal material. The chemical reactions result in the introduction of an n-type dopant, a p-type dopant, or both from the dopant source to each of the first and second portions of the thin film of the semiconductor or semimetal. Ultimately, the methods produce at least one n-type and at least one p-type region in the thin film of the semiconductor or semimetal.Type: GrantFiled: November 30, 2010Date of Patent: February 10, 2015Assignee: Georgia Tech Research CorporationInventors: Kevin Andrew Brenner, Raghunath Murali
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Polycrystalline silicon thick films for photovoltaic devices or the like, and methods of making same
Patent number: 8946062Abstract: A method of manufacturing a polycrystalline silicon film includes: depositing a catalyst layer including nickel and depositing nickel nanoparticles on a substrate; exposing the catalyst layer and the nanoparticles to at least silane gas; and heat treating the substrate coated with the catalyst layer and the nanoparticles during at least part of the exposing to silane gas in growing a silicon based film on the substrate.Type: GrantFiled: November 21, 2012Date of Patent: February 3, 2015Assignee: Guardian Industries Corp.Inventors: Vijayen S. Veerasamy, Martin D. Bracamonte -
Patent number: 8946066Abstract: A highly reliable transistor which includes an oxide semiconductor and has high field-effect mobility and in which a variation in threshold voltage is small is provided. By using the transistor, a high-performance semiconductor device, which has been difficult to realize, is provided. The transistor includes an oxide semiconductor film which contains two or more kinds, preferably three or more kinds of elements selected from indium, tin, zinc, and aluminum. The oxide semiconductor film is formed in a state where a substrate is heated. Further, oxygen is supplied to the oxide semiconductor film with an adjacent insulating film and/or by ion implantation in a manufacturing process of the transistor, so that oxygen deficiency which generates a carrier is reduced as much as possible. In addition, the oxide semiconductor film is highly purified in the manufacturing process of the transistor, so that the concentration of hydrogen is made extremely low.Type: GrantFiled: May 2, 2012Date of Patent: February 3, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kosei Noda, Shunpei Yamazaki, Tatsuya Honda, Yusuke Sekine, Hiroyuki Tomatsu
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Patent number: 8932954Abstract: According to one embodiment, an impurity analysis method comprises performing vapor-phase decomposition on a silicon-containing film formed on a substrate, heating the substrate at a first temperature after vapor phase decomposition, heating the substrate at a second temperature higher than the first temperature after heating at the first temperature, to remove a silicon compound deposited on the surface of the silicon-containing film, dropping a recovery solution onto the substrate surface after heating at the second temperature and moving the substrate surface, to recover metal into the recovery solution, and drying the recovery solution, to perform X-ray fluorescence spectrometry on a dried mark.Type: GrantFiled: August 24, 2012Date of Patent: January 13, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yuji Yamada, Makiko Katano, Chikashi Takeuchi, Tomoyo Naito
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Patent number: 8916457Abstract: Nanoparticles may be formed on a substrate by mixing precursor solutions deposited by an inkjet printer. A first solution is deposited on a substrate from a first inkjet print cartridge. Then, a second solution is deposited on the substrate from a second inkjet print cartridge. The solutions may be printed in an array of droplets on the substrate. Nanoparticles form when droplets of the first solution overlap with droplets of the second solution. In one example, the nanoparticles may be gold nanoparticles formed from mixing a first solution of 1,2-dichlorobenzene (DCB) and oleylamine and a second solution of gold chloride trihydrite and dimethyl sulfoxide (DMSO). The nanoparticles may be incorporated into optoelectronic devices.Type: GrantFiled: May 22, 2013Date of Patent: December 23, 2014Assignee: King Abdullah University of Science and TechnologyInventors: Mutalifu Abulikemu, Ghassan Jabbour
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Publication number: 20140370694Abstract: A method for the manufacture of at least part of a thin-film device including forming one or more indentations in a substrate, preferably a plastic substrate, an indentation having sidewalls and a base; filling at least one of the one or more indentations with a first ink, the first ink having a first material precursor, preferably a first metal-, semiconductor-, or a metal-oxide precursor; and, annealing at least a portion of the first ink such that a surface of the base inside the indentation is dewetted and a narrowed first structure of the first material inside of the indentation is formed.Type: ApplicationFiled: September 10, 2012Publication date: December 18, 2014Inventors: Ryoichi Ishihara, Michiel Van Der Zwan
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Patent number: 8907333Abstract: Composite of layers which comprises a dielectric layer and a layer which comprises pyrogenic zinc oxide and is bonded to the dielectric layer. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to the dielectric layer in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm, and the zinc oxide layer is dried and then treated at temperatures of less than 200° C. Process for producing the composite of layers, in which the pyrogenic zinc oxide is applied to a substrate layer or a composite of substrate layers in the form of a dispersion in which the zinc oxide particles are present with a mean aggregate diameter of less than 200 nm to form a zinc oxide layer, and then the zinc oxide layer and the substrate layer are treated at temperatures of less than 200° C., and then a dielectric layer is applied to the zinc oxide layer. Field-effect transistor which has the composite of layers.Type: GrantFiled: March 10, 2008Date of Patent: December 9, 2014Assignees: Evonik Degussa GmbH, Forschungszentrum Karlsruhe GmbHInventors: Frank-Martin Petrat, Heiko Thiem, Sven Hill, Andre Ebbers, Koshi Okamura, Roland Schmechel
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Patent number: 8900961Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.Type: GrantFiled: October 19, 2010Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Anthony I. Chou, Toshiharu Furukawa, Steven J. Holmes, Wesley C. Natzle
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Publication number: 20140335649Abstract: A compound semiconductor precursor ink composition includes an ink composition for forming a chalcogenide semiconductor film and a peroxide compound mixed with the ink composition. A method for forming a chalcogenide semiconductor film and a method for forming a photovoltaic device each include using the compound semiconductor precursor ink composition containing peroxide compound to form a chalcogenide semiconductor film.Type: ApplicationFiled: May 9, 2013Publication date: November 13, 2014Inventors: Feng-Yu Yang, Ching Ting, Yueh-Chun Liao
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Patent number: 8883617Abstract: One aspect in the present disclosure relates to a method for manufacturing an amorphous metal oxide semiconductor. In an exemplary embodiment, a film is deposited on a substrate from a mixed solution as a starting element. For example, the mixed solution includes at least an indium alkoxide and a zinc alkoxide in a solvent. The film made from the mixed solution on the substrate is cured by thermal-annealing in a water vapor atmosphere, at a temperature range of, for example, 210 to 275 degrees Celsius, inclusive.Type: GrantFiled: September 11, 2012Date of Patent: November 11, 2014Assignees: Panasonic Corporation, Cambridge Enterprise Ltd.Inventors: Yoshihisa Yamashita, Kulbinder Kumar Banger, Henning Sirringhaus
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Patent number: 8874254Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.Type: GrantFiled: July 11, 2011Date of Patent: October 28, 2014Assignee: Tokyo Electron LimitedInventors: Shuji Iwanaga, Nobuyuki Sata
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Patent number: 8846507Abstract: Compositions and methods for controlled polymerization and/or oligomerization of hydrosilanes compounds including those of the general formulae SinH2n and SinH2n+2 as well as alkyl- and arylsilanes, to produce soluble silicon polymers as a precursor to silicon films having low carbon content.Type: GrantFiled: May 17, 2013Date of Patent: September 30, 2014Assignee: Thin Film Electronics ASAInventors: Dmitry Karshtedt, Joerg Rockenberger, Fabio Zurcher, Brent Ridley, Erik Scher
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Patent number: 8846505Abstract: A method for growing islands of semiconductor monocrystals from a solution on an amorphous substrate includes the procedures of depositing a semiconductor-metal mixture layer, applying lithography and etching for forming at least one platform, heating the at least one platform, and saturating the semiconductor-metal solution until a monocrystal of the semiconductor component is formed. The procedure of depositing a semiconductor-metal mixture layer, includes a semiconductor component and at least one other metal component, is performed on top of the amorphous substrate. The procedure of applying lithography and etching to the semiconductor-metal mixture layer and a portion of the amorphous substrate is performed for forming at least one platform, the at least one platform having a top view shape corresponding to crystal growth direction and habit respective of the semiconductor component.Type: GrantFiled: March 9, 2010Date of Patent: September 30, 2014Assignee: SKOKIE Swift CorporationInventor: Moshe Einav
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Publication number: 20140287572Abstract: A manufacturing method of MIS (Metal Insulator Semiconductor)-type semiconductor device includes the steps of; forming a zirconium oxynitride (ZrON) layer; forming an electrode layer containing titanium nitride (TiN) on the zirconium oxynitride (ZrON) layer; and heating the electrode layer.Type: ApplicationFiled: February 3, 2014Publication date: September 25, 2014Applicant: TOYODA GOSEI CO., LTD.Inventors: Kiyotaka MIZUKAMI, Takahiro Sonoyama, Toru Oka, Junya Nishii
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Publication number: 20140264377Abstract: According to one embodiment, a photoconductive semiconductor switch includes a structure of nanopowder of a high band gap material, where the nanopowder is optically transparent, and where the nanopowder has a physical characteristic of formation from a sol-gel process. According to another embodiment, a method includes mixing a sol-gel precursor compound, a hydroxy benzene and an aldehyde in a solvent thereby creating a mixture, causing the mixture to gel thereby forming a wet gel, drying the wet gel to form a nanopowder, and applying a thermal treatment to form a SiC nanopowder.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: LAWRENCE LIVERMORE NATIONAL SECURITY, LLCInventors: Richard L. Landingham, Joe Satcher, Jr., Robert Reibold
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Patent number: 8829652Abstract: A light emitting device with graded composition hole tunneling layer is provided. The device comprises a substrate and an n-type semiconductor layer is disposed on the substrate, in which the n-type semiconductor layer comprises a first portion and a second portion. A graded composition hole tunneling layer is disposed on the first portion of the n-type semiconductor layer. An electron blocking layer is disposed on the graded composition hole tunneling layer. A p-type semiconductor layer is disposed on the electron blocking layer. A first electrode is disposed on the p-type semiconductor layer, and a second electrode is disposed on the second portion of the n-type semiconductor layer and is electrical insulated from the first portion of the n-type semiconductor. The graded composition hole tunneling layer is used as the quantum-well to improve the transport efficiency of the holes to increase the light emitting efficiency of the light emitting device.Type: GrantFiled: July 17, 2012Date of Patent: September 9, 2014Assignee: National Chiao Tung UniversityInventors: Chao-Hsun Wang, Hao-Chung Kuo
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Patent number: 8778785Abstract: There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes the steps of providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of ?25 to 80° C. and under a vacuum in the range of 10?6 to 1,000 Torr, for a first period of 1-100 minutes, to form a partially dried layer; and heating the partially dried layer to a temperature above 100° C. for a second period of 1-50 minutes to form a dried layer.Type: GrantFiled: May 15, 2009Date of Patent: July 15, 2014Assignee: E I du Pont de Nemours and CompanyInventors: Reid John Chesterfield, Nugent Truong, Jeffrey A. Merlo, Adam Fennimore, Jonathan M. Ziebarth
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Patent number: 8778708Abstract: There is provided a process for forming a layer of electroactive material having a substantially flat profile. The process includes: providing a workpiece having at least one active area; depositing a liquid composition including the electroactive material onto the workpiece in the active area, to form a wet layer; treating the wet layer on the workpiece at a controlled temperature in the range of ?25 to 80° C. and under a vacuum in the range of 10?6 to 1,000 Torr, for a first period of 1-100 minutes, to form a partially dried layer; heating the partially dried layer to a temperature above 100° C. for a second period of 1-50 minutes to form a dried layer.Type: GrantFiled: March 8, 2010Date of Patent: July 15, 2014Assignee: E I du Pont de Nemours and CompanyInventors: Reid John Chesterfield, Justin Butler, Paul Anthony Sant
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Patent number: 8759199Abstract: A method of selectively growing a plurality of semiconductor carbon nanotubes using light irradiation. The method includes disposing a plurality of nanodots, which include a catalyst material, on a substrate; growing a plurality of carbon nanotubes from the plurality of nanodots, and irradiating light onto the nanodot to selectively grow the plurality of semiconductor carbon nanotubes.Type: GrantFiled: September 10, 2010Date of Patent: June 24, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Won-mook Choi, Jae-young Choi, Jin Zhang, Guo Hong
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Publication number: 20140170841Abstract: The present invention provides a silicon carbide semiconductor device having an ohmic electrode improved in adhesion of a wire thereto by preventing deposition of carbon so as not to form a Schottky contact, as well as a method for manufacturing such a silicon carbide semiconductor device. In the SiC semiconductor device, upon forming the ohmic electrode, a first metal layer made of one first metallic element is formed on one main surface of a SiC layer. Further, a Si layer made of Si is formed on an opposite surface of the first metal layer to its surface facing the SiC layer. The stacked structure thus formed is subjected to thermal treatment. In this way, there can be obtained a silicon carbide semiconductor device having an ohmic electrode adhered well to a wire by preventing deposition of carbon atoms on the surface layer of the electrode and formation of a Schottky contact resulting from Si and SiC.Type: ApplicationFiled: January 29, 2014Publication date: June 19, 2014Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Hideto Tamaso
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Patent number: 8709858Abstract: The present invention relates to a method for decreasing or increasing the band gap shift in the production of photovoltaic devices by means of coating a substrate with a formulation containing a silicon compound, e.g., in the production of a solar cell comprising a step in which a substrate is coated with a liquid-silane formulation, the invention being characterized in that the formulation also contains at least one germanium compound. The invention further relates to the method for producing such a photovoltaic device.Type: GrantFiled: April 28, 2010Date of Patent: April 29, 2014Assignee: Evonik Degussa GmbHInventors: Bernhard Stuetzel, Wolfgang Fahrner
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Patent number: 8673401Abstract: A method for depositing gallium using a gallium ink, comprising, as initial components: a gallium component comprising gallium; a stabilizing component; an additive; and, a liquid carrier; is provided comprising applying the gallium ink on the substrate; heating the applied gallium ink to eliminate the additive and the liquid carrier, depositing gallium on the substrate; and, optionally, annealing the deposited gallium.Type: GrantFiled: January 7, 2013Date of Patent: March 18, 2014Assignee: Rohm and Haas Electronic Materials LLCInventors: David Mosley, David Thorsen
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Publication number: 20140051237Abstract: A representative printable composition comprises a liquid or gel suspension of a plurality of substantially spherical semiconductor particles; and a first solvent comprising a polyol or mixtures thereof, such as glycerin; and a second solvent different from the first solvent, the second solvent comprising a carboxylic or dicarboxylic acid or mixtures thereof, such as glutaric acid. The composition may further comprise a third solvent such as tetramethylurea, butanol, or isopropanol. In various embodiments, the plurality of substantially spherical semiconductor particles have a size in any dimension between about 5 nm and about 100?. A representative composition can be printed and utilized to produce diodes, such as photovoltaic diodes or light emitting diodes.Type: ApplicationFiled: August 16, 2012Publication date: February 20, 2014Applicant: NTHDEGREE TECHNOLOGIES WORLDWIDE INC.Inventors: Vera Nicholaevna Lockett, Mark David Lowenthal, Neil O. Shotton, William Johnstone Ray, Tricia Youngbull, Theodore I. Kamins
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Publication number: 20140035103Abstract: Provided is a high-quality Group III nitride crystal of excellent processability. A Group III nitride crystal is produced by forming a film is composed of an oxide, hydroxide and/or oxyhydroxide containing a Group III element by heat-treating a Group III nitride single crystal at 1000° C. or above, and removing the film.Type: ApplicationFiled: October 15, 2013Publication date: February 6, 2014Applicant: MITSUBISHI CHEMICAL CORPORATIONInventors: Hajime MATSUMOTO, Kunitada SUZAKI, Kenji FUJITO, Satoru NAGAO
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Patent number: 8642455Abstract: Methods and devices are provided for transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that of the feedstock or precursor materials, even after selective forces settling. In particular, planar particles disperse more easily, form much denser coatings (or form coatings with more interparticle contact area), and anneal into fused, dense films at a lower temperature and/or time than their counterparts made from spherical nanoparticles. These planar particles may be nanoflakes that have a high aspect ratio. The resulting dense films formed from nanoflakes are particularly useful in forming photovoltaic devices.Type: GrantFiled: April 19, 2010Date of Patent: February 4, 2014Inventors: Matthew R. Robinson, Jeroen K. J. Van Duren, Craig Leidholm, Brian M. Sager
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Patent number: 8633040Abstract: The invention can be used for producing different luminescent materials and as a basis for producing subminiature light-emitting diodes, white light sources, single-electron transistors, nonlinear optical devices and photosensitive and photovoltaic devices. The inventive method for producing semiconductor quantum dots involves synthesizing nanocrystal nuclei from a chalcogen-containing precursor and a precursor containing a group II or IV metal using an organic solvent and a surface modifier. The method is characterized in that (aminoalkyl)trialkoxysilanes are used as the surface modifier, core synthesis is carried out at a permanent temperature ranging from 150 to 250 C for 15 seconds to 1 hour and in that the reaction mixture containing the nanocrystal is additionally treated by UV-light for 1-10 minutes and by ultrasound for 5-15 minutes.Type: GrantFiled: August 18, 2009Date of Patent: January 21, 2014Assignee: The “Nanotech-Dubna” Trial Center for Science and TechnologyInventors: Roman Vladimirovich Novichkov, Maxim Sergeevich Wakstein, Ekaterina Leonidovna Nodova, Aleksey Olegovich Maniashin, Irina Ivanovna Taraskina
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Patent number: 8617947Abstract: A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms.Type: GrantFiled: April 26, 2012Date of Patent: December 31, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-kyu Yang, Phil-ouk Nam, Ki-hyun Hwang, Jae-young Ahn, Han-mei Choi, Bi-o Kim
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Patent number: 8598023Abstract: There is disclosed a substrate processing apparatus including a processing chamber housing a substrate, pipes for supplying gas into the processing chamber, and heaters provided in the middle of the pipes, and heating the gas. In the substrate processing apparatus, the heaters heat the gas to a temperature lower than a temperature at which exhaust gas is generated from the pipes to dry the substrate in the heated gas.Type: GrantFiled: July 31, 2012Date of Patent: December 3, 2013Assignee: Fujitsu Semiconductor LimitedInventor: Tomokazu Kawamoto
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Publication number: 20130312831Abstract: Techniques for enhancing energy conversion efficiency in chalcogenide-based photovoltaic devices by improved grain structure and film morphology through addition of urea into a liquid-based precursor are provided. In one aspect, a method of forming a chalcogenide film includes the following steps. Metal chalcogenides are contacted in a liquid medium to form a solution or a dispersion, wherein the metal chalcogenides include a Cu chalcogenide, an M1 and an M2 chalcogenide, and wherein M1 and M2 each include an element selected from the group consisting of: Ag, Mn, Mg, Fe, Co, Cd, Ni, Cr, Zn, Sn, In, Ga, Al, and Ge. At least one organic additive is contacted with the metal chalcogenides in the liquid medium. The solution or the dispersion is deposited onto a substrate to form a layer. The layer is annealed at a temperature, pressure and for a duration sufficient to form the chalcogenide film.Type: ApplicationFiled: June 1, 2012Publication date: November 28, 2013Applicant: International Business Machines CorporationInventors: David Brian Mitzi, Xiaofeng Qiu
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Patent number: 8592243Abstract: A method for forming a buffer layer in a dye-sensitized solar cell including a transparent electrode, a counter electrode, an electrolyte layer disposed between the electrodes, and a photocatalyst film disposed between the electrodes and near the transparent electrode, the buffer layer being disposed between the transparent electrode and photocatalyst film, the method including: forming the buffer layer by sintering a mixed solution of an alcohol solution and 0.03% to 5% by mass of metal alkoxide by laser beam irradiation after applying the mixed solution to the surface of the transparent electrode by spin coating, the transparent electrode being rotated by a rotating table.Type: GrantFiled: December 22, 2010Date of Patent: November 26, 2013Assignee: Hitachi Zosen CorporationInventors: Takeshi Sugiyo, Tetsuya Inoue
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Patent number: 8559478Abstract: Photonic integrated circuits on silicon are disclosed. By bonding a wafer of compound semiconductor material as an active region to silicon and removing the substrate, the lasers, amplifiers, modulators, and other devices can be processed using standard photolithographic techniques on the silicon substrate. A silicon laser intermixed integrated device in accordance with one or more embodiments of the present invention comprises a silicon-on-insulator substrate, comprising at least one waveguide in a top surface, and a compound semiconductor substrate comprising a gain layer, the compound semiconductor substrate being subjected to a quantum well intermixing process, wherein the upper surface of the compound semiconductor substrate is bonded to the top surface of the silicon-on-insulator substrate.Type: GrantFiled: January 16, 2009Date of Patent: October 15, 2013Assignee: The Regents of the University of CaliforniaInventors: Matthew N. Sysak, John E. Bowers, Alexander W. Fang, Hyundai Park
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Publication number: 20130252407Abstract: Compositions and methods for controlled polymerization and/or oligomerization of hydrosilanes compounds including those of the general formulae SinH2n and SinH2n+2 as well as alkyl- and arylsilanes, to produce soluble silicon polymers as a precursor to silicon films having low carbon content.Type: ApplicationFiled: May 17, 2013Publication date: September 26, 2013Inventors: Dmitry KARSHTEDT, Joerg ROCKENBERGER, Fabio ZURCHER, Brent RIDLEY, Erik SCHER
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Patent number: 8518808Abstract: A GaN sample in a sealed enclosure is heated very fast to a high temperature above the point where GaN is thermodynamically stable and is then cooled down very fast to a temperature where it is thermodynamically stable. The time of the GaN exposure to a high temperature range above its thermodynamic stability is sufficiently short, in a range of few seconds, to prevent the GaN from decomposing. This heating and cooling cycle is repeated multiple times without removing the sample from the enclosure. As a result, by accumulating the exposure time in each cycle, the GaN sample can be exposed to a high temperature above its point of thermodynamic stability for a long time but the GaN sample integrity is maintained (i.e., the GaN doesn't decompose) due to the extremely short heating duration of each single cycle.Type: GrantFiled: September 16, 2011Date of Patent: August 27, 2013Assignee: The United States of America, as represented by the Secretary of the NavyInventors: Boris N. Feigelson, Travis Anderson, Francis J. Kub
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Patent number: 8486753Abstract: Disclosed are a patterning method of a metal oxide thin film using nanoimprinting, and a manufacturing method of a light emitting diode (LED). The method for forming a metal oxide thin film pattern using nanoimprinting includes: coating a photosensitive metal-organic material precursor solution on a substrate; preparing a mold patterned to have a protrusion and depression structure; pressurizing the photosensitive metal-organic material precursor coating layer with the patterned mold; forming a cured metal oxide thin film pattern by heating the pressurized photosensitive metal-organic material precursor coating layer or by irradiating ultraviolet rays to the pressurized photosensitive metal-organic material precursor coating layer while being heated; and removing the patterned mold from the metal oxide thin film pattern, and selectively further includes annealing the metal oxide thin film pattern.Type: GrantFiled: February 2, 2010Date of Patent: July 16, 2013Assignee: Korea Institute of Machinery and MaterialsInventors: Hyeong Ho Park, Jun Ho Jeong, Ki Don Kim, Dae Geun Choi, Jun Hyuk Choi, Ji Hye Lee, Soon Won Lee
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Publication number: 20130161793Abstract: Silicon single crystal substrates having uniform resistance, few BMDs in a surface layer and a moderate number of BMDs in a center of thickness of the substrate are formed from Czochralski silicon single crystals. The substrates have a resistivity in the center of a first main surface not lower than 50 ?·cm and a rate of change in resistivity in the first main surface not higher than 3%, an average density of bulk micro defects in a region between the first main surface and a plane at a depth of 50 ?m of less than 1×108/cm3, and an average density of bulk micro defects in a region lying between a plane at a depth of 300 ?m and a plane at a depth of 400 ?m from the first main surface not lower than 1×108 /cm3 and not higher than 1×109 /cm3.Type: ApplicationFiled: September 12, 2012Publication date: June 27, 2013Applicant: SILTRONIC AGInventors: Katsuhiko Nakai, Masamichi Ohkubo, Hikaru Sakamoto
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Patent number: 8470636Abstract: The present invention relates to aqueous processes to make metal chalcogenide nanoparticles that are useful precursors to copper zinc tin sulfide/selenide and copper tin sulfide/selenide. In addition, this invention provides processes for preparing crystalline particles from the metal chalcogenide nanoparticles, as well as processes for preparing inks from both the metal chalcogenide nanoparticles and the crystalline particles.Type: GrantFiled: November 22, 2010Date of Patent: June 25, 2013Assignee: E I du Pont de Nemours and CompanyInventors: Daniela Rodica Radu, Lynda Kaye Johnson, Cheng-Yu Lai, Meijun Lu, Irina Malajovich
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Patent number: 8470626Abstract: Exemplary embodiments of the present invention relate to a method of fabricating a light emitting diode (LED). According to an exemplary embodiment of the present invention, the method includes growing a first GaN-based semiconductor layer on a substrate at a first temperature by supplying a chamber with a nitride source gas and a first metal source gas, stopping the supply of the first metal source gas and maintaining the first temperature for a first time period after stopping the supply of the first metal source gas, decreasing the temperature of the substrate to the a second temperature after the first time period elapses, growing an active layer of the first GaN-based semiconductor layer at the second temperature by supplying the chamber with a second metal source gas.Type: GrantFiled: June 1, 2011Date of Patent: June 25, 2013Assignee: Seoul Opto Device Co., Ltd.Inventors: Kwang Joong Kim, Chang Suk Han, Seung Kyu Choi, Ki Bum Nam, Nam Yoon Kim, Kyung Hae Kim, Ju Hyung Yoon
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Patent number: 8460983Abstract: Doped semiconductor ink formulations, methods of making doped semiconductor ink formulations, methods of coating or printing thin films, methods of forming electronic devices and/or structures from the thin films, and methods for modifying and controlling the threshold voltage of a thin film transistor using the films are disclosed. A desired dopant may be added to an ink formulation comprising a Group IVA compound and a solvent, and then the ink may be printed on a substrate to form thin films and conductive structures/devices, such as thin film transistors. By adding a customized amount of the dopant to the ink prior to printing, the threshold voltage of a thin film transistor made from the doped semiconductor ink may be independently controlled upon activation of the dopant.Type: GrantFiled: January 21, 2009Date of Patent: June 11, 2013Assignee: Kovio, Inc.Inventors: Wenzhuo Guo, Fabio Zürcher, Arvind Kamath, Joerg Rockenberger
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Patent number: 8461031Abstract: A method for making a thin-film structure includes a thin film stabilized on a substrate. The structure of the thin film is defined by a material which includes at least one first chemical species. The method includes a step of inputting particles of the first chemical species into the thin film so as to compensate for the flow of vacancies from the surface of the film.Type: GrantFiled: October 25, 2006Date of Patent: June 11, 2013Assignee: Commissariat a l'Energie AtomiqueInventors: Joël Eymery, Pascal Pochet
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Patent number: 8455346Abstract: According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film.Type: GrantFiled: March 30, 2011Date of Patent: June 4, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiro Nojiri, Hiroyuki Fukumizu, Shinichi Nakao, Kei Watanabe, Kazuhiko Yamamoto, Ichiro Mizushima, Yoshio Ozawa
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Patent number: 8426297Abstract: A method of manufacturing a silicon wafer, an oxygen concentration in a surface layer to be maintained more than a predetermined value while promoting a defect-free layer. Strength of the surface layer can be made higher than that of an ordinary annealed sample as a COP free zone is secured. A method of manufacturing a silicon wafer doped with nitrogen and oxygen, includes growing a single crystal silicon doped with the nitrogen by Czochralski method, slicing the grown single crystal silicon to obtain a single crystal silicon wafer; heat treating the sliced single crystal silicon wafer in an ambient gas including a hydrogen gas and/or an inert gas; polishing the heat treated single crystal silicon wafer, after the heat treatment, such that an obtained surface layer from which COP defects have been removed by the heat treatment is polished away until an outermost surface has a predetermined oxygen concentration.Type: GrantFiled: August 7, 2009Date of Patent: April 23, 2013Assignee: Sumco Techxiv CorporationInventor: Shinya Sadohara
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Patent number: 8372734Abstract: Methods and devices are provided for transforming non-planar or planar precursor materials in an appropriate vehicle under the appropriate conditions to create dispersions of planar particles with stoichiometric ratios of elements equal to that of the feedstock or precursor materials, even after selective forces settling. In particular, planar particles disperse more easily, form much denser coatings (or form coatings with more interparticle contact area), and anneal into fused, dense films at a lower temperature and/or time than their counterparts made from spherical nanoparticles. These planar particles may be nanoflakes that have a high aspect ratio. The resulting dense films formed from nanoflakes are particularly useful in forming photovoltaic devices. In one embodiment, at least one set of the particles in the ink may be inter-metallic flake particles (microflake or nanoflake) containing at least one group IB-IIIA inter-metallic alloy phase.Type: GrantFiled: June 19, 2007Date of Patent: February 12, 2013Assignee: Nanosolar, IncInventors: Jeroen K. J. Van Duren, Matthew R. Robinson, Brian M. Sager