Abstract: A method of manufacturing a semiconductor device, including providing a semiconductor wafer, forming a photoresist film on a main surface of the semiconductor wafer, forming a first mask pattern and a second mask pattern on the photoresist film, selectively removing portions of the photoresist film according to the first and second mask patterns, to respectively form a first opening and a second opening in the photoresist film, a position of the second opening differing from that of the first opening, and performing ion implantation of an impurity into the semiconductor wafer, using the photoresist film having the first and second openings formed therein as a mask.

Abstract: Methods and apparatus for static charge neutralization in variable pressure environments are disclosed. In particular, barrier discharge ionization apparatus may include a hollow dielectric channel disposed within a variable pressure environment and may have at least one open end, a reference emitter disposed on the outer surface of the channel, and a high voltage electrode disposed within the channel. The high voltage electrode may present a high intensity electric field to the reference emitter through the dielectric channel in response to the provision of a variable-waveform signal dictated by conditions in the variable pressure environment. This results in the generation of a plasma region with electrically balanced charge carriers within the variable pressure environment due to barrier discharge occurring at the interface of the reference emitter and the outer surface of the dielectric channel. The disclosed apparatus are compatible with either radio frequency or micro-pulse voltage power supplies.

Abstract: An exemplary semiconductor device comprises a through silicon via penetrating a semiconductor substrate including a circuit pattern on one side of the substrate, a first doped layer formed in the other side , and a bump connected with the through silicon via.

Abstract: The present invention generally relates to methods of forming substrates using remote radical hydride doping. The methods generally include remotely activating a gas and introducing activated radicals of the gas into a chamber. The activated radicals may be activated hydride radicals of a gas such as diborane (B2H6), phosphine (PH3), or arsine (AsH3) which are utilized to incorporate an element such as boron, phosphorus, or arsenic into a substrate having a surface temperature between about 400 degrees Celsius and about 1000 degrees Celsius. Alternatively, the activated radicals may be activated radicals of an inert gas. The activated radicals of the inert gas are introduced into a chamber having a dopant-containing gas, such as diborane, phosphine, or arsine, therein. The activated radicals of the inert gas activate the dopant-gas and incorporate dopants into a heated substrate located within the chamber.

Abstract: A method of manufacturing a silicon carbide semiconductor device of an embodiment includes: implanting ions in a silicon carbide substrate; performing first heating processing of the silicon carbide substrate in which the ions are implanted; and performing second heating processing of the silicon carbide substrate for which the first heating processing is performed, at a temperature lower than the first heating processing.

Abstract: A method includes the step of preparing a GaN-based substrate 10, the step of forming on the substrate a nitride-based semiconductor multilayer structure including a p-type AldGaeN layer (p-type semiconductor region) 26, the p-type AldGaeN layer 26 being made of an AlxInyGazN semiconductor (x+y+z=1, x?0, y?0, z?0), and a principal surface of the p-type AldGaeN layer 26 being an m-plane, the step of forming a metal layer 28 which contains at least one of Mg and Zn on the principal surface of the p-type AldGaeN layer 26 and performing a heat treatment, the step of removing the metal layer 28, and the step of forming a p-type electrode on the principal surface of the p-type AldGaeN layer 26, wherein the heat treatment causes a N concentration to be higher than a Ga concentration in the p-type AldGaeN layer 26.

Abstract: A method for forming a laterally varying n-type doping concentration is provided. The method includes providing a semiconductor wafer with a first surface, a second surface arranged opposite to the first surface and a first n-type semiconductor layer having a first maximum doping concentration, implanting protons of a first maximum energy into the first n-type semiconductor layer, and locally treating the second surface with a masked hydrogen plasma. Further, a semiconductor device is provided.

Abstract: When positively charged ions are implanted into a target substrate, charge-up damage may occur on the target substrate. In order to suppress charge-up caused by secondary electrons emitted from the target substrate when positively charged ions are implanted, a conductive member is installed at a position facing the target substrate and electrically grounded with respect to a high frequency. Further, a field intensity generated in the target substrate may be reduced by controlling an RF power applied to the target substrate in pulse mode.

Abstract: A process of producing a diamond thin-film includes implanting dopant into a diamond by an ion implantation technique, forming a protective layer on at least part of the surface of the ion-implanted diamond, and firing the protected ion-implanted diamond at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C. A process of producing a diamond semiconductor includes implanting dopant into each of two diamonds by an ion implantation technique and superimposing the two ion-implanted diamonds on each other such that at least part of the surfaces of each of the ion-implanted diamonds makes contact with each other, and firing the ion implanted diamonds at a firing pressure of no less than 3.5 GPa and a firing temperature of no less than 600° C.

Abstract: One embodiment of inventive concepts exemplarily described herein may be generally characterized as a semiconductor device including an isolation region within a substrate. The isolation region may define an active region. The active region may include an edge portion that is adjacent to an interface of the isolation region and the active region and a center region that is surrounded by the edge portion. The semiconductor device may further include a gate electrode on the active region and the isolation region. The gate electrode may include a center gate portion overlapping a center portion of the active region, an edge gate portion overlapping the edge portion of the active region, and a first impurity region of a first conductivity type within the center gate portion and outside the edge portion. The semiconductor device may further include a gate insulating layer disposed between the active region and the gate electrode.

Abstract: Semiconductor devices can be fabricated using conventional designs and process but including specialized structures to reduce or eliminate detrimental effects caused by various forms of radiation. Such semiconductor devices can include the one or more parasitic isolation devices and/or buried guard ring structures disclosed in the present application. The introduction of design and/or process steps to accommodate these novel structures is compatible with conventional CMOS fabrication processes, and can therefore be accomplished at relatively low cost and with relative simplicity.

Abstract: Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfaces prior to wafer introduction.

Abstract: A plasma immersion ion implantation process for implanting a selected species at a desired ion implantation depth profile in a workpiece is carried out in a reactor chamber having a set of plural parallel ion shower grids that divide the chamber into an upper ion generation region and a lower process region, each of the ion shower grids having plural orifices in mutual registration from grid to grid, the plural orifices oriented in a non-parallel direction relative to a surface plane of the respective ion shower grid. The process includes placing a workpiece in the process region, the workpiece having a workpiece surface generally facing the surface plane of the closest one of the plural ion shower grids, and furnishing the selected species into the ion generation region. The process further includes evacuating the process region, and applying plasma source power to generate a plasma of the selected species in the ion generation region.

Abstract: Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfaces prior to wafer introduction.

Abstract: [Object] To provide a deposition apparatus 1 capable of suppressing a temporal change in film formation conditions. [Solution] In the deposition apparatus 1 including a substrate holder 12 supported in a vacuum chamber 10 grounded on the earth, a substrate 14 held by the substrate holder 12, deposition sources 34, 36 placed distant from the substrate 14 so as to face the substrate, an ion gun 38 for irradiating ions to the substrate 14, and a neutralizer 40 for irradiating electrons to the substrate 14, an irradiated ion guide member 50 and an irradiated electron guide member 52 are respectively attached to the ion gun 38 and the neutralizer 40.

Abstract: A plasma immersion ion implantation process for implanting a selected species at a desired ion implantation depth profile in a workpiece is carried out in a reactor chamber with an ion shower grid that divides the chamber into an upper ion generation region and a lower process region, the ion shower grid having plural elongate orifices oriented in a non-parallel direction relative to a surface plane of the ion shower grid.

Abstract: Embodiments of this method improve the results of a chemical mechanical polishing (CMP) process. A surface is implanted with a species, such as, for example, Si, Ge, As, B, P, H, He, Ne, Ar, Kr, Xe, and C. The implant of this species will at least affect dishing, erosion, and polishing rates of the CMP process. The species may be selected in one embodiment to either accelerate or decelerate the CMP process. The dose of the species may be varied over the surface in one particular embodiment.

Abstract: The present invention is directed to a method for fabricating a thermal management substrate having a Silicon (Si) layer on a polycrystalline diamond film, or on a diamond-like-carbon (DLC) film. The method comprises acts of fabricating a separation by implantation of oxygen (SIMOX) wafer; depositing a polycrystalline diamond film onto the SIMOX wafer; and removing various layers of the SIMOX wafer to leave a Si overlay layer that is epitaxially fused with the polycrystalline diamond film. In the case of the DLC film, the method comprises acts of ion-implanting a Si wafer; depositing an amorphous DLC film onto the Si wafer; and removing various layers of the Si wafer to leave a Si overlay structure epitaxially fused with the DLC film.

Abstract: A method for fabricating a metal oxide semiconductor (MOS) transistor comprises forming a source region of a first conductivity type and a drain region of the first conductivity type, which are separated from each other by a channel region, in upper regions of a semiconductor substrate, forming a gate stack on the channel region, and feeding hydrogen into junctions of the source and drain regions to neutralize dopants of the first conductivity type present within particular portions of the junctions.

Abstract: Method of forming one or more doped regions in a semiconductor substrate and semiconductor junctions formed thereby, using gas cluster ion beams.

Abstract: Method of forming one or more doped regions in a semiconductor substrate and semiconductor junctions formed thereby, using gas cluster ion beams.

Abstract: A technique for boron implantation is disclosed. In one particular exemplary embodiment, the technique may be realized by an apparatus for boron implantation. The apparatus may comprise a reaction chamber. The apparatus may also comprise a source of pentaborane coupled to the reaction chamber, wherein the source is capable of supplying a substantially pure form of pentaborane into the reaction chamber. The apparatus may further comprise a power supply that is configured to energize the pentaborane in the reaction chamber sufficiently to produce a plasma discharge having boron-bearing ions.

Abstract: An inductor formed on a semiconductor substrate, comprising active device regions. The inductor comprises conductive lines formed on a dielectric layer overlying the semiconductor substrate. The conductive lines are patterned and etched into the desired shape, in one embodiment a planar spiral. A region of the substrate below the inductor are removed to lower the inductive Q factor.

Abstract: A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.

Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.

Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.

Abstract: Microelectronic apparatus having protection against high frequency crosstalk radiation, comprising: a planar insulating substrate; an active semiconductor electronic device located over a first region of the insulating substrate; and a doped semiconductor located in a second region of the insulating substrate substantially surrounding the first region. Apparatus further comprising a dissipative conductor overlaying and adjacent to the doped semiconductor. Apparatus additionally comprising metallic test probe contacts making electrical connections with the active semiconductor electronic device. Application of the apparatus to dissipate crosstalk radiation having a center frequency within a range between about 1 gigahertz and about 1,000 gigahertz. Methods for making the apparatus.

Abstract: An n-type channel diffused layer and an n-type well diffused layer are formed in the top portion of a semiconductor substrate, and a gate insulating film and a gate electrode are formed on the semiconductor substrate. Using the gate electrode as a mask, boron and arsenic are implanted to form p-type extension implanted layers and n-type pocket impurity implanted layers. Fluorine is then implanted using the gate electrode as a mask to form fluorine implanted layers. The resultant semiconductor substrate is subjected to rapid thermal annealing, forming p-type high-density extension diffused layers and n-type pocket diffused layers. Sidewalls and p-type high-density source/drain diffused layers are then formed.

Abstract: A process is provided for forming an isolating nitride film to isolate gate polysilicon of a gate structure. Specifically, the process comprises providing a channel region defined by a source and drain region of a semiconductor substrate having a gate structure comprising an isolating oxide layer positioned on the channel region and the polysilicon layer positioned on the oxide layer. More specifically, the process comprises the steps of forming the nitrogen implanted regions over the semiconductor substrate by implanting nitrogen atoms into those regions and growing spacers from exposed portions of the polysilicon layer. During the spacer growth, the spacer grows vertically as well as laterally extending under the polysilicon edges. Diffusion of nitrogen atoms to the substrate surface forms silicon nitride under the gate edges, which minimizes current leakages into gate polysilicon.

Abstract: A method is disclosed for producing highly uniform semi-insulating characteristics in single crystal silicon carbide for semiconductor applications. The method includes irradiating a silicon carbide single crystal having net p-type doping and deep levels with neutrons until the concentration of 31P equals or exceeds the original net p-type doping while remaining equal to or less than the sum of the concentration of deep levels and the original net p-type doping.

Abstract: A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.

Abstract: A method of forming a charge balanced, silicon dioxide layer gate insulator layer on a semiconductor substrate, with reduced leakage obtained via nitrogen treatments, has been developed. Prior to thermal growth of a silicon dioxide gate insulator layer, negatively charged fluorine ions are implanted into a top portion of a semiconductor substrate. The thermal oxidation procedure results in the growth of a silicon dioxide layer with incorporated, negatively charged fluorine ions. Subsequent nitrogen treatments, used to reduce gate insulator leakage, result in generation of positive charge in the exposed silicon dioxide layer, compensating the negatively charged fluorine ions and resulting in the desired charge balanced, silicon dioxide gate insulator layer.

Abstract: Process for fabricating a SONOS flash memory device, including in one embodiment, forming a bottom oxide layer of an ONO structure on a semiconductor substrate, wherein the bottom oxide layer has a first oxygen vacancy content; treating the bottom oxide layer to decrease the first oxygen vacancy content to a second oxygen vacancy content; and depositing a dielectric charge-storage layer on the bottom oxide layer. In another embodiment, a process for fabricating a SONOS flash memory device includes forming a bottom oxide layer of an ONO structure on the semiconductor substrate under strongly oxidizing conditions, wherein the bottom oxide layer has a super-stoichiometric oxygen content and an oxygen vacancy content reduced relative to a bottom oxide layer formed by a conventional process; and depositing a dielectric charge-storage layer on the bottom oxide layer.

Abstract: A method of manufacturing a semiconductor device includes providing a silicon semiconductor layer over an insulating layer, and partially removing a first portion of the silicon layer. The silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the silicon layer initially can have the same thickness. A semiconductor device is also disclosed.

Abstract: A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged logic such as CMOS. Ion implantation of oxygen is used to formed patterned buried oxide layers at selected depths and mask edges may be shaped to form stepped oxide regions from one depth to another. Trenches may be formed through buried oxide end regions to remove high concentrations of dislocations in single crystal silicon containing substrates. The invention overcomes the problem of forming DRAM with a storage capacitor formed with a deep, trench in bulk Si while forming merged logic regions on SOI.

Abstract: The invention describes a method for forming ultra shallow junction formation. Dopant species are implanted into a semiconductor. Solid phase epitaxy anneals and subsequent ultra high temperature anneals are performed following the implantation processes.

Abstract: A semiconductor device includes a gate electrode formed on a semiconductor region via a gate insulative film and an extension high concentration diffusion layer of a first conductivity type formed in the semiconductor region beside the gate electrode. A dislocation loop defect layer is formed in a region of the semiconductor region beside the gate electrode and at a position shallower than an implantation projected range of the extension high concentration diffusion layer.

Abstract: A process for the fabrication of an integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region, and a gate oxide layer is form on the active regions. Gate electrodes are formed upon the gate oxide layer in the active regions. An angled, high dose, ion implant is performed to selectively dope the gate oxide layer beneath an edge of each gate electrode in a gate-drain overlap region, and the fabrication of the integrated circuit is completed.

Abstract: There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conductive layer of a gate electrode of dual-gate construction is formed on an isolation oxide film. N-type impurities are implanted into an n-type implantation region of the polysilicon film while a photoresist film is taken as a mask. P-type impurities are implanted into a p-type impurity region of the polysilicon film 3 while another photoresist film is taken as a mask. Implantation of n-type impurities and implantation of p-type impurities are performed such that an overlapping area to be doped with these impurities in an overlapping manner is inevitably formed.

Abstract: A method of forming an ultra-thin dielectric layer, including the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density.

Abstract: A method and apparatus for measuring the concentration of different mobile ions in the oxide layer of a semiconductor wafer from the contact potential shift caused by different ions drifting across the oxide that includes depositing charge (e.g., using a corona discharge device) on the surface of the oxide and heating the wafer to allow different mobile ions in the oxide to drift. The difference in the contact potential measured before and after heating provides an indication of the different mobile ion concentration in the oxide layer.

Abstract: This invention relates to the field of semiconductor integrated circuits and, particularly to stand-alone and embedded memory chips fabricated on Silicon-on-Insulator (SOI) substrates and devices. Partially depleted (PD) and fully depleted (FD) devices are utilized on the same chip. The invention is a process flow utilizing fully depleted SOI devices in one area of the chip and partially depleted SOI devices in selected other areas of the chip. The choice of fully depleted or partially depleted is solely determined by the circuit application in that specific area of the chip. The invention is able to be utilized in accordance with DRAM processing, and especially embedded DRAMs with their large proportion of associated logic circuitry.

Abstract: A method for forming an ultra-shallow junction by boron plasma doping is disclosed. A substrate is placed in a pulse type electric field. A flowing carrying gas drives boron ions in a channel above the substrate, and then a negative pulse type voltage is applied so that the boron ions may uniformly enter into the substrate. Then a rapid annealing process is performed so as to be formed with an ultra-shallow junction on the substrate. In the present invention, by the boron plasma doping, an ultra-shallow junction is provided on a surface of the substrate. Therefore, after the next thermal process, the property of the element can be retained. A lower depth junction is acquired, and the diffusion in the horizontal direction is suppressed.

Abstract: A method for introducing an impurity includes the steps of: introducing an impurity having charges into a target to be processed, such as a semiconductor substrate and a film formed on a substrate; and supplying electrons from a filament into the target to neutralize the charges of the impurity. The step of supplying electrons includes a step of controlling the maximum energy of the electrons supplied at a predetermined energy or less.

Abstract: We have discovered that, contrary to conventional wisdom about forming DP defects, electrical saturation in highly doped 2D layers of Si does not occur. In accordance with one aspect of our invention, free-carrier concentrations in excess of about 7×1020 cm−3 can be attained in single crystal Si layers &dgr;-doped with a Group V element. In one embodiment, free-carrier concentrations in excess of about 2×1021 cm−3 are realized in single crystal Si that is &dgr;-doped with Sb. In another embodiment, the &dgr;-doped layer is formed as an integral part of an FET.

Abstract: A transistor having reduced series resistance and method for producing the same. The method reduces transistor series resistance by implanting nitrogen into an nLDD/Source/Drain extension region of the transistor. The nitrogen implantation in connection with the implantation of a conventional n-type dopant (e.g. arsenic or phosphorus), results in a transistor having low series resistance, reduced hot carrier effects and no significant increase in source/drain extension overlap.

Abstract: The invented method can be used to melt and recrystallize the source and drain regions of an integrated transistor device(s) using a laser, for example. The invented method counteracts shadowing and interference effects caused by the presence of the gate region(s) during annealing of the source and drain regions with radiant energy generated by a laser, for example. The invented method includes forming a radiant energy absorber layer over at least the gate region(s) of an integrated transistor device(s), and irradiating the radiant energy absorber layer with radiant energy to generate heat in the source and drain regions as well as in the radiant energy absorber layer. The heat generated in the radiant energy absorber layer passes through the gate region(s) to portions of source and drain regions of the integrated transistor device(s) adjacent the gate region(s).

Abstract: A method of fabricating a semiconductor device having active components grown on a substrate, involves providing a semiconductor substrate on which the active components are grown, and doping the semiconductor substrate to render it non conductive and thereby reduce parasitic capacitance between active components thereon. The components typically comprise a VCSEL and monitor. The doped substrate reduces parasitic capacitance.

Abstract: In a pretreatment process, a silicon oxide film (13) with nitrogen content is formed on a semiconductor substrate (10). In a segregation process executing heat treatment in an inert gas atmosphere, a silicon nitride layer (14) segregates out at the interface of the silicon substrate (10) and the silicon oxide film (13). In a high dielectric film forming process, the unnecessary silicon oxide film (13) on the silicon nitride layer (14) is removed, a high dielectric oxide layer (15) is formed on the exposed silicon nitride layer (14). Whereby, a gate electrode (16) consisting of the silicon nitride layer (14) and the high dielectric oxide layer (15) is formed.

Abstract: A thin film field effect transistor includes source and drain regions, an active region sandwiched by the source and drain semiconductor regions. A gate insulating film is provided to cover the source and drain regions and the active region, and a semiconductor gate is formed on the gate insulating film above the active region. A gate electrode is formed on the semiconductor gate such that a non-covering portion where the gate electrode does not cover the semiconductor gate is formed.