Ion Implantation Of Dopant Into Semiconductor Region Patents (Class 438/514)
  • Patent number: 10699871
    Abstract: Provided herein are systems and methods for spatially resolved optical metrology of an ion beam. In some embodiments, a system includes a chamber containing a plasma/ion source operable to deliver an ion beam to a wafer, and an optical collection module operable with the chamber, wherein the optical collection module includes an optical device for measuring a light signal from a volume of the ion beam. The system may further include a detection module operable with the optical collection module, the detection module comprising a detector for receiving the measured light signal and outputting an electric signal corresponding to the measured light signal, thus corresponding to the property of the sampled plasma volume.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: June 30, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Gang Shu, Glen Gilchrist, Shurong Liang
  • Patent number: 10600872
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide layer of the first conductivity type, and an insulating film. In the silicon carbide semiconductor device, no fluorine or chlorine is detectable in the insulating film, at a boundary layer of the insulating film and the first silicon carbide layer, or at the surface of first silicon carbide layer where the insulating film is provided.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 24, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Yasuhiko Oonishi, Fumikazu Imai
  • Patent number: 10593735
    Abstract: The present disclosure provides a diode device comprising a first electrode, a hole transport layer, a functional layer, an electron transport layer and a second electrode that are stacked, wherein the functional layer comprises at least one sub-functional layer each comprising a photo-detection layer and an electroluminescent layer which are stacked and a difference of energy barriers between the photo-detection layer and the electroluminescent layer is not more than 1.5 eV; the photo-detection layer comprises a nanocrystalline derived from a copper indium sulfide system compound, and the electroluminescent layer comprises an oil-soluble nanocrystalline. The present disclosure further provides a method for manufacturing a diode device, and a diode apparatus having both electro-luminescence and photoelectric response properties, and higher material universal applicability.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 17, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shuai Chang, Haizheng Zhong, Dengbao Han
  • Patent number: 10580693
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: March 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
  • Patent number: 10541144
    Abstract: A method for etching features into a silicon containing layer comprising performing a plurality of cycles in a plasma processing chamber is provided. Each cycle comprises a deposition phase and an activation phase. The deposition phase comprises flowing a precursor into the plasma processing chamber to form a self-limiting monolayer, wherein the precursor comprises a head group component and a tail group component, wherein the tail group component comprises fluorine and carbon, and stopping the flow of the precursor into the plasma processing chamber. The activation phase comprises flowing an activation gas comprising an ion bombardment gas, into the plasma processing chamber, creating a plasma from the activation gas, providing an activation bias to cause ion bombardment of the self-limiting monolayer, wherein the ion bombardment activates the fluorine from the tail group component to etch the silicon containing layer, and stopping the flow of the activation gas.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: January 21, 2020
    Assignee: Lam Research Corporation
    Inventor: Eric Hudson
  • Patent number: 10541301
    Abstract: A method of producing a semiconductor device includes providing a semiconductor body including a semiconductor body material having a dopant diffusion coefficient that is smaller than the corresponding dopant diffusion coefficient of silicon. At least one first semiconductor region doped with dopants of a first conductivity type is produced in the semiconductor body, including by applying a first implantation of first implantation ions. At least one second semiconductor region adjacent to the at least one first semiconductor region and doped with dopants of a second conductivity type complementary to the first conductivity type is produced in the semiconductor body, including by applying a second implantation of second implantation ions.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: January 21, 2020
    Assignee: Infineon Technologies AG
    Inventors: Hans-Joachim Schulze, Wolfgang Jantscher, Roland Rupp, Werner Schustereder, Hans Weber
  • Patent number: 10522656
    Abstract: A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia-Ling Chan, Derek Chen, Liang-Yin Chen, Chien-I Kuo
  • Patent number: 10522364
    Abstract: A method including forming hard mask patterns on a substrate; forming etch stop patterns surrounding the hard mask patterns; forming spacer patterns covering sidewalls of the etch stop patterns; removing the etch stop patterns; etching the substrate to form active and dummy fins; forming a block mask pattern layer surrounding the active and dummy fins and forming mask etch patterns on a top surface of the block mask pattern layer; etching the block mask pattern layer to form block mask patterns surrounding the active fins; etching the dummy fins; removing the block mask patterns surrounding the active fins; and depositing a device isolation film on the substrate such that the device isolation film is not in contact with the upper portions of the active fins, wherein a spacing distance between the active fin and the dummy fin is greater than an active fin spacing distance between the active fins.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung Min Kim, Dong Won Kim
  • Patent number: 10439025
    Abstract: A first part of a semiconductor body is provided. Impurities are introduced into the first part of the semiconductor body, The impurities act as recombination centers in the semiconductor body and form a recombination Zone, and the impurities include at least a heavy metal. A second part of the semiconductor body is epitaxially produced on the first part after introducing the impurities in the first part. During epitaxially producing the second part of the semiconductor body on the first part of the semiconductor body, impurities in the first part of the semiconductor body are diffused to the second part of the semiconductor body.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: October 8, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Frank Pfirsch, Hans-Joachim Schulze
  • Patent number: 10395890
    Abstract: An ion implantation apparatus includes: a multistage linear acceleration unit including a plurality of stages of high-frequency resonators and a plurality of stages of focusing lenses; a first beam measuring unit disposed in the middle of the multistage linear acceleration unit and configured to allow passage of a beam portion adjacent to a center of a beam trajectory and measure a current intensity of another beam portion blocked by an electrode body outside a vicinity of the center of the beam trajectory; a second beam measuring unit disposed downstream of the multistage linear acceleration unit and configured to measure a current intensity of an ion beam exiting from the multistage linear acceleration unit; and a control device configured to adjust a control parameter of the plurality of stages of focusing lenses based on measurement results of the first and second beam measuring units.
    Type: Grant
    Filed: January 4, 2018
    Date of Patent: August 27, 2019
    Assignee: SUMITOMO HEAVY INDUSTRIES ION TECHNOLOGY CO., LTD.
    Inventor: Haruka Sasaki
  • Patent number: 10347489
    Abstract: A method of manufacturing a semiconductor device is presented. The method includes providing a semiconductor layer comprising silicon carbide, wherein the semiconductor layer comprises a first region doped with a first dopant type. The method further includes implanting the semiconductor layer with a second dopant type using a single implantation mask and a substantially similar implantation dose to form a second region and a junction termination extension (JTE) in the semiconductor layer, wherein the implantation dose is in a range from about 2×1013 cm?2 to about 12×1013 cm?2. Semiconductor devices are also presented.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: July 9, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Peter Almern Losee, Alexander Viktorovich Bolotnikov, Stacey Joy Kennerly
  • Patent number: 10338466
    Abstract: Techniques include providing selective or differential planarization such that different regions of a substrate can have different amounts of material removed. In general, methods herein use photo-reactive generator compounds to generate solubility-changing agents. A specific pattern of light is projected onto a substrate containing such photo-reactive generator compounds to create different concentrations of solubility-changing agent(s) at specific locations across a substrate. As generated solubility-changing agents are diffused into an underlying layer, these concentration differences then control an amount (height or depth) of material removed from a given film or layer at specific spatial locations on the substrate.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: July 2, 2019
    Assignee: Tokyo Electron Limited
    Inventor: Anton J. deVilliers
  • Patent number: 10319810
    Abstract: A semiconductor device of an embodiment includes transistor cells in a transistor cell area of a semiconductor body. A super junction structure in the semiconductor body includes a plurality of drift sub-regions and compensation sub-regions of opposite first and second conductivity types, respectively, and alternately arranged along a lateral direction. A termination area outside the transistor cell area between an edge of the semiconductor body and the transistor cell area includes first and third termination sub-regions of the first conductivity type, respectively. A second termination sub-region of the second conductivity type is sandwiched between the first and the third termination sub-regions along a vertical direction perpendicular to a first surface of the semiconductor body.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 11, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Hans Weber
  • Patent number: 10319717
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins on a first region of the semiconductor substrate, forming a bi-polymer structure, selectively removing the first polymer of the bi-polymer structure and forming deep trenches in the semiconductor substrate resulting in pillars in a second region of the semiconductor structure. The method further includes selectively removing the second polymer of the bi-polymer structure, doping the pillars, and depositing a high-k metal gate (HKMG) over the first and second regions to form the MIS capacitor in the second region of the semiconductor substrate.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Kangguo Cheng, Peng Xu, Chen Zhang
  • Patent number: 10261415
    Abstract: A chemically amplified positive-type photosensitive resin composition capable of forming a resist pattern having a nonresist portion with a favorable rectangular sectional shape, a method of manufacturing a resist pattern using the composition, a method of manufacturing a substrate with a template using the composition, and a method of manufacturing a plated article using the substrate with a template manufactured by the method. In a chemically amplified positive-type photosensitive resin composition including an acid generator, a resin whose solubility in alkali increases under the action of acid, and an organic solvent, an acrylic resin is used that includes a constituent unit derived from an acrylic acid ester including an —SO2-containing cyclic group or a lactone-containing cyclic group, and a constituent unit derived from an acrylic acid ester containing an organic group including an aromatic group and an alcoholic hydroxyl group.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: April 16, 2019
    Assignee: TOKYO OHKA KOGYO CO., LTD.
    Inventors: Makiko Irie, Aya Momozawa
  • Patent number: 10161062
    Abstract: A composition comprising an engineered defect concentration comprises a metal oxide single crystal having a polar surface and a bulk concentration of interstitial oxygen (Oi) of at least about 1014 atoms/cm3. The polar surface comprises a concentration of impurity species of about 5% or less of a monolayer. A method of engineering a defect concentration in a single crystal comprises exposing a metal oxide single crystal having a polar surface to molecular oxygen at a temperature of about 850° C. or less, and injecting atomic oxygen into the single crystal at an effective diffusion rate Deff of at least about 10?16 cm2/s.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: December 25, 2018
    Assignee: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
    Inventors: Edmund G. Seebauer, Prashun Gorai
  • Patent number: 10128133
    Abstract: An etching tool that includes an interior chamber is provided. A plurality of type III-V semiconductor wafers is provided. A process cycle is performed for each one of the type III-V semiconductor wafers in the plurality. The process cycle includes performing a preliminary contamination control process. The process cycle further includes inserting one of the type III-V semiconductor wafers into the interior chamber. The process cycle further includes etching type III-V semiconductor material away from the type III-V semiconductor wafer that is present in the interior chamber. The process cycle further includes removing the type III-V semiconductor wafer that is present in the interior chamber. The preliminary contamination control process includes forming a carbon containing protective material that completely covers exposed surfaces of the interior chamber.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: November 13, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Haghofer, Clemens Ostermaier
  • Patent number: 10115723
    Abstract: Complementary metal oxide semiconductor (CMOS) devices employing plasma-doped source/drain structures and related methods are disclosed. In certain aspects, a source and drain of a CMOS device are formed at end portions of a channel structure by plasma doping end portions of the channel structure above solid state solubility of the channel structure, and annealing the end portions for liquid phase epitaxy and activation (e.g., superactivation). In this manner, the source and drain can be integrally formed in the end portions of the channel structure to provide coextensive surface area contact between the source and drain and the channel structure for lower channel contact resistance. This is opposed to forming the source/drain using epitaxial growth that provides an overgrowth beyond the end portion surface area of the channel structure to reduce channel contact resistance, which may short adjacent channels structures.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: October 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Jeffrey Junhao Xu
  • Patent number: 9837487
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Lin, Chih-Lin Wang, Kang-Min Kuo
  • Patent number: 9831091
    Abstract: Embodiments described herein generally relate to a method and apparatus for plasma treating a process chamber. A substrate having a gate stack formed thereon may be placed in a process chamber, and hydrogen containing plasma may be used to treat the gate stack in order to cure the defects in the gate stack. As the result of hydrogen containing plasma treatment, the gate stack has lower leakage and improved reliability. To protect the process chamber from Hx+ ions and H* radicals generated by the hydrogen containing plasma, the process chamber may be treated with a plasma without the substrate placed therein and prior to the hydrogen containing plasma treatment. In addition, components of the process chamber that are made of a dielectric material may be coated with a ceramic coating including an yttrium containing oxide in order to protect the components from the plasma.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: November 28, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Wei Liu, Theresa Kramer Guarini, Huy Q. Nguyen, Malcolm Bevan, Houda Graoui, Philip A. Bottini, Bernard L. Hwang, Lara Hawrylchak, Rene George
  • Patent number: 9805912
    Abstract: A system, apparatus and method for increasing ion source lifetime in an ion implanter are provided. Oxidation of the ion source and ion source chamber poisoning resulting from a carbon and oxygen-containing source gas is controlled by utilizing a hydrogen co-gas, which reacts with free oxygen atoms to form hydroxide and water.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: October 31, 2017
    Assignee: Axcelis Technologies, Inc.
    Inventors: Neil K. Colvin, Tseh-Jen Hsieh
  • Patent number: 9735110
    Abstract: A semiconductor device according to the present invention includes a semiconductor substrate, and an interlayer dielectric film, formed on the semiconductor substrate, having a multilayer structure of a compressive stress film and a tensile stress film.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: August 15, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Ryosuke Nakagawa, Yuichi Nakao
  • Patent number: 9659784
    Abstract: Provided herein are approaches for patterning a semiconductor device. Exemplary approaches include providing a set of photoresist patterning features atop a substrate, the set of patterning features having a surface roughness characterized by a set of protrusions and a set of indentations. The approaches further include implanting first ions into a sidewall surface of the set of photoresist patterning features to form a film layer having a non-uniform thickness along the sidewall surface, wherein a thickness of the film layer formed over the indentations is greater than a thickness of the film layer formed over the protrusions. The approaches further include sputtering the sidewall surface of the photoresist patterning features following the formation of the film layer to modify a portion of the film layer and/or the set of protrusions, wherein the sputtering includes directing second ions to photoresist patterning features at an angle with the sidewall surface.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 23, 2017
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Maureen K. Petterson, Tristan Ma, John Hautala
  • Patent number: 9606532
    Abstract: A method for transporting a group of semiconductor wafers and a manufacturing system are provided. A semiconductor processing facility is provided. The semiconductor processing facility includes a first destination, a second destination, and a transport system configured to transport a group of semiconductor wafers from the first destination to the second destination. Real time information is collected, where the real time information includes information on a current process executing in the semiconductor processing facility and information on a transfer time. The information on the transfer time includes data that indicates an amount of time required to transport the group of semiconductor wafers from the first destination to the second destination. A request is issued to the transport system to effect the transportation of the group of semiconductor wafers from the first destination to the second destination. A timing of the request is based on the first and second data.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: March 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-Pin Huang, Wen-Chi Chien, Yuh-Dean Tsai, Bing-Yuan Cheng, Wei-Cheng Wang
  • Patent number: 9589768
    Abstract: The invention relates to an apparatus (1) for producing a reflection-reducing layer on a surface (21) of a plastics substrate (20). The apparatus comprises a first sputtering device (3) for applying a base layer (22) to the surface (21) of the plastics substrate (20), a plasma source (4) for plasma-etching the coated substrate surface (21), and a second sputtering device (5) for applying a protective layer (24) to the substrate surface (21). These processing devices (3, 4, 5) are arranged jointly in a vacuum chamber (2), which has inlets (8) for processing gases. In order to move the substrate (20) between the processing devices (3, 4, 5) in the interior of the vacuum chamber (2), a conveying apparatus (10) is provided which is preferably in the form of a rotary table (11). Furthermore, the invention relates to a method for producing such a reflection-reducing layer on the surface (21) of the plastics substrate (20).
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: March 7, 2017
    Assignee: Leybold Optics GmbH
    Inventors: Michael Scherer, Jurgen Pistner, Harro Hagedorn, Michael Klosch-Trageser
  • Patent number: 9583661
    Abstract: A grid for minimizing effects of ion divergence in plasma ion implant. The plasma grid is made of a flat plate having a plurality of holes, wherein the holes are arranged in a plurality of rows and a plurality of columns thereby forming beamlets of ions that diverge in one direction. A mask is used to form the implanted shapes on the wafer, wherein the holes in the mask are oriented orthogonally to the direction of beamlet divergence.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: February 28, 2017
    Assignee: INTEVAC, INC.
    Inventors: Vinay Prabhakar, Babak Adibi
  • Patent number: 9425265
    Abstract: Embodiments of a semiconductor die having a semiconductor device implemented on the semiconductor die and an edge termination structure around a periphery of the semiconductor device and methods of fabricating the same are disclosed. In one embodiment, a semiconductor die includes a semiconductor device and an edge termination structure around a periphery of the semiconductor device, where the edge termination structure includes negative features (e.g., trenches and/or divots) that vary dose in a corresponding edge termination region to approximate a desired dose profile. In one embodiment, the desired dose profile is a substantially decreasing or substantially linearly decreasing dose from an edge of a main junction of the semiconductor device to an edge of the edge termination region. In this manner, electric field crowding at the edge of the main junction of the semiconductor device is substantially reduced, which in turn substantially improves a break-down voltage of the semiconductor device.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: August 23, 2016
    Assignee: Cree, Inc.
    Inventors: Edward Robert Van Brunt, Vipindas Pala, Lin Cheng, Anant Kumar Agarwal
  • Patent number: 9425081
    Abstract: The disclosure relates to a method for implantation of atomic or ionic species into a batch of substrates made of semiconductor material, in which: each substrate made of semiconductor material is positioned on a respective support of a batch implanter, each substrate comprising a thin layer of electrical insulator on its surface; and a dose of at least one ionic or atomic species is implanted over the whole surface of the substrates, through their layer of insulator, so as to form a fragilization region within each substrate and to bound there a thin layer of semiconductor material between the thin layer of insulator and the fragilization region of the substrate, the implantation method being characterized in that, during the method, each support on which a substrate is positioned has at least two separate inclinations with respect to the plane orthogonal to the direction of implantation of the species in order to improve the implantation depth of the species in the substrate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 23, 2016
    Assignee: SOITEC
    Inventors: Nadia Ben Mohamed, Carole David, Camille Rigal
  • Patent number: 9390883
    Abstract: An ion implantation apparatus includes an ion beam directing unit, a substrate support, and a controller. The controller is configured to effect a relative movement between an ion beam passing the ion beam directing unit and the substrate support. A beam track of the ion beam on a substrate mounted on the substrate support includes circles or a spiral.
    Type: Grant
    Filed: February 11, 2014
    Date of Patent: July 12, 2016
    Assignee: Infineon Technologies AG
    Inventors: Alexander Breymesser, Stephan Voss, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 9331142
    Abstract: A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: May 3, 2016
    Assignee: VISHAY GENERAL SEMICONDUCTOR LLC
    Inventors: Shih-Kuan Chen, Wan-Lan Chiang, Ming-Tai Chiang, Chih-Ping Peng, Yih-Yin Lin
  • Patent number: 9331195
    Abstract: The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ru-Yi Su, Fu-Chih Yang, Chun Lin Tsai, Chih-Chang Cheng, Ruey-Hsin Liu
  • Patent number: 9318332
    Abstract: A grid for minimizing effects of ion divergence in plasma ion implant. The plasma grid is made of a flat plate having a plurality of holes, wherein the holes are arranged in a plurality of rows and a plurality of columns thereby forming beamlets of ions that diverge in one direction. A mask is used to form the implanted shapes on the wafer, wherein the holes in the mask are oriented orthogonally to the direction of beamlet divergence.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 19, 2016
    Assignee: INTEVAC, INC.
    Inventors: Vinay Prabhakar, Babak Adibi
  • Patent number: 9306069
    Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material, wherein a bottom portion of the upper portion comprises a dopant with a first peak concentration; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and an isolation structure surrounding the fin structure, wherein a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao Hsiung Wang, Chi-Wen Liu
  • Patent number: 9293623
    Abstract: Techniques for manufacturing a device are disclosed. In accordance with one exemplary embodiment, the technique may be realized as a method for forming a solar cell. The method may comprise: implanting p-type dopants into a substrate via a blanket ion implantation process; implanting n-type dopants into the substrate via the blanket ion implantation process; and performing a first annealing process to form the p-type region and performing a second annealing process to form a second n-type region.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: March 22, 2016
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Nicholas P. T. Bateman, Deepak A. Ramappa
  • Patent number: 9287136
    Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Ramachandran Muralidhar, Dae-Gyu Park, Xinhui Wang, Min Yang
  • Patent number: 9263249
    Abstract: The present invention is directed to a method and an apparatus for manufacturing a semiconductor device including step S22 to form an insulating film on a front surface of a semiconductor wafer that is a surface on which a semiconductor element is to be formed and on a back surface that is a surface opposing the front surface, step S26 to remove the insulating film formed on the back surface by selectively providing a first chemical on the back surface of the semiconductor wafer, and step S30 to remove the insulating film formed on the front surface by simultaneously immersing the plurality of semiconductor wafers in a second chemical.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: February 16, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Watanabe Tomohiro, Fumihiko Inoue
  • Patent number: 9245756
    Abstract: A method for fabricating a semiconductor device includes: implanting a first species into a substrate at a cold temperature to form a first region; and implanting a second species into the substrate at a hot temperature to form a second region that is adjacent to the first region.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: January 26, 2016
    Assignee: SK Hynix Inc.
    Inventors: Jae-Chun Cha, Seung-Woo Jin, An-Bae Lee, Il-Sik Jang
  • Patent number: 9230811
    Abstract: Disclosed are an active layer ion implantation method and an active layer ion implantation method for thin-film transistor. The active layer ion implantation method comprises: applying a photoresist on the active layer; and implanting ions into the active layer through the photoresist.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: January 5, 2016
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Zhanjie Ma
  • Patent number: 9214345
    Abstract: There is provided an ion implantation method, a composition for forming an ion implantation film and a resist underlayer film-forming composition. An ion implantation method including the steps of: forming a film by applying a film-forming composition containing a compound including an element in group 13, group 14, group 15, or group 16 and an organic solvent onto a substrate and baking the film-forming composition; and implanting impurity ions into the substrate from above through the film and introducing the element in group 13, group 14, group 15, or group 16 in the film into the substrate. The film-forming composition is a film-forming composition for ion implantation containing a compound including an element in group 13, group 14, group 15, or group 16, and an organic solvent. In addition, the underlayer film-forming composition contains a compound having at least two borate ester groups.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: December 15, 2015
    Assignee: Nissan Chemical Industries, Ltd.
    Inventors: Tomoya Ohashi, Takahiro Kishioka
  • Patent number: 9190314
    Abstract: A substrate is treated by means of at least one pulse of a luminous flux of determined wavelength. The substrate comprises an embedded layer that absorbs the luminous flux independently of the temperature. The embedded layer is interleaved between a first treatment layer and a second treatment layer. The first treatment layer has a coefficient of absorption of luminous flux that is low at ambient temperature and rises as the temperature rises. The luminous flux may be applied in several places of a surface of the first layer to heat regions of the embedded layer and generate a propagating thermal front in the first layer opposite the heated regions of the embedded layer, which generate constraints within the second layer.
    Type: Grant
    Filed: September 5, 2011
    Date of Patent: November 17, 2015
    Assignee: SOITEC
    Inventor: Michel Bruel
  • Patent number: 9178168
    Abstract: The present invention has an object of providing a light-emitting device including an OLED formed on a plastic substrate, which prevents degradation due to penetration of moisture or oxygen. On a plastic substrate, a plurality of films for preventing oxygen or moisture from penetrating into an organic light-emitting layer in the OLED (“barrier films”) and a film having a smaller stress than the barrier films (“stress relaxing film”), the film being interposed between the barrier films, are provided. Owing to a laminate structure, if a crack occurs in one of the barrier films, the other barrier film(s) can prevent moisture or oxygen from penetrating into the organic light emitting layer. The stress relaxing film, which has a smaller stress than the barrier films, is interposed between the barrier films, making it possible to reduce stress of the entire sealing film. Therefore, a crack due to stress hardly occurs.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: November 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Takayama, Mai Akiba
  • Patent number: 9105725
    Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, an active semiconductor layer, and a buried insulator layer interposed between the bulk substrate layer and the active semiconductor layer. A first source/drain (S/D) region includes a first stand-alone butting implant having a first butting width. A second S/D region includes a second stand-alone butting implant having a second butting width. A gate well-region is interposed between the first and second S/D regions. The gate well-region has a gate width that is greater than the first and second butting widths.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Wilfried E. Haensch, Gan Wang, Xin Wang, Yanfeng Wang, Keith Kwong Hon Wong
  • Patent number: 9064976
    Abstract: A method is provided for modeling charge distribution on FinFET sidewalls for estimating variability in device performance. The method includes: inputting structure parameters and simulation parameters for a FinFET structure; identifying a semiconductor-oxide interface in the structure, the interface including a plurality of atomic steps and a plurality of trapped charges; distributing charges at the interface; and performing device simulations and current-voltage analysis upon generating all samples of given number of devices.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: June 23, 2015
    Assignee: International Business Machines Corporation
    Inventors: Samarth Agarwal, Mohit Bajaj, Terence B. Hook
  • Patent number: 9048252
    Abstract: There are provided a semiconductor device having a drain region making a BLDD structure withstandable against a high voltage, sufficiently suppressing a hot-carrier deterioration, and having a high ESD withstandable characteristic, and a method for manufacturing the same. A semiconductor device is formed including a MOS transistor having a source region and a drain region both formed in a semiconductor substrate, and a channel region formed therebetween. At this time, the concentration of holes emitted form P-type impurities injected into the channel region and contributing an electrical conduction is lower at a side close to the drain region than at a side close to the source region. The drain region includes a drift region into which N-type impurities are injected. The drift region extends toward the channel region from the drain region except a nearby area to the surface of the semiconductor substrate.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: June 2, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Toshiro Sakamoto
  • Publication number: 20150147874
    Abstract: The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin.
    Type: Application
    Filed: November 25, 2013
    Publication date: May 28, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Cheng Huang, I-Ming Tseng, Yu-Ting Li, Chun-Hsiung Wang, Wu-Sian Sie, Yi-Liang Liu, Chia-Lin Hsu, Po-Chao Tsao, Chien-Ting Lin, Shih-Fang Tzou
  • Patent number: 9041105
    Abstract: An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: William F. Clark, Jr., Qizhi Liu, Robert M. Rassel, Yun Shi
  • Patent number: 9034741
    Abstract: A semiconductor device and method for manufacturing the same, wherein the method includes fabrication of field effect transistors (FET). The method includes growing a doped epitaxial halo region in a plurality of sigma-shaped source and drain recesses within a semiconductor substrate. An epitaxial stressor material is grown within the sigma-shaped source and drain recesses surrounded by the doped epitaxial halo forming source and drain regions with controlled current depletion towards the channel region to improve device performance. Selective growth of epitaxial regions allows for control of dopants profile and hence tailored and enhanced carrier mobility within the device.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: May 19, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Keith E. Fogel, Judson R. Holt, Balasubramanian Pranatharthiharan, Alexander Reznicek
  • Patent number: 9034743
    Abstract: A method of processing a workpiece is disclosed, where the ion chamber is first coated with the desired dopant species and another species. Following this conditioning process, a feedgas, which comprises fluorine and the desired dopant, is introduced to the chamber and ionized. Ions are then extracted from the chamber and accelerated toward the workpiece, where they are implanted without being first mass analyzed. The other species used during the conditioning process may be a Group 3, 4 or 5 element. The desired dopant species may be boron.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: May 19, 2015
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Peter F. Kurunczi, Bon-Woong Koo, John A. Frontiero, William T. Levay, Christopher J. Leavitt, Timothy J. Miller, Vikram M. Bhosle, John W. Graff, Nicholas P T Bateman
  • Patent number: 9029250
    Abstract: A method for producing semiconductor regions including impurities includes forming a trench in a first surface of a semiconductor body. Impurity atoms are implanted into a bottom of the trench. The trench is extended deeper into the semiconductor body, thereby forming a deeper trench. Impurity atoms are implanted into a bottom of the deeper trench.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: May 12, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Jens Peter Konrath, Ronny Kern, Hans-Joachim Schulze
  • Patent number: 9023720
    Abstract: After formation of a silicon Fin part on a silicon substrate, a thin film including an impurity atom which becomes a donor or an acceptor is formed so that a thickness of the thin film formed on the surface of an upper flat portion of the silicon Fin part becomes large relative to a thickness of the thin film formed to the surface of side wall portions of the silicon Fin part. A first diagonal ion implantation from a diagonal upper direction to the thin film is performed and subsequently a second diagonal ion implantation is performed from an opposite diagonal upper direction to the thin film. Recoiling of the impurity atom from the inside of the thin film to the inside of the side wall portions and to the inside of the upper flat portion is realized by performing the first and second diagonal ion implantations.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: May 5, 2015
    Assignee: Sen Corporation
    Inventors: Genshu Fuse, Michiro Sugitani