Using Additional Material To Improve Wettability Or Flow Characteristics (e.g., Flux, Etc.) Patents (Class 438/538)
-
Patent number: 8679929Abstract: A method of fabricating a one-time programmable (OTP) memory cell with improved read current in one of its programmed states, and a memory cell so fabricated. The OTP memory cell is constructed with trench isolation structures on its sides. After trench etch, and prior to filling the isolation trenches with dielectric material, a fluorine implant is performed into the trench surfaces. The implant may be normal to the device surface or at an angle from the normal. Completion of the cell transistor to form a floating-gate metal-oxide-semiconductor (MOS) transistor is then carried out. Improved on-state current (Ion) results from the fluorine implant.Type: GrantFiled: December 6, 2011Date of Patent: March 25, 2014Assignee: Texas Instruments IncorporatedInventors: Shanjen “Robert” Pan, Allan T. Mitchell, Weidong Tian
-
Patent number: 8026556Abstract: A method of manufacturing a resistive divider circuit, includes providing a silicon body having a plurality of opposing pairs of intermediate taps extending therefrom. Each tap comprises a thin silicon stem supporting a relatively wider silicon platform. A silicidation protection (SIPROT) layer is deposited over the body and intermediate taps and then patterned to expose the platform. A silicidation process is performed to silicidate the platform to form a contact pad of relatively low resistivity.Type: GrantFiled: April 19, 2007Date of Patent: September 27, 2011Assignee: NXP B.V.Inventor: Andy C. Negoi
-
Patent number: 7998842Abstract: The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.Type: GrantFiled: August 29, 2005Date of Patent: August 16, 2011Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Hyungjun Kim, Stephen M. Rossnagel
-
Patent number: 7670884Abstract: The manufacturing method of a substrate having a conductive layer has the steps of: forming an inorganic insulating layer over a substrate; forming an organic resin layer with a desired shape over the inorganic insulating layer; forming a low wettability layer with respect to a composition containing conductive particles on a first exposed portion of the inorganic insulating layer; removing the organic resin layer; and coating a second exposed portion of the inorganic insulating layer with a composition containing conductive particles and baking, thereby forming a conductive layer.Type: GrantFiled: November 10, 2008Date of Patent: March 2, 2010Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Gen Fujii, Masafumi Morisue, Hironobu Shoji, Junya Maruyama, Kouji Dairiki, Tomoyuki Aoki
-
Patent number: 7538024Abstract: A method for fabricating a dual-damascene copper structure includes providing a semiconductor substrate having a dielectric layer thereon and a dual-damascene hole positioned in the dielectric layer, wherein a portion of the semiconductor substrate is exposed in the dual-damascene hole. A PVD process and an atomic CVD process are sequentially performed to form a substrate-protecting layer and a tantalum nitride layer in the dual-damascene hole. And then a copper layer is formed in the dual-damascene hole.Type: GrantFiled: May 3, 2005Date of Patent: May 26, 2009Assignee: United Microelectronics Corp.Inventors: Hsien-Che Teng, Chin-Fu Lin, Meng-Chi Chen
-
Patent number: 7470604Abstract: The present invention, the quality of the surface of a substrate is improved and the wettability thereof is controlled by light irradiation from the reverse side with respect to the substrate having the conductive layer. A conductive material or an insulating material is adhered on the modified surface by discharging it (including jetting, etc.), or the like to form a conductive layer and an insulating layer. The processing efficiency by the light can be enhanced by function of the light absorption and energy radiation of the photocatalytic substance. Furthermore, the mask layer is formed selectively on the conductive layer and the wettability of the region on the conductive layer that is a non-irradiation region is also controlled.Type: GrantFiled: October 6, 2005Date of Patent: December 30, 2008Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Gen Fujii
-
Patent number: 7329604Abstract: The method for fabricating a semiconductor device comprises the step of forming a Co film 72 on a gate electrode 30 having a gate length Lg of below 50 nm including 50 nm; the first thermal processing step of making thermal processing to react the Co film 72 and the gate electrode 30 with each other to form a CoSi film 76a on the upper part of the gate electrode 30; the step of selectively etching off the unreacted part of the Co film 72; and the second thermal processing step of making thermal processing to react the CoSi film 76a and the gate electrode 30 with each other to form a CoSi2 film 42a on the upper part of the gate electrode 30, wherein in the first thermal processing step, the CoSi film 76a is formed so that the ratio h/w of the height h of the CoSi film 76a to the width w of the CoSi film 76a is below 0.7 including 0.7.Type: GrantFiled: April 7, 2005Date of Patent: February 12, 2008Assignee: Fujtisu LimitedInventor: Kazuo Kawamura
-
Patent number: 7268065Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.Type: GrantFiled: June 18, 2004Date of Patent: September 11, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
-
Patent number: 7189623Abstract: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate.Type: GrantFiled: August 31, 2005Date of Patent: March 13, 2007Assignee: Micron Technology, Inc.Inventors: Salman Akram, Akram Ditali
-
Patent number: 7176115Abstract: The present invention provides a manufacturing method that allows a Group III nitride substrate with a low dislocation density to be manufactured, and a semiconductor device that is manufactured using the manufacturing method. The manufacturing method includes, in an atmosphere including nitrogen, allowing a Group III element and the nitrogen to react with each other in an alkali metal melt to cause generation and growth of Group III nitride crystals. In the manufacturing method, a plurality of portions of a Group III nitride semiconductor layer are prepared, selected as seed crystals, and used for at least one of the generation and the growth of the Group III nitride crystals, and then surfaces of the seed crystals are brought into contact with the alkali metal melt.Type: GrantFiled: March 18, 2004Date of Patent: February 13, 2007Assignees: Matsushita Electric Industrial Co., Ltd.Inventors: Yasuo Kitaoka, Hisashi Minemoto, Isao Kidoguchi, Akihiko Ishibashi, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
-
Patent number: 6943097Abstract: The present invention provides metallic films containing a Group IVB or VB metal, silicon and optionally nitrogen by utilizing atomic layer deposition (ALD). In particularly, the present invention provides a low temperature thermal ALD method of forming metallic silicides and a plasma-enhanced atomic layer deposition (PE-ALD) method of forming metallic silicon nitride film. The methods of the present invention are capable of forming metallic films having a thickness of a monolayer or less on the surface of a substrate. The metallic films provided in the present invention can be used for contact metallization, metal gates or as a diffusion barrier.Type: GrantFiled: August 19, 2003Date of Patent: September 13, 2005Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Hyungjun Kim, Stephen M. Rossnagel
-
Patent number: 6846730Abstract: A method of etching nitride over oxide is provided for the formation of vertical profile nitride spacers with high uniformity while maintaining the integrity of underlying thin oxide layers. The method includes providing a first gas flow including a first fluorocarbon and a second fluorocarbon at a first ratio, applying a first quantity of power to the first gas flow to create a first plasma, etching a first portion of a silicon nitride layer with the first plasma, providing a second gas flow including the first fluorocarbon and the second fluorocarbon at a second ratio greater than the first ratio, applying a second quantity of power to the second gas flow to create a second plasma, and etching a second portion of the silicon nitride layer with the second plasma.Type: GrantFiled: March 12, 2004Date of Patent: January 25, 2005Assignee: ProMOS Technologies Inc.Inventors: Barbara A. Haselden, John Lee
-
Patent number: 6737340Abstract: The present invention provides a system and method for creating self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. A self-doping negative contact may be formed from unalloyed silver which may be applied to the silicon substrate by either sputtering, screen printing a paste or evaporation. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag—Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. The temperature is then decreased towards the eutectic temperature.Type: GrantFiled: June 19, 2002Date of Patent: May 18, 2004Assignee: Ebara CorporationInventors: Daniel L. Meier, Hubert P. Davis, Ruth A. Garcia, Joyce A. Jessup
-
Patent number: 6632730Abstract: The present invention provides a system and method for creating self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. A self-doping negative contact may be formed from unalloyed silver which may be applied to the silicon substrate by either sputtering, screen printing a paste or evaporation. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag—Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. The temperature is then decreased towards the eutectic temperature.Type: GrantFiled: March 29, 2000Date of Patent: October 14, 2003Assignee: Ebara Solar, Inc.Inventors: Daniel L. Meier, Hubert P. Davis, Ruth A. Garcia, Joyce A. Jessup
-
Patent number: 6362083Abstract: A method for fabricating a locally reinforced metallic microfeature on a substrate provided preferably with an electrical contacting or a driving circuit, and on an organic, patterned sacrificial layer, which is removed after the metallic microfeature is applied, is described. In fabricating the local reinforcement of the microfeature, at least one further organic layer, formed as a mask, is deposited, which is likewise removed following pattern delineation of the metallic layer.Type: GrantFiled: November 24, 1999Date of Patent: March 26, 2002Assignee: Robert Bosch GmbHlInventors: Roland Mueller-Fiedler, Juergen Graf, Stefan Kessel, Joerg Rehder