Fusing Dopant With Substrate (i.e., Alloy Junction) Patents (Class 438/537)
  • Patent number: 9659778
    Abstract: Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies AG
    Inventors: Knut Stahrenberg, Jin-Ping Han
  • Patent number: 8975156
    Abstract: A method of sealing a first wafer and a second wafer each made of semiconducting materials, including: implanting a metallic species in at least the first wafer, assembling the first wafer and the second wafer by molecular bonding, and after the molecular bonding, forming a metallic ohmic contact including alloys formed between the implanted metallic species and the semiconducting materials of the first wafer and the second wafer, the metallic ohmic contact being formed at an assembly interface between the first wafer and the second wafer, wherein the forming includes causing the implanted metallic species to diffuse towards the interface between the first wafer with the second wafer and beyond the interface.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: March 10, 2015
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Stephane Pocas, Hubert Moriceau, Jean-Francois Michaud
  • Patent number: 8962459
    Abstract: A method selectively diffuses dopants into a substrate wafer. The method comprises blanket depositing a doped liquid precursor including dopants on a surface of the substrate wafer to create a doped film on the surface of the substrate wafer, selectively forming a diffusion source in the doped film to selectively diffuse the dopants into the substrate wafer, and heating the doped film on the substrate wafer, wherein said heating the doped film diffuses the dopants from the doped film into the substrate wafer.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: February 24, 2015
    Assignee: Piquant Research LLC
    Inventor: Daniel Inns
  • Patent number: 8828790
    Abstract: A method for local contacting and local doping of a semiconductor layer including the following process steps: A) Generation of a layer structure on the semiconductor layer through i) application of at least one intermediate layer on one side of the semiconductor layer, and ii) application of at least one metal layer onto the intermediate layer last applied in step i), wherein the metal layer at least partly covers the last applied intermediate layer, B) Local heating of the layer structure in such a manner that in a local region a short-time melt-mixture of at least partial regions of at least the layers: metal layer, intermediate layer and semiconductor layer, forms. After solidification of the melt-mixture, a contacting is created between metal layer and semiconductor layer. It is essential that in step A) i) at least one intermediate layer designed as dopant layer is applied, which contains a dopant wherein the dopant has a greater solubility in the semiconductor layer than the metal of the metal layer.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: September 9, 2014
    Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V.
    Inventors: Ralf Preu, Andreas Grohe, Daniel Biro, Jochen Rentsch, Marc Hofmann, Jan-Frederik Nekarda, Andreas Wolf
  • Patent number: 8729711
    Abstract: A semiconductor device includes a semiconductor substrate having a first surface being an element formation surface, and a second surface opposite to the first surface; a through-hole formed to penetrate the semiconductor substrate from the first surface to the second surface; an insulating film formed on an inner wall of the through-hole; a barrier film formed on the inner wall of the through-hole with the insulating film interposed therebetween; and a conductive portion formed to fill the through-hole provided with the insulating film and the barrier film. A gettering site is formed in a portion of the semiconductor substrate around the through-hole at least near a side of the first surface.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: May 20, 2014
    Assignee: Panasonic Corporation
    Inventor: Taichi Nishio
  • Patent number: 8669169
    Abstract: Methods for selectively diffusing dopants into a substrate wafer are provided. A liquid precursor is doped with dopants. The liquid precursor is selected from a group comprising monomers, polymers, and oligomers of silicon and hydrogen. The doped liquid precursor is deposited on a surface of the substrate wafer to create a doped film. The doped film is heated on the substrate wafer for diffusing the dopants from the doped film into the substrate wafer at different diffusion rates to create a heavily diffused region and a lightly diffused region in the substrate wafer. The method disclosed herein further comprises selective curing of the doped film on the surface of the substrate wafer. The selectively cured doped film acts as a diffusion source for selectively diffusing the dopants into the substrate wafer.
    Type: Grant
    Filed: September 1, 2010
    Date of Patent: March 11, 2014
    Assignee: Piquant Research LLC
    Inventor: Daniel Inns
  • Patent number: 8658454
    Abstract: Methods of fabricating solar cells are described. A porous layer may be formed on a surface of a substrate, the porous layer including a plurality of particles and a plurality of voids. A solution may be dispensed into one or more regions of the porous layer to provide a patterned composite layer. The substrate may then be heated.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: February 25, 2014
    Assignee: SunPower Corporation
    Inventors: Thomas Pass, Robert Rogers
  • Patent number: 8614115
    Abstract: A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: December 24, 2013
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Harold J. Hovel, Rainer Klaus Krause, Kevin S. Petrarca, Gerd Pfeiffer, Kevin M. Prettyman, Carl Radens, Brian C. Sapp
  • Patent number: 8501604
    Abstract: A method of forming a doped region in a semiconductor layer of a substrate by alloying with doping elements is disclosed. In one aspect, the method includes screen printing a paste layer of doping element paste to the substrate and firing the screen printed paste layer of doping element paste, wherein a highly pure doping element layer is applied to the semiconductor layer after which the paste layer is screen printed to the doping element layer.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: August 6, 2013
    Assignee: IMEC
    Inventor: Sukhvinder Singh
  • Patent number: 8481419
    Abstract: A method for producing an electrically conducting metal contact on a semiconductor component having a coating on the surface of a semiconductor substrate. In order to keep transfer resistances low while maintaining good mechanical strength, the invention proposes applying a particle-containing fluid onto the coating, where the particles contain at least metal particles and glass frits, curing the fluid while simultaneously forming metal areas in the substrate through heat treatment, removing the cured fluid and the areas of the coating covered by the fluid, and depositing, for the purposes of forming the contact without using intermediate layers, electrically conducting material from a solution onto areas of the semiconductor component in which the coating is removed while at the same time conductively connecting the metal areas present in said areas on the substrate.
    Type: Grant
    Filed: November 26, 2009
    Date of Patent: July 9, 2013
    Assignee: SHOTT Solar AG
    Inventors: Jorg Horzel, Gunnar Schubert, Stefan Dauwe, Peter Roth, Tobias Droste, Wilfried Schmidt, Ingrid Ernst
  • Patent number: 8455323
    Abstract: There is provided a method for manufacturing a semiconductor wafer, comprising: performing heating so that metals dissolve into semiconductors of the wafer to form a semiconductor-metal compound; and performing cooling so that the formed semiconductor-metal compound retrogradely melt to form a mixture of the metals and the semiconductors. According to embodiments of the present invention, it is possible to achieve wafers of a high purity applicable to the semiconductor manufacture.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: June 4, 2013
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang, Chao Zhao
  • Publication number: 20130032883
    Abstract: Field effect transistors fabricated using atomic layer doping processes are disclosed. In accordance with an embodiment of an atomic layer doping method, a semiconducting surface and a dopant gas mixture are prepared. Further, a dopant layer is grown on the semiconducting surface by applying the dopant gas mixture to the semiconducting surface under a pressure that is less than 500 Torr and a temperature that is between 300° C. and 750° C. The dopant layer includes at least 4×1020 active dopant atoms per cm3 that react with atoms on the semiconducting surface such that the reacted atoms increase the conductivity of the semiconducting surface.
    Type: Application
    Filed: August 4, 2011
    Publication date: February 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Young-Hee Kim, Isaac Lauer, Ramachandran Muralidhar, Dae-Gyu Park, Xinhui Wang, Min Yang
  • Patent number: 8216926
    Abstract: Method of producing a partly or completely semi-insulating or p-type doped ZnO substrate from an n-type doped ZnO substrate, in which the n-type doped ZnO substrate is brought into contact with an anhydrous molten salt chosen from anhydrous molten sodium nitrate, lithium nitrate, potassium nitrate and rubidium nitrate. Partly or completely semi-insulating or p-type doped ZnO substrate, said substrate being in particular in the form of a thin layer, film or in the form of nanowires; and said substrate being doped at the same time by an element chosen from Na, Li, K and Rb; by N; and by O; it being furthermore possible for ZnO or GaN to be epitaxially grown on this substrate. Electronic, optoelectronic or electro-optic device such as a light-emitting diode (LED) comprising this substrate.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: July 10, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Maurice Couchaud, Céline Chevalier
  • Publication number: 20120149181
    Abstract: There is provided a method for manufacturing a semiconductor wafer, comprising: performing heating so that metals dissolve into semiconductors of the wafer to form a semiconductor-metal compound; and performing cooling so that the formed semiconductor-metal compound retrogradely melt to form a mixture of the metals and the semiconductors. According to embodiments of the present invention, it is possible to achieve wafers of a high purity applicable to the semiconductor manufacture.
    Type: Application
    Filed: February 25, 2011
    Publication date: June 14, 2012
    Applicant: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huicai Zhong, Qingqing Liang, Chao Zhao
  • Patent number: 8174074
    Abstract: A semiconductor device, an integrated circuit, and method for fabricating the same are disclosed. The semiconductor device includes a gate stack formed on an active region of a silicon-on-insulator substrate. A gate spacer is formed over the gate stack. A source region that includes embedded silicon germanium is formed within the semiconductor layer. A drain region that includes embedded silicon germanium is formed within the semiconductor layer. The source region includes an angled implantation region that extends into the embedded silicon germanium of the source region, and is asymmetric relative to the drain region.
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: May 8, 2012
    Assignee: International Business Machines Corporation
    Inventors: Chung-Hsun Lin, Isaac Lauer, Jeffrey W. Sleight
  • Publication number: 20110309489
    Abstract: A method of forming a doped region in a semiconductor layer of a substrate by alloying with doping elements is disclosed. In one aspect, the method includes screen printing a paste layer of doping element paste to the substrate and firing the screen printed paste layer of doping element paste, wherein a highly pure doping element layer is applied to the semiconductor layer after which the paste layer is screen printed to the doping element layer.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 22, 2011
    Applicant: IMEC
    Inventor: Sukhvinder Singh
  • Publication number: 20110233711
    Abstract: A method for local contacting and local doping of a semiconductor layer including the following process steps: A) Generation of a layer structure on the semiconductor layer through i) application of at least one intermediate layer on one side of the semiconductor layer, and ii) application of at least one metal layer onto the intermediate layer last applied in step i), wherein the metal layer at least partly covers the last applied intermediate layer, B) Local heating of the layer structure in such a manner that in a local region a short-time melt-mixture of at least partial regions of at least the layers: metal layer, intermediate layer and semiconductor layer, forms. After solidification of the melt-mixture, a contacting is created between metal layer and semiconductor layer. It is essential that in step A) i) at least one intermediate layer designed as dopant layer is applied, which contains a dopant wherein the dopant has a greater solubility in the semiconductor layer than the metal of the metal layer.
    Type: Application
    Filed: August 20, 2009
    Publication date: September 29, 2011
    Applicant: Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V.
    Inventors: Ralf Preu, Andreas Grohe, Daniel Biro, Jochen Rentsch, Marc Hofmann, Jan-Frederik Nekarda, Andreas Wolf
  • Publication number: 20110021010
    Abstract: A method deposits an undoped silicon layer on a primary layer, deposits a cap layer on the undoped silicon layer, patterns a masking layer on the cap layer, and patterns the undoped silicon layer into silicon mandrels. The method incorporates impurities into sidewalls of the silicon mandrels in a process that leaves sidewall portions of the silicon mandrels doped with impurities and that leaves central portions of at least some of the silicon mandrels undoped. The method removes the cap layer to leave the silicon mandrels standing on the primary layer and performs a selective material removal process to remove the central portions of the silicon mandrels and to leave the sidewall portions of the silicon mandrels standing on the primary layer. The method patterns at least the primary layer using the sidewall portions of the silicon mandrels as a patterning mask and removes the sidewall portions of the silicon mandrels to leave at least the primary layer patterned.
    Type: Application
    Filed: July 27, 2009
    Publication date: January 27, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Toshiharu Furukawa
  • Patent number: 7629243
    Abstract: A method for manufacturing a semiconductor device is provided, which includes forming a gate insulating film on a semiconductor substrate, forming a first layer on the gate insulating film, the first layer containing a first p-type impurity and, an amorphous or polycrystalline formed of Si1-xGex (0?x<0.25), subjecting the first layer to a first heat treatment wherein the first layer is heated for 1 msec or less at a temperature higher than 1100° C., forming a second layer on the first layer, the second layer containing a second p-type impurity and formed of amorphous silicon or polycrystalline silicon, the second p-type impurity having a smaller covalent bond radius than that of the first p-type impurity, and subjecting the second layer to a second heat treatment to heat the second layer at a temperature ranging from 800° C. to 1100° C.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: December 8, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunehiro Ino, Akio Kaneko, Nobutoshi Aoki
  • Publication number: 20090162988
    Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.
    Type: Application
    Filed: February 27, 2009
    Publication date: June 25, 2009
    Inventors: Thomas Keena, Ki Chang, Francine Y. Robb, Mingjiao Liu, Ali Salih, John Michael Parsey, JR., George Chang
  • Publication number: 20090098718
    Abstract: In order to produce doping regions (DG) in a substrate (S) having different dopings with the aid of a single mask (DM) different mask regions are provided which have elongated mask openings (MO) having different orientations relative to the spatial direction of an oblique implantation. The substrate is rotated between the first and second oblique implantations, wherein during the first oblique implantation maximum and minimum shadings in the different mask regions are opposite one another and the conditions are precisely reversed during the second oblique implantation after the rotation of the substrate.
    Type: Application
    Filed: November 3, 2005
    Publication date: April 16, 2009
    Inventors: Martin Knaipp, Rainer Minixhofer, Martin Schrems
  • Patent number: 7268065
    Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: September 11, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
  • Patent number: 7262119
    Abstract: A method of fabricating a semiconductor wafer includes fabricating a gate electrode on a silicon substrate of the semiconductor device and incorporating germanium into the silicon substrate thereafter.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: August 28, 2007
    Assignee: LSI Corporation
    Inventor: Mohammad Mirabedini
  • Patent number: 7189623
    Abstract: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: March 13, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Akram Ditali
  • Patent number: 7109098
    Abstract: A method of forming semiconductor junctions in a semiconductor material of a workpiece includes ion implanting dopant impurities in selected regions of the semiconductor material, introducing an optical absorber material precursor gas into a chamber containing the workpiece, generating an RF oscillating toroidal plasma current in a reentrant path that includes a process zone overlying the workpiece by applying RF source power, so as to deposit a layer of an optical absorber material on the workpiece, and optically annealing the workpiece so as to activate dopant impurities in the semiconductor material.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: September 19, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Kartik Ramaswamy, Hiroji Hanawa, Biagio Gallo, Kenneth S. Collins, Kai Ma, Vijay Parihar, Dean Jennings, Abhilash J. Mayur, Amir Al-Bayati, Andrew Nguyen
  • Patent number: 7060547
    Abstract: A method for forming a junction region of a semiconductor device is disclosed. The steps of the method include providing a semiconductor substrate. A gate structure is formed on the semiconductor substrate. A dopant is implanted into the semiconductor substrate to form the junction region. An insulator layer is formed on the gate structure and the semiconductor substrate. A carbon-containing plasma treatment is performed to the insulator layer. A spacer is formed on a side-wall of the gate structure and the dopant is implanted into the semiconductor substrate to form a source/drain region next to the junction region. A heat treatment is performed to the semiconductor substrate.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: June 13, 2006
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Kun Chen, Neng-Hui Yang, Chin-Cheng Chien, Hsiang-Ying Wang
  • Patent number: 7012008
    Abstract: In a two-step spacer fabrication process for a non-volatile memory device, a thin oxide layer is deposited on a wafer substrate leaving a gap in the core of the non-volatile memory device. Implantation and/or oxide-nitride-oxide removal can be accomplished through this gap. After implantation, a second spacer is deposited. After the second spacer deposition, a periphery spacer etch is performed. By the above method, a spacer is formed.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: March 14, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeffrey A. Shields, Tuan D. Pham, Mark T. Ramsbey, Yu Sun, Angela T. Hui, Maria Chow Chan
  • Patent number: 6872644
    Abstract: A semiconductor device includes source and drain contact regions which include a non-compounded combination of a semiconductor material and at least one metal. The metal may include an elemental metal, such as gold or aluminum, or may include an intermetallic. The contact regions may be formed by depositing a limited amount of the at least one metal on a source and a drain of the device, and annealing the device to induce diffusion of the at least one metal into the source and drain. The annealing time and temperature may be selected to limit diffusion of the at least one metal.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: March 29, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthew S. Buynoski, Witold P. Maszara
  • Patent number: 6784018
    Abstract: A first conductive electrode material is formed on a substrate. Chalcogenide comprising material is formed thereover. The chalcogenide material comprises AxSey. A silver comprising layer is formed over the chalcogenide material. The silver is irradiated effective to break a chalcogenide bond of the chalcogenide material at an interface of the silver comprising layer and chalcogenide material and diffuse at least some of the silver into the chalcogenide material. After the irradiating, the chalcogenide material outer surface is exposed to an iodine comprising fluid effective to reduce roughness of the chalcogenide material outer surface from what it was prior to the exposing. After the exposing, a second conductive electrode material is deposited over the chalcogenide material, and which is continuous and completely covering at least over the chalcogenide material, and the second conductive electrode material is formed into an electrode of the device.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Kristy A. Campbell, John T. Moore
  • Patent number: 6709959
    Abstract: A semiconductor device is fabricated by introducing an impurity element into a Si substrate by an ion implantation process with an energy set such that the depth of a junction formed in the Si substrate by the impurity element is less than about 50 nm, and then annealing the substrate, wherein the method further includes a step of removing an oxide film from a surface of the Si substrate before the step of ion implantation process.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: March 23, 2004
    Assignee: Fujitsu Limited
    Inventors: Masataka Kase, Toshiki Miyake, Mitsuaki Hori, Kenichi Hikazutani, Manabu Nakamura, Takayuki Wada, Yoshikazu Kataoka
  • Patent number: 6703295
    Abstract: The present invention provides a system and method for creating self-doping contacts to silicon devices in which the contact metal is coated with a layer of dopant and subjected to high temperature, thereby alloying the silver with the silicon and simultaneously doping the silicon substrate and forming a low-resistance ohmic contact to it. A self-doping negative contact may be formed from unalloyed silver which may be applied to the silicon substrate by either sputtering, screen printing a paste or evaporation. The silver is coated with a layer of dopant. Once applied, the silver, substrate and dopant are heated to a temperature above the Ag—Si eutectic temperature (but below the melting point of silicon). The silver liquefies more than a eutectic proportion of the silicon substrate. The temperature is then decreased towards the eutectic temperature.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: March 9, 2004
    Assignee: Ebara Corporation
    Inventors: Daniel L. Meier, Hubert P. Davis, Ruth A. Garcia, Joyce A. Jessup
  • Patent number: 6531379
    Abstract: The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the present invention comprising a step of physically contacting a semiconductor surface having a layer of a dopant/bandgap source material thereon such that upon said physical contact impurity atoms from the dopant/bandgap source material are driven into the semiconductor substrate.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: March 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, John Joseph Ellis-Monaghan, James Albert Slinkman
  • Patent number: 6507626
    Abstract: A bandpass phase tracker automatically samples at prescribed carrier phases when digitizing a vestigial-sideband intermediate-frequency signal, which VSB I-F signal is modulated in accordance with a baseband symbol code of a prescribed symbol frequency. Heterodyning circuitry mixes oscillations from a local oscillator with the VSB I-F signal received from the I-F amplifier to generate an analog low-frequency heterodyne signal offset from zero frequency. The heterodyne signal is digitized in accordance with a first sampling clock signal to supply input signal for digital demodulation circuitry that demodulates the VSB I-F signal to supply real and imaginary components of a demodulated signal at baseband. The real component of the demodulated signal is supplied to an equalizer and symbol decoded; the imaginary component controls the frequency and phase of the local oscillator.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: January 14, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Allen LeRoy Limberg
  • Patent number: 6500741
    Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: December 31, 2002
    Assignee: Fabtech, Inc.
    Inventors: Walter R. Buchanan, Roman J. Hamerski
  • Patent number: 6479885
    Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant, material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: November 12, 2002
    Assignee: Fabtech, Inc.
    Inventors: Walter R. Buchanan, Roman J. Hamerski
  • Publication number: 20020048891
    Abstract: A semiconductor material and a method for forming the same, said semiconductor material having produced by a process comprising melting a noncrystal semiconductor film containing therein carbon, nitrogen, and oxygen each at a concentration of 5×1019 atoms·cm−3 or lower, preferably 1×1019 atoms·cm−3 or lower, by irradiating a laser beam or a high intensity light equivalent to a laser beam to said noncrystal semiconductor film, and then recrystallizing the thus molten amorphous silicon film. The present invention provides thin film semiconductors having high mobility at an excellent reproducibility, said semiconductor materials being useful for fabricating thin film semiconductor devices such as thin film transistors improved in device characteristics.
    Type: Application
    Filed: March 9, 1998
    Publication date: April 25, 2002
    Inventors: SHUNPEI YAMAZAKI, HONGYONG ZHANG, NAOTO KUSUMOTO, YASUHIKO TAKEMURA
  • Patent number: 6376346
    Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: April 23, 2002
    Assignee: FabTech, Inc.
    Inventors: Walter R. Buchanan, Roman J. Hamerski
  • Publication number: 20020022367
    Abstract: A method for fabricating a semiconductor substrate includes forming a suicide layer at a predetermined portion of a semiconductor substrate, implanting two or more impurity ions before annealing, and forming an impurity region in the semiconductor substrate by annealing the silicide layer and by diffusing the impurity ions from the silicide layer into the semiconductor substrate. Accordingly, the present invention can improve reliability and performance of a semiconductor device by reducing dopant loss and leakage current of a PN junction in the substrate and by decreasing a sheet resistance of the silicide layer. The dose of the second implanter ions is about one hundred to one thousand times less than the dose of the first implanted ions.
    Type: Application
    Filed: November 5, 1999
    Publication date: February 21, 2002
    Inventors: JI SOO PARK, DONG KYUN SON
  • Patent number: 6287881
    Abstract: A method of fabricating a semiconductor device having active components grown on a substrate, involves providing a semiconductor substrate on which the active components are grown, and doping the semiconductor substrate to render it non conductive and thereby reduce parasitic capacitance between active components thereon. The components typically comprise a VCSEL and monitor. The doped substrate reduces parasitic capacitance.
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: September 11, 2001
    Assignee: Mitel Semiconductor AB
    Inventors: Jan Jonssön, Mikael Wickström