Abstract: A classifier circuit includes an array of dual gate graphene transistors, each of the transistors having a source, a top gate receiving one of an input voltage to be evaluated or a reference voltage, a bottom or embedded gate receiving the other of the input voltage or reference voltage and a drain, the source and drain contacting a graphene channel One of the source and the drain is connected to a voltage source. A common output combines output current of a plurality of the dual gate graphene transistors, which current varies in response to the difference between the input voltage and the reference voltage. A method for forming a classifier transistor with high remanent polarization forms dielectric with ferroelectric capability on a low resistivity substrate. A non-ferroelectric oxide layer is formed on the dielectric. A window is opened, and a graphene channel is formed in the window.

Abstract: A method of implementing bandgap tuning of a graphene-based switching device includes subjecting a bi-layer graphene to an electric field while simultaneously subjecting the bi-layer graphene to an applied strain that reduces an interlayer spacing between the bi-layer graphene, thereby creating a bandgap in the bi-layer graphene.

Abstract: A pattern film forming method includes a step of producing a transfer sheet in which a thin film is formed on a surface of a sheet-shaped material and a step of pressing the thin film against a pattern film formation surface of the substrate with a pressing member having convex portions corresponding to the pattern film from a reverse surface of the transfer sheet opposite to the thin film or a reverse surface of the substrate opposite to the pattern film formation surface to transfer the thin film to the substrate. A pattern film forming apparatus includes a sheet supply device, a pressing device and a substrate transport device. A high-definition pattern film having a desired pattern and a sharp edge can be formed with high productivity.

Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.

Abstract: A method of forming a transistor gate includes forming a gate oxide layer over a semiconductive substrate. Chlorine is provided within the gate oxide layer. A gate is formed proximate the gate oxide layer. In another method, a gate and a gate oxide layer are formed in overlapping relation, with the gate having opposing edges and a center therebetween. At least one of chlorine or fluorine is concentrated in the gate oxide layer within the overlap more proximate at least one of the gate edges than the center. Preferably, the central region is substantially undoped with fluorine and chlorine. The chlorine and/or fluorine can be provided by forming sidewall spacers proximate the opposing lateral edges of the gate, with the sidewall spacers comprising at least one of chlorine or fluorine. The spacers are annealed at a temperature and for a time effective to diffuse the fluorine or chlorine into the gate oxide layer to beneath the gate.

Abstract: A method is provided for tuning (i.e. modifying, changing) the impedance of semiconductor components or devices using a focused heating source. The method may be exploited for finely tuning the impedance of semiconductor components or devices, by modifying the dopant profile of a region of low dopant concentration (i.e. increasing the dopant concentration) by diffusion of dopants from adjacent regions of higher dopant concentration through the melting action of a focused heating source, for example a laser. The present invention is in particular directed to the use of lasers in relation to circuits for the creation of conductive links and pathways where none existed before. The present invention more particularly relates to a means wherein impedance modification (i.e. trimming or tuning) may advantageously be carried out as a function of the location of one or more conductive bridge(s) along the length of a gap region.

Abstract: The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the present invention comprising a step of physically contacting a semiconductor surface having a layer of a dopant/bandgap source material thereon such that upon said physical contact impurity atoms from the dopant/bandgap source material are driven into the semiconductor substrate.

Abstract: A structure comprising a thin layer (2) that can be integral with a support (3), the thin layer being a layer of a semiconductor material made insulating by ion implantation except for at least one zone that permits a vertical electrical connection through the entire thickness of the thin layer (2). A method of manufacturing such a structure is also disclosed.

Abstract: Integrated circuits, semiconductor devices and methods for making the same are described. Each embodiment shows a diffused, doped backside layer in a device wafer that is oxide bonded to a handle wafer. The diffused layer may originate in the device handle, in the handle wafer, in the bond oxide or in an additional semiconductor layer of polysilicon or epitaxial silicon. The methods use a thermal bond oxide or a combination of a thermal and deposited oxide.