Abstract: A photoluminescence measurement system can include an optical source.

Abstract: A method for forming doping regions is disclosed, including providing a substrate, forming a first-type doping material on the substrate and forming a second-type doping material on the substrate, wherein the first-type doping material is separated from the second-type doping material by a gap; forming a covering layer to cover the substrate, the first-type doping material and the second-type doping material; and performing a thermal diffusion process to diffuse the first-type doping material and the second-type doping material into the substrate.

Abstract: A method for forming doping regions is disclosed, including providing a substrate, forming a first-type doping material on the substrate and forming a second-type doping material on the substrate, wherein the first-type doping material is separated from the second-type doping material by a gap; forming a covering layer to cover the substrate, the first-type doping material and the second-type doping material; and performing a thermal diffusion process to diffuse the first-type doping material and the second-type doping material into the substrate.

Abstract: Disclosed herein is a method for fabricating a complementary tunneling field effect transistor based on a standard CMOS IC process, which belongs to the field of logic devices and circuits of field effect transistors in ultra large scaled integrated (ULSI) circuits. In the method, an intrinsic channel and body region of a TFET are formed by means of complementary P-well and N-well masks in the standard CMOS IC process to form a well doping, a channel doping and a threshold adjustment by implantation. Further, a bipolar effect in the TFET can be inhibited via a distance between a gate and a drain on a layout so that a complementary TFET is formed. In the method according to the invention, the complementary tunneling field effect transistor (TFET) can be fabricated by virtue of existing processes in the standard CMOS IC process without any additional masks and process steps.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

Abstract: Disclosed is a coating liquid for impurity diffusion comprising: (A) a polyvinyl alcohol resin having a 1,2-diol structural unit represented by the following general formula (1): wherein R1, R2 and R3 each independently represent a hydrogen atom or an organic group, X represents a single bond or a bond chain, and R4, R5 and R6 each independently represent a hydrogen atom or an organic group; (B) an impurity; and (C) water. The coating liquid for impurity diffusion is highly stable, and exhibits excellent printing properties; for example, when printing is continuously carried out for a longer period of time or resumed after a pause. Accordingly, the coating liquid for impurity diffusion is particularly suitable as a coating liquid for impurity diffusion for use for applying by screen printing.

Abstract: Provided is a semiconductor laser, wherein (?a??w)>15 (nm) and Lt<25 (?m), where ?w is the wavelength of light corresponding to the band gap of the active layer disposed at a position within a distance of 2 ?m from one end surface in a resonator direction, ?a is the wavelength of light corresponding to the band gap of the active layer disposed at a position that is spaced a distance of equal to or more than ( 3/10)L and ?( 7/10)L from the one end surface in a resonator direction, “L” is the resonator length, and “Lt” is the length of a transition region provided between the position of the active layer with a band gap corresponding to a light wavelength of ?w+2 (nm) and the position of the active layer with a band gap corresponding to a light wavelength of ?a?2 (nm) in the resonator direction.

Abstract: A method for controlled growth of silicon carbide and structures produced by the method are disclosed. A crystal of silicon carbide (SiC) can be grown by placing a sacrificial substrate in a growth zone with a source material. The source material may include a low-solubility impurity. SiC is then grown on the sacrificial substrate to condition the source material. The sacrificial substrate is then replaced with the final substrate, and SiC is grown on the final substrate. A single crystal of silicon carbide is produced, wherein the crystal of silicon carbide has substantially few micropipe defects. Such a crystal may also include a substantially uniform concentration of the low-solubility impurity, and may be used to make wafers and/or SiC die.

Abstract: The present invention concerns new methods of fabricating a silicon material comprising phosphorus. The methods allow high levels of phosphorus to be combined with the silicon. In one aspect of the invention a sample of phosphorus is surrounded with a sample of silicon. At least some of the phosphorus is then vaporised and caused to interact with the silicon.

Abstract: A TFT array substrate includes a TFT having an ohmic contact film and a source electrode and a drain electrode formed on the ohmic contact film. It also includes a pixel electrode electrically connected with the drain electrode. The source electrode and the drain electrode are made of an Al alloy containing Ni as an additive.

Abstract: A structure to diminish high voltage instability in a high voltage device when under stress includes an amorphous silicon layer over a field oxide on the high voltage device.

Abstract: A method of forming a multi-doped junction is disclosed. The method includes providing a first substrate and a second substrate. The method also includes depositing a first ink on a first surface of each of the first substrate and the second substrate, the first ink comprising a first set of nanoparticles and a first set of solvents, the first set of nanoparticles comprising a first concentration of a first dopant. The method further includes depositing a second ink on a second surface of each of the first substrate and the second substrate, the second ink comprising a second set of nanoparticles and a second set of solvents, the second set of nanoparticles comprising a second concentration of a second dopant. The method also includes placing the first substrate and the second substrate in a back to back configuration; and heating the first substrate and the second substrate in a first drive-in ambient to a first temperature and for a first time period.

Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.

Abstract: A method of manufacturing a transistor and a structure thereof, wherein a very shallow region having a high dopant concentration of germanium is implanted into a channel region of a transistor at a low energy level, forming an amorphous germanium implantation region in a top surface of the workpiece, and forming a crystalline germanium implantation region beneath the amorphous germanium implantation region. The workpiece is annealed using a low-temperature anneal to convert the amorphous germanium region to a crystalline state while preventing a substantial amount of diffusion of germanium further into the workpiece, also removing damage to the workpiece caused by the implantation process. The resulting structure includes a crystalline germanium implantation region at the top surface of a channel, comprising a depth below the top surface of the workpiece of about 120 ? or less. The transistor has increased mobility and a reduced effective oxide thickness (EOT).

Abstract: A surface mount connector assembly for mounting to a printed wiring board (PWB) in a low-profile manner. The height of the surface mount connector assembly is diminished because the connector assembly extends from one side of the PWB to the other through an opening in the PWB. The surface mount connector assembly includes an outer housing portion having a plurality of openings therethrough for receiving a plurality of electrical contacts. The surface mount connector also includes an inner housing portion to be nested within the outer housing portion. Each of the electrical contacts are configured to be received within one of the openings in the inner housing portion such that a portion of each contact extends into the interior of the inner housing portion and another portion of each contact extends to the exterior of the inner housing portion.

Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a programming voltage is applied across the metal silicide layer, there is intense localized heating. The heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. The heating causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device.

Abstract: A method for enhancing the equilibrium solubility of boron and indium in silicon. The method involves first-principles quantum mechanical calculations to determine the temperature dependence of the equilibrium solubility of two important p-type dopants in silicon, namely boron and indium, under various strain conditions. The equilibrium thermodynamic solubility of size-mismatched impurities, such as boron and indium in silicon, can be raised significantly if the silicon substrate is strained appropriately. For example, for boron, a 1% compressive strain raises the equilibrium solubility by 100% at 1100° C.; and for indium, a 1% tensile strain at 1100° C., corresponds to an enhancement of the solubility by 200%.

Abstract: A method for enhancing the equilibrium solubility of boron and indium in silicon. The method involves first-principles quantum mechanical calculations to determine the temperature dependence of the equilibrium solubility of two important p-type dopants in silicon, namely boron and indium, under various strain conditions. The equilibrium thermodynamic solubility of size-mismatched impurities, such as boron and indium in silicon, can be raised significantly if the silicon substrate is strained appropriately. For example, for boron, a 1% compressive strain raises the equilibrium solubility by 100% at 1100° C.; and for indium, a 1% tensile strain at 1100° C., corresponds to an enhancement of the solubility by 200%.

Abstract: A method for enhancing the equilibrium solubility of boron and indium in silicon. The method involves first-principles quantum mechanical calculations to determine the temperature dependence of the equilibrium solubility of two important p-type dopants in silicon, namely boron and indium, under various strain conditions. The equilibrium thermodynamic solubility of size-mismatched impurities, such as boron and indium in silicon, can be raised significantly if the silicon substrate is strained appropriately. For example, for boron, a 1% compressive strain raises the equilibrium solubility by 100% at 1100° C.; and for indium, a 1% tensile strain at 1100° C., corresponds to an enhancement of the solubility by 200%.