Diffusing A Dopant Patents (Class 438/542)
  • Patent number: 10121664
    Abstract: A thin film containing a dopant is deposited on a surface of a semiconductor wafer. The semiconductor wafer on which the thin film containing the dopant is deposited is rapidly heated to a first peak temperature by irradiation with light from halogen lamps, so that the dopant is diffused from the thin film into the surface of the semiconductor wafer. The thermal diffusion using the rapid heating achieves the introduction of the necessary and sufficient dopant into the semiconductor wafer without producing defects. The surface of the semiconductor wafer is heated to a second peak temperature by further irradiating the semiconductor wafer with flashes of light from flash lamps, so that the dopant is activated. The flash irradiation which is extremely short in irradiation time achieves a high activation rate without excessive diffusion of the dopant.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: November 6, 2018
    Assignee: Screen Holdings Co., Ltd.
    Inventors: Kazuhiko Fuse, Hideaki Tanimura, Shinichi Kato
  • Patent number: 10014144
    Abstract: A curing method, a manufacture method of a display panel, a display panel and a mask, the curing method includes: providing curable material, providing a mask; and providing an incident light on a side of the mask to cure the curable material, wherein a shielding layer of the mask aligns with the curable material; the shielding layer including light conversion material, and the light conversion material is configured to convert the incident light to an exiting light which is capable of curing the curable material.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: July 3, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Jinyu Ren, Bo Zhou, Changjian Xu, Guojing Ma
  • Patent number: 9040400
    Abstract: In connection with various example embodiments, an organic electronic device is provided with an organic material that is susceptible to decreased mobility due to the trapping of electron charge carriers in response to exposure to air. The organic material is doped with an n-type dopant that, when combined with the organic material, effects air stability for the doped organic material (e.g., exhibits a mobility that facilitates stable operation in air, such as may be similar to operation in inert environments). Other embodiments are directed to organic electronic devices n-doped and exhibiting such air stability.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: May 26, 2015
    Inventors: Peng Wei, Zhenan Bao, Joon Hak Oh
  • Patent number: 9041157
    Abstract: An electrically actuated device comprises an active region disposed between a first electrode and a second electrode, a substantially nonrandom distribution of dopant initiators at an interface between the active region and the first electrode, and a substantially nonrandom distribution of dopants in a portion of the active region adjacent to the interface.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: May 26, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Wei Wu, Sagi Varghese Mathai, Shih-Yuan (SY) Wang, Jianhua Yang
  • Publication number: 20150132930
    Abstract: A semiconductor device manufacturing method includes: amorphizing the impurity diffusion layer formation region; doping the impurity diffusion layer formation region of the semiconductor substrate with impurities; and performing an annealing treatment including lamp annealing in which a heating lamp is used and microwave annealing in which microwaves are irradiated, on the semiconductor substrate doped with the impurities, for activating the impurities. In addition to activation of the impurity, re-crystallization and removing of crystal defects also take place in the annealing treatment.
    Type: Application
    Filed: April 19, 2013
    Publication date: May 14, 2015
    Inventors: Yoshimasa Watanabe, Kentaro Shiraga
  • Patent number: 9029226
    Abstract: The embodiments of mechanisms for doping lightly doped drain (LDD) regions by driving dopants from highly doped source and drain regions by annealing for finFET devices are provided. The mechanisms overcome the limitation by shadowing effects of ion implantation for advanced finFET devices. The highly doped source and drain regions are formed by epitaxial growing one or more doped silicon-containing materials from recesses formed in the fins. The dopants are then driven into the LDD regions by advanced annealing process, which can achieve targeted dopant levels and profiles in the LDD regions.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: May 12, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Tsan-Chun Wang, Su-Hao Liu
  • Patent number: 9018083
    Abstract: In an example of a method for controlling the formation of dopants in an electrically actuated device, a predetermined concentration of a dopant initiator is selected. The predetermined amount of the dopant is localized, via diffusion, at an interface between an electrode and an active region adjacent to the electrode. The dopant initiator reacts with a portion of the active region to form the dopants.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: April 28, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Duncan Stewart, Philip J. Kuekes, William Tong
  • Patent number: 8981357
    Abstract: A hydrophobic organic layer may be formed on a surface of a graphene doped with a dopant to improve stability of the doped graphene with respect to moisture and temperature. Thus, the transparent electrode having the doped graphene containing the hydrophobic organic layer may be usefully applied in solar cells or display devices.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: March 17, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seon-mi Yoon, Hyeon-jin Shin, Jae-young Choi, Won-mook Choi, Soo-min Kim, Young-hee Lee
  • Patent number: 8975170
    Abstract: Dopant ink compositions for forming doped regions in semiconductor substrates and methods for fabricating dopant ink compositions are provided. In an exemplary embodiment, a dopant ink composition comprises a dopant compound including at least one alkyl group bonded to a Group 13 element or a Group 15 element. Further, the dopant ink composition includes a silicon-containing compound.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: March 10, 2015
    Assignee: Honeywell International Inc.
    Inventors: Ligui Zhou, Richard A. Spear, Roger Yu-Kwan Leung, Wenya Fan, Helen X. Xu, Lea M. Metin, Anil Shriram Bhanap
  • Patent number: 8962460
    Abstract: Methods of selectively forming a metal-doped chalcogenide material comprise exposing a chalcogenide material to a transition metal solution, and incorporating transition metal of the transition solution into the chalcogenide material without substantially incorporating the transition metal into an adjacent material. The chalcogenide material is not silver selenide. Another method comprises forming a chalcogenide material adjacent to and in contact with an insulative material, exposing the chalcogenide material and the insulative material to a transition metal solution, and diffusing transition metal of the transition metal solution into the chalcogenide material while substantially no transition metal diffuses into the insulative material.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Prashant Raghu, Theodore M. Taylor, Scott E. Sills
  • Patent number: 8962444
    Abstract: Methods of manufacturing a semiconductor device are provided. The method includes forming a poly-silicon layer doped with first p-type dopants on a substrate, etching the poly-silicon layer and the substrate to form a poly-silicon pattern and a trench, forming device isolation pattern covering a lower sidewall of the poly-silicon pattern in the trench, thermally treating the poly-silicon pattern in a gas including second p-type dopants, forming a dielectric layer and a conductive layer on the thermally treated poly-silicon pattern and the device isolation pattern, etching the conductive layer, the dielectric layer, and the thermally treated poly-silicon pattern to form a control gate, a dielectric pattern, and a floating gate respectively.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Hwan Kim, Sunggil Kim, HongSuk Kim, Guk-Hyon Yon, Hunhyeong Lim
  • Patent number: 8962459
    Abstract: A method selectively diffuses dopants into a substrate wafer. The method comprises blanket depositing a doped liquid precursor including dopants on a surface of the substrate wafer to create a doped film on the surface of the substrate wafer, selectively forming a diffusion source in the doped film to selectively diffuse the dopants into the substrate wafer, and heating the doped film on the substrate wafer, wherein said heating the doped film diffuses the dopants from the doped film into the substrate wafer.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: February 24, 2015
    Assignee: Piquant Research LLC
    Inventor: Daniel Inns
  • Publication number: 20150040983
    Abstract: The present invention relates to a method for acidic surface etching of a silicon wafer, such as those used for solar cells, comprising contacting at least one surface of a silicon wafer as cut with an acidic etching agent, provided that the wafer is, prior to the acidic etching, not subjected to an alkaline etching step or process. Further, the present invention is directed to Si wafer, photovoltaic cells, PERC photovoltaic cells and solar modules produced according to the method of the present invention.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 12, 2015
    Applicant: SolarWorld Industries America, Inc.
    Inventor: Konstantin Holdermann
  • Patent number: 8946068
    Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Devendra Sadana, Lidija Sekaric
  • Publication number: 20140370665
    Abstract: A method for manufacturing a power semiconductor device is disclosed which can include: providing a wafer of a first conductivity type; and applying on a second main side of the wafer at least one of a dopant of the first conductivity type for forming a layer of the first conductivity type and a dopant of a second conductivity type for forming a layer of the second conductivity type. A Titanium layer with a metal having a melting point above 1300° C. is then deposited on the second main side. The Titanium deposition layer is annealed so that simultaneously an intermetal compound layer is formed at the interface between the Titanium deposition layer and the wafer and the dopant is diffused into the wafer. A first metal electrode layer is created on the second main side.
    Type: Application
    Filed: September 4, 2014
    Publication date: December 18, 2014
    Applicant: ABB Technology AG
    Inventors: Munaf RAHIMO, Chiara Corvasce, Jan Vobecky, Yoichi Otani
  • Patent number: 8912083
    Abstract: The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: December 16, 2014
    Assignee: NanoGram Corporation
    Inventors: Guojun Liu, Uma Srinivasan, Shivkumar Chiruvolu
  • Patent number: 8901010
    Abstract: Methods for protecting a texturized region and a lightly doped diffusion region of a solar cell to improve solar cell lifetime and efficiency are disclosed. In an embodiment, an example method includes providing a solar cell having a front side which faces the sun during normal operation and a back side opposite the front side, a silicon substrate and where the silicon substrate includes a texturized region and a lightly doped diffusion region. The method includes placing the solar cell on a receiving medium with the front side of the solar cell placed on an upper surface of the receiving medium, where the upper surface of the receiving medium prevents damage to the to the lightly doped diffusion region and damage to the texturized region on the front side of the solar cell during a contact printing process or transferring. In an embodiment, the lightly doped diffusion region has a doping concentration below 1×1019 cm?3 and the receiving medium includes a material having a moh's hardness in the range of 5-10.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 2, 2014
    Assignee: SunPower Corporation
    Inventors: Staffan Westerberg, Florito Dennis Tingchuy Vicente, Michael Cudzinovic, Princess Carmi Tomada, Jemellee Guiao
  • Patent number: 8900962
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a base region and an emitter region in a front surface of a semiconductor layer. The method can include forming a first impurity implantation region by implanting first impurity of a first conductivity type into a back surface of the semiconductor layer. The method can include selectively forming a second impurity implantation region by selectively implanting second impurity of a second conductivity type into the first impurity implantation region. In addition, the method can include irradiating the first impurity implantation region and the second impurity implantation region with laser light. A peak of impurity concentration profile in a depth direction of at least one of the first impurity implantation region and the second impurity implantation region before irradiation with the laser light is adjusted to a depth of 0.05 ?m or more and 0.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: December 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Yamashita, Etsuo Hamada, Hideki Nozaki, Hironobu Shibata
  • Patent number: 8895420
    Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 25, 2014
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Daniel-Camille Bensahel, Yves Morand
  • Patent number: 8895348
    Abstract: A solar cell, comprising: a doped silicon substrate, the silicon substrate comprising a front surface and a rear surface; a front phosphorous diffusion layer formed on the front surface; a front anti-reflective layer formed on the front phosphorous diffusion layer; a front metal electrode on the front surface in ohmic contact with the front phosphorous diffusion layer through the front anti-reflective layer; a rear passivation layer formed on the rear surface; a rear metal electrode in a pattern on the rear surface passing through the rear passivation layer; and a rear p+ diffusion area on the rear surface between the rear passivation layer and a boron-doped region of the silicon substrate, the rear p+ diffusion area surrounding the rear metal electrode.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: November 25, 2014
    Inventors: Karim Lofti Bendimerad, Daniel Aneurin Inns, Dmitry Poplavskyy
  • Publication number: 20140322905
    Abstract: The present disclosure disclosed a method of forming the buffer layer in the LTPS products. The method comprises the following steps: heating the substrate to make the alkali metal ions diffuse to the surface of the glass; washing the substrate by acid to remove the alkali metal ions on the surface of the glass; forming the buffer layer on the glass which has been heated and washed by acid, wherein the material of the buffer layer is SiOx. The method of the present disclosure based on the design of the single buffer layer, it can greatly promote the capacity and can economize the gas. Furthermore, it can avoid the cross contamination of the different layers so as to promote characteristic of the element.
    Type: Application
    Filed: April 24, 2014
    Publication date: October 30, 2014
    Applicant: EverDisplay Optronics (Shanghai) Limited
    Inventors: YuanHsin LEE, MinChing HSU
  • Publication number: 20140315376
    Abstract: A method for embedding a dopant into a glass substrate is provided. The method may include the steps of applying the dopant to a surface of the glass substrate, positioning the glass substrate adjacent to a catalyst such that the dopant is intermediate the catalyst and the glass substrate, heating the glass substrate to a first temperature, operating a directed thermal energy source so as to generate thermal energy incident upon the dopant, reducing the temperature of the glass substrate to a second temperature below the first temperature, and holding the glass substrate at the second temperature for at least a period of time.
    Type: Application
    Filed: March 13, 2014
    Publication date: October 23, 2014
    Applicant: LIGHTING SCIENCE GROUP CORPORATION
    Inventors: Fredric S. Maxik, David E. Bartine, Theodore Scone, Sepehr Sadeh
  • Patent number: 8858843
    Abstract: A high-fidelity dopant paste is disclosed. The high-fidelity dopant paste includes a solvent, a set of non-glass matrix particles dispersed into the solvent, and a dopant.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: October 14, 2014
    Assignee: Innovalight, Inc.
    Inventors: Elena Rogojina, Maxim Kelman, Giuseppe Scardera
  • Patent number: 8859352
    Abstract: Embodiments of the present invention are directed to an image sensor having pixel transistors and peripheral transistors disposed in a silicon substrate. For some embodiments, a protective coating is disposed on the peripheral transistors and doped silicon is epitaxially grown on the substrate to form lightly-doped drain (LDD) areas for the pixel transistors. The protective oxide may be used to prevent epitaxial growth of silicon on the peripheral transistors during formation of the LDD areas of the pixel transistors.
    Type: Grant
    Filed: July 26, 2012
    Date of Patent: October 14, 2014
    Assignee: OmniVision Technologies, Inc.
    Inventors: Duli Mao, Hsin-Chih Tai, Howard E. Rhodes, Vincent Venezia, Yin Qian
  • Patent number: 8853438
    Abstract: Formulations of solutions and processes are described to form a substrate including a dopant. In particular implementations, the dopant may include arsenic (As). In an embodiment, a dopant solution is provided that includes a solvent and a dopant. In a particular embodiment, the dopant solution may have a flashpoint that is at least approximately equal to a minimum temperature capable of causing atoms at a surface of the substrate to attach to an arsenic-containing compound of the dopant solution. In one embodiment, a number of silicon atoms at a surface of the substrate are covalently bonded to the arsenic-containing compound.
    Type: Grant
    Filed: November 5, 2012
    Date of Patent: October 7, 2014
    Assignee: Dynaloy, LLC
    Inventors: Spencer Erich Hochstetler, Kimberly Dona Pollard, Leslie Shane Moody, Peter Borden Mackenzie, Junjia Liu
  • Publication number: 20140295655
    Abstract: A semiconductor device and method for forming the same provide a through silicon via (TSV) surrounded by a dielectric liner. The TSV and dielectric liner are surrounded by a well region formed by thermal diffusion. The well region includes a dopant impurity type opposite the dopant impurity type of the substrate. The well region may be a double-diffused well with an inner portion formed of a first material and with a first concentration and an outer portion formed of a second material with a second concentration. The surrounding well region serves as an isolation well, reducing parasitic capacitance.
    Type: Application
    Filed: June 10, 2014
    Publication date: October 2, 2014
    Inventor: Chi-Yeh YU
  • Publication number: 20140291809
    Abstract: The semiconductor substrate includes a high-ohmic semiconductor material with a conduction band edge and a valence band edge, separated by a bandgap, wherein the semiconductor material includes acceptor or donor impurity atoms or crystal defects, whose energy levels are located at least 120 meV from the conduction band edge, as well as from the valence band edge in the bandgap; and wherein the concentration of the impurity atoms or crystal defects is larger than 1×1012 cm?3.
    Type: Application
    Filed: June 11, 2014
    Publication date: October 2, 2014
    Inventors: Hans-Joachim Schulze, Frank Pfirsch, Hans-Joerg Timme
  • Patent number: 8846508
    Abstract: Methods to implant ions into the sidewall of a three dimensional high aspect ratio feature, such as a trench or via, are disclosed. The methods utilize a phenomenon known as knock-in, which causes a first species of ions, already disposed in the fill material, to become implanted in the sidewall when these ions are struck by ions of a second species being implanted into the fill material. In some embodiments, these first species and second species have similar masses to facilitate knock-in. In some embodiments, the entire hole is not completely filled with fill material. Rather, some fill material is deposited, an ion implant is performed to cause knock-in to the sidewall adjacent to the deposited fill material, and the process is repeated until the hole is filled.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: September 30, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Jonathan Gerald England, Andrew M. Waite, Simon Ruffell
  • Patent number: 8846512
    Abstract: Methods of incorporating impurities into materials can be useful in non-volatile memory devices as well as other integrated circuit devices. Various embodiments provide for incorporating impurities into a material using a mask.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jaydeb Goswami
  • Publication number: 20140264754
    Abstract: Methods of forming doped elements of semiconductor device structures include forming trenches having undercut portions separating stem portions of a substrate. The stem portions extend between a base portion of the substrate and overlying broader portions of the substrate material. A carrier material including a dopant is formed at least on the sides of the stems in the undercut portions of the trenches. The dopant is diffused from the carrier material into the stems. As such, the narrow stem portions of the substrate become doped with a targeted dopant-delivery method. The doped stems may form or be incorporated within buried, doped, conductive elements of semiconductor device structures, such as digit lines of memory arrays. Also disclosed are related semiconductor device structures.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Shyam Surthi
  • Patent number: 8835290
    Abstract: Compositions and methods for doping silicon substrates by treating the substrate with a diluted dopant solution comprising tetraethylene glycol dimethyl ether (tetraglyme) and a dopant-containing material and subsequently diffusing the dopant into the surface by rapid thermal annealing. Diethyl-1-propylphosphonate and allylboronic acid pinacol ester are preferred dopant-containing materials, and are preferably included in the diluted dopant solution in an amount ranging from about 1% to about 20%, with a dopant amount of 4% or less being more preferred.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: September 16, 2014
    Assignee: Dynaloy, LLC
    Inventors: Kimberly Dona Pollard, Allison C. Tonk
  • Publication number: 20140256123
    Abstract: In an example of a method for controlling the formation of dopants in an electrically actuated device, a predetermined concentration of a dopant initiator is selected. The predetermined amount of the dopant is localized, via diffusion, at an interface between an electrode and an active region adjacent to the electrode. The dopant initiator reacts with a portion of the active region to form the dopants.
    Type: Application
    Filed: May 23, 2014
    Publication date: September 11, 2014
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Jianhua Yang, Duncan Stewart, Philip J. Kuekes, William Tong
  • Patent number: 8828817
    Abstract: A method of forming a semiconductor device includes performing a first pre-amorphous implantation process on a substrate, where the substrate has a gate stack. The method further includes forming a first stress film over the substrate. The method also includes performing a first annealing process on the substrate and the first stress film. The method further includes performing a second pre-amorphous implantation process on the annealed substrate, forming a second stress film over the substrate, and performing a second annealing process on the substrate and the second stress film.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yuan Lu, Li-Ping Huang, Han-Ting Tsai, Wei-Ching Wang, Ming-Shuan Li, Hsueh-Jen Yang, Kuan-Chung Chen
  • Patent number: 8828776
    Abstract: Multi-zone, solar cell diffusion furnaces having a plurality of radiant element (SiC) or/and high intensity IR lamp heated process zones, including baffle, ramp-up, firing, soaking and cooling zone(s). The transport of solar cell wafers, e.g., silicon, selenium, germanium or gallium-based solar cell wafers, through the furnace is implemented by use of an ultra low-mass, wafer transport system comprising laterally spaced shielded, synchronously driven, metal bands or chains carrying non-rotating alumina tubes suspended on wires between them. The wafers rest on raised circumferential standoffs spaced laterally along the alumina tubes, which reduces contamination. The high intensity IR flux rapidly photo-radiation conditions the wafers so that diffusion occurs >3× faster than conventional high-mass thermal furnaces. Longitudinal side wall heaters comprising coil heaters in Inconel sheaths inserted in carrier tubes are employed to insure even heating of wafer edges adjacent the side walls.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: September 9, 2014
    Assignee: TP Solar, Inc.
    Inventors: Richard W. Parks, Luis Alejandro Rey Garcia, Peter G. Ragay
  • Patent number: 8822318
    Abstract: A method and system are disclosed for doping a semiconductor substrate. In one embodiment, the method comprises forming a carbon free layer of phosphoric acid on a semiconductor substrate, and diffusing phosphorous from the layer of phosphoric acid in the substrate to form an activated phosphorous dopant therein. In an embodiment, the semiconductor substrate is immersed in a solution of a phosphorous compound to form a layer of the phosphorous compound on the substrate, and this layer of phosphorous is processed to form the layer of phosphoric acid. In an embodiment, this processing may include hydrolyzing the layer of the phosphorous compound to form the layer of phosphoric acid. In one embodiment, an oxide cap layer is formed on the phosphoric acid layer to form a capped substrate. The capped substrate may be annealed to diffuse the phosphorous in the substrate and to form the activated dopant.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: September 2, 2014
    Assignee: Inernational Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Damon Farmer, Lidija Sekaric
  • Patent number: 8815723
    Abstract: A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method also includes performing an ion implantation process to the back surface of the silicon substrate and performing a green laser annealing process to the implanted back surface of the silicon substrate. The green laser annealing process uses an annealing temperature greater than or equal to about 1100° C. for a duration of about 100 to about 400 nsec. After performing the green laser annealing process, a silicon polishing process is performed on the back surface of the silicon substrate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shou Shu Lu, Hsun-Ying Huang, I-Chang Lin, Chia-Chi Hsiao, Yung-Cheng Chang
  • Patent number: 8815722
    Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. At least one silicon-containing layer is formed in source/drain (S/D) regions adjacent to sidewalls of the gate structure. An N-type doped silicon-containing layer is formed over the at least one silicon-containing layer. The N-type doped silicon-containing layer has an N-type dopant concentration higher than that of the at least one silicon-containing layer. The N-type doped silicon-containing layer is annealed so as to drive N-type dopants of the N-type doped silicon-containing layer to the S/D regions.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: August 26, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ka-Hing Fung, Wei-Yuan Lu, Han-Ting Tsai
  • Patent number: 8816503
    Abstract: A semiconductor device with a buried electrode is manufactured by forming a cavity within a semiconductor substrate, forming an active device region in an epitaxial layer disposed on the semiconductor substrate and forming the buried electrode below the active device region in the cavity. The buried electrode is formed from an electrically conductive material different than the material of the semiconductor substrate.
    Type: Grant
    Filed: August 29, 2011
    Date of Patent: August 26, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Carsten Ahrens, Johannes Baumgartl, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze
  • Patent number: 8796093
    Abstract: A FinFET structure is fabricated using a process that facilitates the effective doping of fin structures. A doped layer is annealed to drive dopants into the fins. The doped layer is removed following annealing. Subsequent to removal of the doped layer, doped semiconductor material is grown epitaxially on the side walls of the fins, forming doped regions extending laterally from the fin side walls. Growth of the semiconductor material may be timed to form diamond-shaped, unmerged epitaxy.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek
  • Publication number: 20140199826
    Abstract: A manufacturing method for a semiconductor device includes introducing an impurity into a SiC substrate, forming a mixed material layer, which is made from a resin and a fibrous carbon material, on a surface of the SiC material into which the impurity is introduced, performing heat treatment of the SiC substrate in which the mixed material layer is formed on the surface of the SiC substrate, and removing the mixed material layer after the heat treatment.
    Type: Application
    Filed: January 9, 2014
    Publication date: July 17, 2014
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Norihiro Togawa
  • Patent number: 8765617
    Abstract: A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon nitride on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including a nitrogen atom.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Inc.
    Inventor: Takeyoshi Masuda
  • Patent number: 8753928
    Abstract: In a process of manufacturing a transistor including an oxide semiconductor layer, an amorphous oxide semiconductor layer which includes a region containing excess oxygen as compared to a stoichiometric composition ratio of an oxide semiconductor in a crystalline state is formed over a silicon oxide film, an aluminum oxide film is formed over the amorphous oxide semiconductor layer, and then heat treatment is performed so that at least part of the amorphous oxide semiconductor layer is crystallized and an oxide semiconductor layer which includes a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor layer is formed.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: June 17, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuhei Sato, Keiji Sato, Tetsunori Maruyama
  • Patent number: 8753945
    Abstract: In a method of forming MOS transistor, a gate structure is formed on a substrate and a first spacer layer is formed on the substrate conformal to the gate structure. A second spacer layer is formed on the first spacer layer. A second spacer is formed on the first spacer layer corresponding to a sidewall of the gate structure by partially removing the second spacer layer from the first spacer layer. Impurities are implanted in the substrate by an ion implantation process using the gate structure including the first spacer layer and the second spacer as an ion implantation mask to form source/drain extension regions at surface portions of the substrate around the gate structure.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: June 17, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keon-Yong Cheon, Dong-Won Kim, Sung-Man Lim, Sadaaki Masuoka, Yaoqi Dong
  • Patent number: 8753937
    Abstract: The present invention provides a manufacturing method of a power transistor device. First, a semiconductor substrate of a first conductivity type is provided, and at least one trench is formed in the semiconductor substrate. Next, the trench is filled with a dopant source layer, and a first thermal drive-in process is performed to form two doped diffusion regions of a second conductivity type in the semiconductor substrate, wherein the doping concentration of each doped diffusion region close to the trench is different from the one of each doped diffusion region far from the trench. Then, the dopant source layer is removed and a tilt-angle ion implantation process and a second thermal drive-in process are performed to adjust the doping concentration of each doped diffusion region close to the trench.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: June 17, 2014
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Chia-Hao Chang
  • Patent number: 8748301
    Abstract: Provided are: a diffusing agent composition for ink-jet; a method for production of electrode and solar battery using the diffusing agent composition; and a solar battery produced by the method for production. The diffusing agent composition for ink-jet includes (a) a silicon compound, (b) an impurity-diffusing component and (c) a solvent, in which: the solvent (c) contains (c1) a solvent having a boiling point of no higher than 100° C. and (c2) a solvent having a boiling point of 180 to 230° C.; and the solvent (c1) is contained at a ratio of 70 to 90% by mass and the solvent (c2) is contained at a ratio of 1 to 20% by mass both relative to the total mass of the composition.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: June 10, 2014
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Toshiro Morita, Katsuya Tanitsu
  • Patent number: 8748937
    Abstract: A semiconductor device includes a semiconductor layer of a first conductor type; a first semiconductor layer of a second conductor type, on the front of the semiconductor layer; a second semiconductor layer of the second conductor type, on the first semiconductor layer and having a higher impurity concentration than the first semiconductor layer; a third semiconductor layer of the second conductor type, on the second semiconductor layer and having a lower impurity concentration than the second semiconductor layer; a first semiconductor region of the first conductor type, in a surface layer of the third semiconductor layer; a second semiconductor region of the second conductor type, in a surface layer of the first semiconductor region; an input electrode contacting the second semiconductor region; a control electrode disposed above part of the first semiconductor region with an insulating film therebetween; and an output electrode disposed on the back of the semiconductor layer.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: June 10, 2014
    Assignees: Fuji Electric Co., Ltd., Yoshitaka Sugawara
    Inventors: Yoshitaka Sugawara, Nobuyuki Takahashi
  • Patent number: 8742473
    Abstract: Semiconductor devices are provided including a gate across an active region of a substrate; a source region and a drain region in the active region on either side of the gate and spaced apart from each other; a main channel impurity region in the active region between the source and drain regions and having a first channel impurity concentration; and a lightly doped channel impurity region in the active region adjacent to the drain region. The lightly doped channel impurity region has the same conductivity type as the main channel impurity region and a second channel impurity concentration, lower than the first channel impurity concentration. The lightly doped channel impurity region and the main channel impurity region contain a first element. The lightly doped channel impurity region also contains a second element, which is a different Group element from the first element.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: June 3, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Uk Han, Min-Chul Park, Young-Jin Choi, Nam-Ho Jeon
  • Patent number: 8722545
    Abstract: A method of forming a transistor is disclosed, in which gate-to-substrate leakage is addressed by forming and maintaining a conformal oxide layer overlying the transistor gate. Using the method disclosed for an n-type device, the conformal oxide layer can be formed as part of the source-drain doping process. Subsequent removal of residual phosphorous dopants from the surface of the oxide layer is accomplished without significant erosion of the oxide layer. The removal step uses a selective deglazing process that employs a hydrolytic reaction, and an acid-base neutralization reaction that includes an ammonium hydroxide component.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: May 13, 2014
    Assignee: STMicroelectronics Pte Ltd.
    Inventors: Hong-Gap Chua, Yee-Chung Chan, Mei-Yu Muk
  • Publication number: 20140124896
    Abstract: Formulations of solutions and processes are described to form a substrate including a dopant. In particular implementations, the dopant may include arsenic (As). In an embodiment, a dopant solution is provided that includes a solvent and a dopant. In a particular embodiment, the dopant solution may have a flashpoint that is at least approximately equal to a minimum temperature capable of causing atoms at a surface of the substrate to attach to an arsenic-containing compound of the dopant solution. In one embodiment, a number of silicon atoms at a surface of the substrate are covalently bonded to the arsenic-containing compound.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 8, 2014
    Applicant: DYNALOY, LLC
    Inventors: Spencer Erich Hochstetler, Kimberly Dona Pollard, Leslie Shane Moody, Peter Borden Mackenzie, Junjia Liu
  • Publication number: 20140120648
    Abstract: The composition for forming an n-type diffusion layer in accordance with the present invention contains a glass powder and a dispersion medium, in which the glass powder includes an donor element and a total amount of the life time killer element in the glass powder is 1000 ppm or less. An n-type diffusion layer and a photovoltaic cell having an n-type diffusion layer are prepared by applying the composition for forming an n-type diffusion layer, followed by a thermal diffusion treatment.
    Type: Application
    Filed: November 10, 2013
    Publication date: May 1, 2014
    Applicant: Hitachi Chemical Company, Ltd.
    Inventors: Yoichi MACHII, Masato YOSHIDA, Takeshi NOJIRI, Kaoru OKANIWA, Mitsunori IWAMURO, Shuichiro ADACHI, Tetsuya SATO, Keiko KIZAWA