Abstract: Methods and apparatus are described that allow the investigation of process variables used in RTP systems to be varied in a combinatorial manner across a plurality of site-isolated regions designated in the surface of a substrate. The methods and apparatus allow process variables such as power, dwell time, light source, cooling gas composition, cooling gas flow rate, reactive gas composition, reactive gas flow rate, and substrate support temperature and the like to be investigated.

Abstract: Systems and methods are provided for activating dopants in a semiconductor structure. For example, a semiconductor structure including a plurality of dopants is provided. One or more microwave-absorption materials are provided, the microwave-absorption materials being capable of increasing an electric field density associated with the semiconductor structure. Microwave radiation is applied to the microwave-absorption materials and the semiconductor structure to activate the plurality of dopants for fabricating semiconductor devices. The microwave-absorption materials are configured to increase the electric field density in response to the microwave radiation so as to increase the semiconductor structure's absorption of the microwave radiation to activate the dopants.

Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.

Abstract: A semiconductor component includes a semiconductor body having a first side and a second side opposite the first side. In the semiconductor body, a dopant region is formed by a dopant composed of an oxygen complex. The dopant region extends over a section L having a length of at least 10 ?m along a direction from the first side to the second side. The dopant region has an oxygen concentration in a range of 1×1017 cm?3 to 5×1017 cm?3 over the section L.

Abstract: First flash irradiation from flash lamps is performed on an upper surface of a semiconductor wafer supported on a temperature equalizing ring of a holder to cause the semiconductor wafer to jump up from the temperature equalizing ring into midair. While the semiconductor wafer is in midair above the temperature equalizing ring, second flash irradiation from the flash lamps is performed on the upper surface of the semiconductor wafer to increase the temperature of the upper surface of the semiconductor wafer to a treatment temperature. Cracking in the semiconductor wafer is prevented because the second flash irradiation is performed while the semiconductor wafer is in midair and subject to no restraints.

Abstract: A method selectively diffuses dopants into a substrate wafer. The method comprises blanket depositing a doped liquid precursor including dopants on a surface of the substrate wafer to create a doped film on the surface of the substrate wafer, selectively forming a diffusion source in the doped film to selectively diffuse the dopants into the substrate wafer, and heating the doped film on the substrate wafer, wherein said heating the doped film diffuses the dopants from the doped film into the substrate wafer.

Abstract: A method for producing a semiconductor device includes: an arranging process of arranging a plurality of silicon carbide wafers having opposed first and surfaces so that the first surface and the second surface of adjacent silicon carbide wafers face each other and are separated in parallel; and a heat treatment process of heating the arranged plurality of silicon carbide wafers so that the first surface of each silicon carbide wafer becomes higher in temperature than the second surface thereof, and, in the adjacent silicon carbide wafers, the second surface of one silicon carbide wafer becomes higher in temperature than the first surface of the other silicon carbide wafer that faces the second surface.

Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

Abstract: A heat treatment method is provided for a panel. The panel includes a plastic housing composition, in which semiconductor chips are embedded by their rear sides and edge sides, and the top sides of the semiconductor chips form a coplanar area with the plastic housing composition. The panel is fixed by its underside on a holder, and a temperature gradient (?T) is then generated between top side and the underside of the panel. The temperature gradient (?T) is then maintained for at least one delimited or selected time period. The panel is then cooled to room temperature (TR).

Abstract: The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process.

Abstract: A technique for fabricating an image sensor including a pixel circuitry region and a peripheral circuitry region includes fabricating front side components on a front side of the image sensor. A dopant layer is implanted on a backside of the image sensor. A anti-reflection layer is formed on the backside and covers a first portion of the dopant layer under the pixel circuitry region while exposing a second portion of the dopant layer under the peripheral circuitry region. The first portion of the dopant layer is laser annealed from the backside of the image sensor through the anti-reflection layer. The anti-reflection layer increases a temperature of the first portion of the dopant layer during the laser annealing.

Abstract: A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

Abstract: A manufacture method for a gallium-doped monocrystalline silicon solar cell is provided. The method includes classifying the sheets of gallium-doped monocrystalline silicon according to resistivity; texturing and washing the sheets of gallium-doped monocrystalline silicon; diffusing the classified, textured and washed sheets of gallium-doped monocrystalline silicon; etching and depositing the sheets of gallium-doped monocrystalline silicon; and metalizing the sheets of gallium-doped monocrystalline silicon. Advantageously, Light Induced Degradation (LID) is efficiently, economically and conveniently suppressed, the light induced efficiency degradation of monocrystalline silicon solar cell can be controlled within 1%, and meanwhile, the effect of the uneven resistivity distribution of gallium-doped monocrystalline on the cell process is reduced.

Abstract: A method of detecting a degradation of a semiconductor device including calculating a first number of first traps accumulated in a gate insulation layer of the semiconductor device over an operation time of the semiconductor device; calculating the second number of second traps accumulated at an interface between the gate insulation layer and a substrate over the operation time; and calculating the degradation of the semiconductor device relative to the operation time using the first number of the first traps and the second number of the second traps.

Abstract: A method of forming a semiconductor structure comprises providing a substrate and forming an insulator layer on the substrate. A first film is formed on the insulator layer. Thus, the first film can correspond to a device region of the semiconductor structure. A second film, comprising a second material that is different from the first material, is also formed on the insulator layer adjacent to the first film. The second material can comprise an isolation material (e.g., an oxide and/or nitride material) and can, for example comprise the same dielectric material as the insulator layer (e.g., silicon dioxide). The second film can correspond to an isolation region (e.g., a shallow trench isolation region) of the semiconductor structure. The second film is specifically formed with a first section having a first thickness and a second section having a second thickness that is different from the first thickness.

Abstract: A method of fabricating a diode is disclosed. One embodiment provides a semiconductor body having a front and a back, opposite the front in a vertical direction of the semiconductor body. The semiconductor body contains, successively in the vertical direction from the back to the front, a heavily n-doped zone, a weakly n-doped zone, a weakly p-doped zone and a heavily p-doped zone. In the vertical direction, the weakly p-doped zone has a thickness of at least 25% and at most 50% of the thickness of the semiconductor body.

Abstract: Embodiments of a process comprising forming a pixel on a front side of a substrate, thinning the substrate, depositing a doped silicon layer on a backside of the thinned substrate, and diffusing a dopant from the doped silicon layer into the substrate. Embodiments of an apparatus comprising a pixel formed on a front side of a thinned substrate, a doped silicon layer formed on a backside of the thinned substrate, and a region in the thinned substrate, and near the backside, where a dopant has diffused from the doped silicon layer into the thinned substrate. Other embodiments are disclosed and claimed.

Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.

Abstract: A masking paste used as a mask for controlling diffusion when diffusing a p-type dopant and an n-type dopant into a semiconductor substrate and forming a high-concentration p-doped region and a high concentration n-doped region is provided that contains at least a solvent, a thickening agent, and SiO2 precursor and/or a TiO2 precursor. Further, a manufacturing method of a solar cell is provided in which the masking paste is pattern-formed on the semiconductor substrate and then the p-type dopant and the n-type dopant are diffused.

Abstract: Methods of fabricating an integrated circuit, in particular a dynamic random access memory are described. After forming memory cells on a semiconductor substrate a mirror layer is provided, said mirror layer covering the memory cells. Then logic devices are formed adjoining to said memory cells covered by said mirror layer, said forming of said logic devices including activating the dopants in dopant regions by means of a radiation annealing, said radiation being reflected by said mirror layer. After at least partly removing the mirror layer; a wiring of the memory cells and of the logic devices is formed.

Abstract: Methods for fabricating semiconductor devices using thermal gradient-inducing films are provided. One method comprises providing a substrate having a first region and a second region and forming a film overlying the second region and exposing the first region. The substrate is subjected to a thermal process wherein the film induces a predetermined thermal gradient between the first region and the second region.

Abstract: The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process.

Abstract: A method of manufacturing a semiconductor element includes implanting ions of a dopant having a large diffusion coefficient into a semiconductor to provide a doped layer; and irradiating the doped layer with a plurality of pulsed laser beams supplied by a plurality of laser irradiation devices to activate the doped layer and provide an activated doped layer. The activated doped layer may be one of a single doped layer or a plurality of successive doped layers which each have respective conduction types that are one of identical or different. Device breakage and failure of the manufactured semiconductor element due to heat induced during laser irradiation are substantially prevented by this method.

Abstract: A method of manufacturing a semiconductor device includes the step of performing an ion implantation process for implanting an impurity ion into a semiconductor substrate, and performing annealing in a state where temperature of respective portions of an annealing chamber are set differently in order to activate the impurity ion.

Abstract: A method of non-thermal annealing of a silicon wafer comprising irradiating a doped silicon wafer with electromagnetic radiation in a wavelength or frequency range coinciding with lattice phonon frequencies of the doped semiconductor material. The wafer is annealed in an apparatus including a cavity and a radiation source of a wavelength ranging from 10–25 ?m and more particularly 15–18 ?m, or a frequency ranging from 12–30 THz and more particularly 16.5–20 THz.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. A barrier metal layer for blocking a metal material from being diffused into an insulating film is formed by means of an ALD method. At this time, the barrier metal layer is formed to have an amorphous structure and the barrier metal layer at the bottom of a contact hole or a via hole is selectively removed so that the barrier metal layer having good anti-diffusion properties even in a thin thickness is obtained. Therefore, it is possible to prevent resistance from increasing due to the barrier metal layer.

Abstract: A method for limiting slip lines in a semiconductor substrate including a support layer and a useful semiconductor layer that is transferred to the support layer. The method includes precipitating at least a portion of interstitial oxygen in the support layer by a series of heat treatments conducted after bonding of the useful semiconductor layer to the support layer. The heat treatments occur at a temperature and a time sufficient to reduce the generation of slip lines therein.

Abstract: Activation of impurities is achieved without involving creation of a crystal defect or deformation by using phonon absorption. A laser beam (42) having a wavelength in a range of 16 to 17 ?m is irradiated onto silicon, to cause phonon absorption. Before an energy supplied from the laser beam (42) diffuses around a portion which is irradiated with the laser beam (42), solid phase epitaxy in the portion finishes. Accordingly, crystallization occurs only in the portion which is irradiated with the laser beam (42), and does not occur in a portion which is not irradiated with the laser beam (42). Hence, heat is not excessively absorbed. Also, local phase change such as melting and solidification is not caused.

Abstract: Activation of impurities is achieved without involving creation of a crystal defect or deformation by using phonon absorption. A laser beam (42) having a wavelength in a range of 16 to 17 &mgr;m is irradiated onto silicon, to cause phonon absorption. Before an energy supplied from the laser beam (42) diffuses around a portion which is irradiated with the laser beam (42), solid phase epitaxy in the portion finishes. Accordingly, crystallization occurs only in the portion which is irradiated with the laser beam (42), and does not occur in a portion which is not irradiated with the laser beam (42). Hence, heat is not excessively absorbed. Also, local phase change such as melting and solidification is not caused.

Abstract: Within an epitaxial base bipolar transistor device and a method for fabricating the epitaxial base bipolar transistor device there is provided: (1) a monocrystalline semiconductor substrate which serves as a collector, in turn having formed thereupon; (2) an epitaxial base layer. Within the epitaxial base bipolar transistor device and method, there is further employed: (1) a pair of inward facing spacers formed over the epitaxial base layer and defining, at least in part, an aperture having at its bottom a portion of the epitaxial base layer; and (2) a pair of outward facing spacers formed over the epitaxial base layer and laminated to a pair of sides of the pair of inward facing spacers opposite the aperture; such that (3) an emitter layer may be formed into the aperture and contacting the epitaxial base layer. The foregoing two pair of spacer layers provide for efficient fabrication of the epitaxial base bipolar transistor device, with enhanced process latitude.

Abstract: A thin film photovoltaic devices is described, having a glass substrate 11 over which is formed a thin film silicon device having an n++ layer 12, a p layer 13 and a dielectric layer 14 (typically silicon oxide or silicon nitride). To create a connection through the p layer 13 to the underlying n++ layer 12, a column of semi-conductor material is heated, the column passing through the various doped layers and the material in the column being heated or melted to allow migration of dopant between layer of the device in the region of the column.

Abstract: A micromachined structure having electrically isolated components is formed by thermomigrating a dopant through a substrate to form a doped region within the substrate. The doped region separates two portions of the substrate. The dopant is selected such that the doped region electrically isolates the two portions of the substrate from each other via junction isolation.

Abstract: A method for forming an ultra-shallow junction using laser annealing wherein an amorphous carbon layer is used as an energy absorber layer comprises the steps of preparing a silicon substrate having isolation layers; forming a gate having a stacked structure of a gate insulating layer, a polysilicon layer and a metal layer on the silicon substrate; forming a sacrificial spacer on the sidewalls of the gate; forming source and drain regions on the silicon substrate regions at both sides of the gate including on the sacrificial spacer; removing the sacrificial spacer; doping impurities to form source/drain extension doping layers on the silicon substrate regions at both sides of the gate; depositing sequentially a reaction preventing layer and an amorphous carbon layer as a laser absorber layer on the resulting structure; forming source/drain extension doping layers on inner sides of the source and drain regions by performing laser annealing in an atmosphere of inert gas or under vacuum; and removing the amorpho

Abstract: The present invention aims to suppress certainly the single-crystallization in polycrystalline silicon that is to compose an emitter electrode, as well as to prevent the interface oxide film from remaining, when a heat treatment is conducted to diffuse dopants, and thereby it is also aimed to regulate the emitter dopant concentrations according to the design as well as to lower the emitter electrode resistance, which will provide a stable hFE; and further, the present invention aims to prevent anomalous bodies such as water-marks to be accidentally produced in a cleaning step following dry etching step to form an emitter electrode, and thereby to achieve an increase in yield as well as an enhancement of device reliability; in the process of the present invention, after an insulating film 4 and a first polycrystalline silicon film 5 are selectively dry etched to form a contact hole, a substrate is cleaned with such a cleansing agent as that composed of ammonia, hydrogen peroxide and water.

Abstract: In a method for fabricating a semiconductor device, a semiconductor wafer is thermally treated with a wafer treatment device, such as in a diffustion process. The semiconductor wafer is deliverd to the treatment device using a conveyor system. The conveyor system is operated in an arrangement consisting of at least two connected armatures and is operated with both heating and cooling elements. The heating and cooling element are implemented for optimal temperture control of the connected conveyor arms with respect to increase throughout while avoiding thermal shock.

Abstract: The invention relates to a method of iteratively, selectively tuning the impedance of integrated semiconductor devices, by modifying the dopant profile of a region of low dopant concentration by controlled diffusion of dopants from one or more adjacent regions of higher dopant concentration through the melting action of a focussed heating source, for example a laser. In particular the method is directed to increasing the dopant concentration of the region of lower dopant concentration, but may also be adapted to decrease the dopant concentration of the region.

Abstract: A BiCMOS integrated circuit is fabricated using a minimum number of wafer processing steps and yet offers the IC circuit designer five (5) different transistor types. These types include P-channel and N-channel MOS transistors and three different bipolar transistors whose emitters are all formed by a different process and all are characterized by different current gains and different breakdown voltages. A differential silicon dioxide/silicon nitride masking technique is used in the IC fabrication process wherein both P-type buried layers (PBL) and N-type buried layers (NBL) are formed in a silicon substrate using a single mask set and further wherein P-type wells and N-type wells are formed above these buried layers in an epitaxial layer, also using a single SiO2/Si3N4 differential mask set. Two of the bipolar transistor emitters are formed by out diffusion from first and second levels of polysilicon, whereas the emitter of the third bipolar transistor is formed by ion implantation doping.

Abstract: A method for forming a conductive film for a semiconductor device wherein a conductive film is formed on each wafer loaded in a boat of a vertical furnace of a low pressure chemical vapor deposition apparatus provided with a chamber, a reaction tube in a center portion of the chamber, a boat loaded in the reaction chamber and a heater surrounding the chamber. The method includes a decompression step for reducing pressure in the chamber to a vacuum condition, a deposition step for depositing a conductive film on each wafer by introducing reaction gas into the chamber in the vacuum condition, a purge step for removing from the chamber toxic gas generated in the deposition step, and a normal pressure step for increasing pressure and temperature in the chamber, wherein the pressure increases from the normal pressure step and the temperature increases from the purge step.

Abstract: There is disclosed a method for forming an ultra-shallow junction of a semiconductor device, comprising a four-stage RTA process following the ion implantation of dopants for source/drain junction, the RTA process being carried out with high temperature-elevating and -quenching rates between the stages, in such a way that relatively low temperatures are used for a short time in the first three stages in order to eliminate only the point defects, which greatly affect the diffusion of dopants, without diffusion of dopants while a relatively high temperature is taken in the last stage with the aim of allowing the dopants to diffuse a little to p.sup.+ and n.sup.+ shallow junctions, thereby obtaining an improvement in electrical activity and reducing junction current leakage and thus, improving the properties and reliability of the resulting semiconductor device.