Abstract: Approaches herein provide precise areal surface reaction with directional ion beam activation. Exemplary approaches include selectively forming a material within a trench of a semiconductor device using a plurality of successive deposition and activation cycles. Each of the plurality of deposition and activation cycles includes forming a precursor conformally along a set of surfaces of the trench, reacting the precursor with a capping compound to form a capping layer along the set of surfaces of the trench, and performing an ion implant to the semiconductor device to activate just a portion of the capping layer. In one approach, the ion implant activates just a portion of the capping layer along a bottom surface of the trench. In another approach, the ion implant activates just a portion of the capping layer along an upper section of a sidewall of the trench.

Abstract: A nanostructure, an optical device including the nanostructure, and methods of manufacturing the nanostructure and the optical device. A method of manufacturing a nanostructure may include forming a block copolymer template layer and a precursor pattern of metal coupled to the block copolymer template layer on a graphene layer, and forming a metal nanopattern on the graphene layer by removing the block copolymer template layer and reducing the precursor pattern.

Abstract: A method for fabricating a semiconductor device includes forming a metal layer on a substrate, forming a plurality of layers of a magnetic tunnel junction (MTJ) element on the metal layer, forming a carbon layer including a hole, wherein the hole penetrates through the carbon layer, forming a metal pattern in the hole of the carbon layer, removing the carbon layer; and patterning the plurality of layers of the MTJ element using the metal pattern as an etching mask.

Abstract: A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.

Abstract: A method of manufacturing doping patterns includes providing a substrate having a plurality of STIs defining and electrically isolating a plurality of active regions in the substrate, forming a patterned photoresist having a plurality of exposing regions for exposing the active regions and the STIs in between the active regions on the substrate, and performing an ion implantation to form a plurality of doping patterns in the active regions.

Abstract: Various embodiments of the present disclosure provide a method of simultaneously co-doping a wide band gap material with p-type and n-type impurities to create a p-n junction within the resulting wide band gap composite material. The method includes disposing a sample comprising a dopant including both p-type and n-type impurities between a pair of wide band gap material films and disposing the sample between a pair of opposing electrodes; and subjecting the sample to a preselected vacuum; and heating the sample to a preselected temperature; and applying a preselected voltage across the sample; and subjecting the sample to at least one laser beam having a preselected intensity and a preselected wavelength, such that the p-type and n-type impurities of the dopant substantially simultaneously diffuse into the wide band gap material films resulting in a wide band gap compound material comprising a p-n junction.

Abstract: A feedforward control is performed so that a line width of a mask constituted by an Si3N4 layer 102 formed by using a photoresist 105b as a mask is to be the same as a line width of a mask pattern constituted by an SiO2 layer 103 based on a measured line width of the photoresist 105b and the measured line width of the mask pattern constituted by the SiO2 layer 103. For example, a control of a trimming amount of the line width of the photoresist 105b is performed so that the line width of the photoresist 105b is to be the same as the line width of the mask pattern constituted by the SiO2 layer 103.

Abstract: An anisotropic conductive material prevents conduction resistance from varying among bumps or among linear terminals when connecting an IC chip or a flexible wire to a wiring board via the anisotropic conductive material. The anisotropic conductive material is formed by dispersing conductive particles in an insulating binder. The minimum melt viscosity [?0] thereof is in a range of from 1×102 to 1×106 mPa·sec, and satisfies the following equation (1): 1<[?1]/[?0]?3??(1) where in the equation (1), [?0] represents the minimum melt viscosity of the anisotropic conductive material, and [?1] represents a melt viscosity at a temperature T1 which is 30° C. lower than a temperature T0 at which the minimum melt viscosity is exhibited.

Abstract: A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias.

Abstract: A method for patterning a semiconductor device includes forming a lower electrode conductive layer over a substrate, forming a stack structure including a lower electrode conductive layer, a first ferromagnetic layer, an insulation layer and a second ferromagnetic layer over a substrate, forming an upper electrode conductive layer used as a first hard mask over the stack structure, forming a second hard mask layer over the upper electrode conductive layer, selectively etching the second hard mask layer to form a second hard mask pattern, etching the upper electrode conductive layer using the second hard mask pattern as an etch barrier to form an upper electrode, and etching the stack structure including the lower electrode conductive layer, the first ferromagnetic layer, the insulation layer and the second ferromagnetic layer by at least using the upper electrode as an etch barrier.

Abstract: A method of fabricating a semiconductor device is provided. The method can include forming a hard mask film including lower and upper hard mask films on a substrate in which an active region and an isolation region are defined and patterning the hard mask film to provide a hard mask pattern partially exposing the active region and the isolation region. An etchant can be applied to the active and isolation regions using the hard mask pattern as an etching mask to form a trench in the active region of the substrate while avoiding substantially etching the isolation region exposed to the etchant and a gate can be formed on the trench.

Abstract: In a method for forming a fine pattern of a semiconductor device, forming a spacer for double patterning of a cell region is performed separate from forming a mask pattern that defines a dummy pattern for a pad of a peripheral circuit region.

Abstract: The method for manufacturing the indium gallium aluminium nitride (InGaAlN) thin film on silicon substrate, which comprises the following steps: introducing magnesium metal for processing online region mask film, that is, or forming one magnesium mask film layer or metal transition layer; then forming one metal transition layer or magnesium mask layer, finally forming one layer of indium gallium aluminium nitride semiconductor layer; or firstly forming one layer of metal transition layer on silicon substrate and then forming the first indium gallium aluminium nitride semiconductor layer, magnesium mask layer and second indium gallium aluminium nitride semiconductor layer in this order. This invention can reduce the dislocation density of indium gallium aluminium nitride materials and improve crystal quality.

Abstract: A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias.

Abstract: An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a plurality areas defined laterally in the substrate through a bottom surface of the substrate; and a light source facing a top surface of the substrate, configured to irradiate a pulsed light at a pulse width of about 0.1 ms to about 100 ms on the entire top surface of the substrate.

Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Abstract: The invention generally encompasses a method for forming a pattern on a substrate. The method comprises applying a precursor comprising at least one metal to a substrate to form a precursor layer, exposing a predetermined portion of the precursor layer and developing the predetermined portion of the precursor layer. The developing step removes, or at least substantially removes, the predetermined portion from the substrate, thereby forming a pattern on the substrate that comprises a remaining portion of the precursor. In one embodiment, the precursor layer comprises Ti(PriO)2(EAA)2.

Abstract: A mask frame assembly includes a frame having an opening and a mask having at least two unit mask elements. Both ends of each unit mask element are fixed to the frame in a state of tension. The unit mask elements include a unit masking pattern, and overlap each other on a predetermined width to form a single mask pattern block. Each unit mask element has a recessed wall in an overlapping portion thereof so as to maintain the thickness of the mask constant at an overlap between the unit mask elements. Accordingly, the mask frame assembly reduces distortion in an evaporation pattern due to an increase in the size of a mask pattern, facilitates the adjustment of a total pitch of evaporation patterns, and prevents evaporation from occurring at undesired positions.

Abstract: A method for manufacturing an electronic device is provided. In one example of the method, the method prevents deformation of a resist mask caused by the irradiation of exposure light. The resist mask has a resist as an opaque element, and can afford mask patterns undergoing little change even with an increase in the number of wafers subjected to exposure processing. The resist mask maintains a high dimensional accuracy. A photomask pattern is formed using as an opaque element a resist comprising a base resin and Si incorporated therein or a resist with a metal such as Si incorporated thereby by a silylation process, to improve the resistance to active oxygen. The deformation of a resist opaque pattern in a photomask is prevented. The dimensional accuracy of patterns transferred onto a Si wafer is improved in repeated use of the photomask.

Abstract: A heat processing apparatus for heating a mask substrate is disclosed. A mask substrate on which a coating solution has been coated is placed on a heating plate that heats the substrate. A frame member is disposed on the heating plate so that the frame member faces a side surface of the mask substrate placed on the heating plate when the frame member is attached to the heating plate and that a clearance is formed between the frame member and the heating plate when the frame member is attached to the heating plate. The frame member suppresses heat radiated from the side surface of the substrate. As a result, the temperature uniformity of the surface of the substrate can be improved. In addition, since the clearance is formed between the frame member and the heating plate, particles do not accumulate in the region. Thus, adhesion of particles to the substrate can be suppressed.

Abstract: A method of fabricating an integrated circuit can include forming a barrier layer along lateral side walls and a bottom of a via aperture, forming a seed layer proximate and conformal to the barrier layer, and forming an implanted layer proximate and conformal to the barrier layer and the seed layer. The via aperture is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: A method is provided for forming a blocking layer in a multilayer semiconductor device for blocking diffusion of a chemical species including the steps of providing an insulating layer including a target surface for forming a metal nitride layer thereon said insulating layer forming a portion of a multilayer semiconductor device; treating the target surface with an RF generated plasma to cause a density increase over a thickness adjacent to and including a target surface sufficient to reduce a diffusion rate of chemical species therethrough; forming at least one metal nitride layer over the target surface; and, carrying out a photolithographic process wherein the surface of the at least one metal nitride layer is patterned for etching.

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract: A method used during the formation of a semiconductor device comprises the steps of forming a polycrystalline silicon layer over a semiconductor substrate assembly and forming a silicon nitride layer over the polycrystalline silicon layer. A silicon dioxide layer is formed over the silicon nitride layer and the silicon dioxide and silicon nitride layers are patterned using a patterned mask having a width, thereby forming sidewalls in the two layers. The nitride and oxide layers are subjected to an oxygen plasma which treats the sidewalls and leaves a portion of the silicon nitride layer between the sidewalls untreated. The silicon dioxide and the untreated portion of the silicon nitride layer are removed thereby resulting in pillars of treated silicon nitride. Finally, the polycrystalline silicon is etched using the pillars as a mask. The patterned polycrystalline silicon layer thereby comprises features having widths narrower than the width of the original mask.

Abstract: The present invention provides a method for forming self-aligned spacers on the horizontal surfaces while removing spacer material from the vertical surfaces. The preferred method uses a resist that can be made insoluble to developer by the use of an implant. By conformally depositing the resist over a substrate having both vertical and horizontal surfaces, implanting the resist, and developing the resist, the resist is removed from the vertical surfaces while remaining on the horizontal surfaces. Thus, a self-aligned spacer is formed on the horizontal surfaces while the spacer material is removed from the vertical surfaces. This horizontal-surface spacer can then be used in further fabrication. The preferred method can be used in many different processes where there is exists a need to differentially process the vertical and horizontal surfaces of a substrate.

Abstract: For contacting a non-linear switching element (10), for example for use in a display device (1), a metallic layer (14) is provided on a layer of non-linear resistive material by means of a low-energetic deposition technique. This layer may function as a contact but also as a protective layer when a contact metallization (15) is provided at a later stage.