Outwardly Patents (Class 438/554)
  • Patent number: 9312128
    Abstract: A structure includes a substrate having a surface and a first transistor disposed in a first region supported by the surface of the substrate. The first transistor has a channel formed in a first compound (Group III-V) semiconductor having a first energy bandgap. The structure further includes a second transistor disposed in a second region supported by the substrate. The second transistor has a channel formed in a second compound (Group III-V) semiconductor having a second energy bandgap that is larger than the first energy bandgap. In one embodiment the first compound semiconductor is a layer that overlies a first portion of the surface of the substrate and the substrate is the second compound semiconductor. In another embodiment the second compound semiconductor is provided as a second layer that overlies a second portion of the surface of the substrate.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: April 12, 2016
    Inventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 9275854
    Abstract: A structure includes a substrate having a surface and a first transistor disposed in a first region supported by the surface of the substrate. The first transistor has a channel formed in a first compound (Group III-V) semiconductor having a first energy bandgap. The structure further includes a second transistor disposed in a second region supported by the substrate. The second transistor has a channel formed in a second compound (Group III-V) semiconductor having a second energy bandgap that is larger than the first energy bandgap. In one embodiment the first compound semiconductor is a layer that overlies a first portion of the surface of the substrate and the substrate is the second compound semiconductor. In another embodiment the second compound semiconductor is provided as a second layer that overlies a second portion of the surface of the substrate. Methods to form the structure are also disclosed.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: March 1, 2016
    Inventors: Kangguo Cheng, Bruce B Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8895420
    Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: November 25, 2014
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics SA
    Inventors: Daniel-Camille Bensahel, Yves Morand
  • Patent number: 8859409
    Abstract: A semiconductor component includes a semiconductor body having a first side and a second side opposite the first side. In the semiconductor body, a dopant region is formed by a dopant composed of an oxygen complex. The dopant region extends over a section L having a length of at least 10 ?m along a direction from the first side to the second side. The dopant region has an oxygen concentration in a range of 1×1017 cm?3 to 5×1017 cm?3 over the section L.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 14, 2014
    Assignee: Infineon Technologies AG
    Inventors: Thomas Neidhart, Franz Josef Niedernostheide, Hans-Joachim Schulze, Werner Schustereder, Alexander Susiti
  • Patent number: 8623749
    Abstract: In one embodiment, a method includes forming a base region for a transistor using a base mask and forming a contact region to the base region. The contact region is formed in an area that is at least partially outside of the base mask. The method then forms an emitter region in a diffused base region. The base region diffuses outwardly to be formed under the contact region.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: January 7, 2014
    Assignee: Diodes Incorporated
    Inventor: David Neil Casey
  • Patent number: 8524559
    Abstract: The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: September 3, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Main-Gwo Chen, Chia-Hao Chang, Chia-Wei Chen
  • Patent number: 8283717
    Abstract: Device isolation/insulation films each have a first height within a first area and a second height higher than the first height within a second area. At least the device isolation/insulation films adjacent to a contact diffusion region exist in the second area, and the device isolation/insulation films adjacent to memory transistors exist in the first area. The device isolation/insulation films are implanted with an impurity of a first conductivity type, and device formation regions each have a diffusion region of the first conductivity type, the diffusion region being formed by diffusion of the impurity of the first conductivity type from the device isolation/insulation films.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: October 9, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junya Matsunami, Hiroyuki Kutsukake
  • Patent number: 8263484
    Abstract: This method for manufacturing a high resistivity silicon wafer includes pulling a single crystal such that the single crystal has a p-type dopant concentration at which a wafer surface resistivity becomes in a range of 0.1 to 10 k ?cm, an oxygen concentration Oi of 5.0×1017 to 20×1017 atoms/cm3 (ASTM F-121, 1979), and a nitrogen concentration of 1.0×1013 to 10×1013 atoms/cm3 (ASTM F-121, 1979) by using a Czochralski method, processing the single crystal into wafers by slicing the single crystal, and subjecting the wafer to an oxygen out-diffusion heat treatment process in a non-oxidizing atmosphere.
    Type: Grant
    Filed: March 1, 2010
    Date of Patent: September 11, 2012
    Assignee: Sumco Corporation
    Inventor: Kazunari Kurita
  • Patent number: 8028621
    Abstract: Methods of fabricating three-dimensional structures comprise: contacting a printing plate face with a suspension comprising particles to arrange the particles at predefined positions on the printing plate face, the predefined positions comprising a first position laterally adjacent to a second position; positioning the printing plate with the printing plate face turned toward a substrate and the first position aligned to a protrusion on the substrate; contacting the protrusion with a first layer of particles disposed at the first position of the printing plate to transfer the first layer of particles to a protrusion surface; moving the printing plate laterally to align the second position to the protrusion; and contacting the first layer of particles disposed on the protrusion surface with a second layer of particles disposed at the second position of the printing plate to transfer the second layer of particles to on top of the first layer of particles.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: October 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Tobias Kraus, Heiko Wolf
  • Patent number: 7838401
    Abstract: A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: November 23, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Ohta, Kenichi Okabe
  • Patent number: 7605064
    Abstract: A method of manufacture for semiconductor electronic products and a circuit structure. A semiconductor material has a surface region and dopant is provided to a portion of the surface region. The portion of the surface region provided with the dopant is irradiated with sufficient energy to induce diffusion of the dopant from the portion of the surface region to another region of the semiconductor material. A method for manufacturing an electronic product with a semiconductor material having a surface and two spaced-apart regions along the surface for receiving dopant includes forming a field effect transistor gate structure is along the surface and over a third region of the surface between the two spaced-apart regions. Dopant is provided to the spaced-apart regions which are heated to a temperature at least 50 degrees C. higher than the peak temperature which results in the third region when the spaced-apart regions are heated.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: October 20, 2009
    Assignee: Agere Systems Inc.
    Inventors: Isik C. Kizilyalli, Joseph Rudolph Radosevich, Pradip Kumar Roy
  • Patent number: 7528058
    Abstract: The invention relates to a method for the production of passivated defining surfaces (6a, 6b) between a first layer, such as a silicide (5), and an adjacent layer. Passivating elements, such as S, Se and Te are used in said layer structure during said method and the first layer is enriched on the adjacent layer during heat treatment on at least one defining surface. Schottky barriers can be reduced and output work of the transition can be adjusted. Components, e.g. Schottky barrier MOSFETs with small or negative Schottky barriers arc disclosed as source and/or drain contacts and spin transistors.
    Type: Grant
    Filed: June 19, 2004
    Date of Patent: May 5, 2009
    Assignee: Forschungzentrum Julich GmbH
    Inventors: Siegfried Mantl, Qing-Tai Zhao
  • Patent number: 7419872
    Abstract: A method for preparing a trench capacitor structure first forms at least one trench in a substrate, and forms a capacitor structure in the bottom portion of the trench, wherein the capacitor structure includes a buried bottom electrode positioned on a lower outer surface of the trench, a first dielectric layer covering an inner surface of the bottom electrode and a top electrode positioned on the surface of the dielectric layer. Subsequently, a collar insulation layer is formed on the surface of the first dielectric layer above the top electrode, and a first conductive block is then formed in the collar insulation layer. A second conductive block with dopants is formed on the first conductive block, and a thermal treating process is performed to diffuse the dopants from the second conductive block into an upper portion of the semiconductor substrate to form a buried conductive region.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: September 2, 2008
    Assignee: Promos Technologies, Inc.
    Inventors: Ching Lee, Chin Wen Lee, Chin Long Hung, Zheng Cheng Chen
  • Patent number: 6930007
    Abstract: The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite-cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.
    Type: Grant
    Filed: September 15, 2003
    Date of Patent: August 16, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Haowen Bu, Shashank Ekbote, Rajesh Khamankar, Shaoping Tang, Freidoon Mehrad
  • Patent number: 6887745
    Abstract: A polysilicon thin film transistor and a method of forming the same is provided. A poly-island layer is formed over a substrate. A gate insulation layer is formed over the poly-island layer. A gate is formed over the gate insulation layer. Using the gate as a mask, an ion implantation of the poly-island layer is carried out to form a source/drain region in the poly-island layer outside the channel region. An oxide layer and a silicon nitride layer, together serving as an inter-layer dielectric layer, are sequentially formed over the substrate. Thickness of the oxide layer is thicker than or the same as (thickness of the nitride layer multiplied by 9000 ?)1/2 and maximum thickness of the nitride layer is smaller than 1000 ?.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: May 3, 2005
    Assignee: Au Optronics Corporation
    Inventors: Kun-Hong Chen, Chinwei Hu
  • Patent number: 6849528
    Abstract: One aspect of the invention relates to a method of forming P-N junctions within a semiconductor substrate. The method involves providing a temporary impurity species, such as fluorine, within the semiconductor crystal matrix prior to solid source in-diffusion of the primary dopant, such as boron. The impurity atom is a faster diffusing species relative to silicon atoms. During in-diffusion, the temporary impurity species acts to reduce the depth to which the primary dopant diffuses and thereby facilitates the formation of very shallow junctions.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: February 1, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Srinivasan Chakravarthi, Periannan Chidambaram
  • Patent number: 6844245
    Abstract: A method of forming a semiconductor device, such as a self-passivating fuse, includes patterning an opening in a dielectric to form a fuse. A seed-layer of a copper-alloy is deposited in the opening and the opening is filled with pure copper. The copper is planarized and a passivation layer is deposited. This passivation layer can be thinned over a fuse portion of the copper. The fuse portion can then be laser fused to form a crater in an area surrounding a blown copper fuse. Exposed portions of the pure copper can then be self-passivated by annealing the device.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: January 18, 2005
    Assignee: Infineon Technologies AG
    Inventor: Hans-Joachim Barth
  • Patent number: 6809336
    Abstract: A semiconductor device is provided which avoids lowering of the sense speeds of plural sense amplifiers due to their drives. In the semiconductor device, a P-type well layer (6) containing a P-type impurity is selectively disposed in a main surface of an epitaxial layer (3). An N-type bottom layer (7) containing an N-type impurity is disposed so as to make contact with a bottom surface of the P-type well layer (6). A P-type well layer (2) is disposed in such a thickness as to make contact with the N-type bottom layer (7), so that the N-type bottom layer (7) and P-type well layer (2) form a PN junction. Further, in the main surface of the epitaxial layer (3), an N-type well layer (4) containing an N-type impurity and a P-type well layer (5) containing a P-type impurity are selectively disposed so as to sandwich therebetween the P-type well layer (6).
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: October 26, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Tatsuya Kunikiyo, Takeshi Hamamoto, Yoshinori Tanaka
  • Patent number: 6617209
    Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: September 9, 2003
    Assignee: Intel Corporation
    Inventors: Robert Chau, Reza Arghavani, Mark Doczy
  • Publication number: 20030036258
    Abstract: The invention includes a method of fabricating a circuit in a manner to place certain structures within a predefined distance of one another. Electrical connections are formed between certain structures of silicon, by annealing a conductive material to cause silicon out-diffusing to form local interconnects. The silicon out-diffusion can be facilitated without a masking step thereby simplifying as well as speeding up the fabrication process. The invention also includes a local interconnect thus formed.
    Type: Application
    Filed: September 17, 2002
    Publication date: February 20, 2003
    Applicant: Micron Technology, Inc.
    Inventors: Todd Abbott, Jigish D. Trivedi, Mike Violette, Chuck Dennison
  • Publication number: 20020132440
    Abstract: During the production of integrated semiconductor structures, it is often necessary to differently dope immediately adjacent regions. A method is provided for producing two adjacent regions of a predetermined area in an integrated semiconductor, whereby a first region of the two adjacent regions includes a doping with a lower target concentration than a second region. The predetermined area of a semiconductor blank is doped with a dopant until a concentration of the dopant is obtained that is at least as high as the target concentration of the second region. A protective layer is applied to the second region, and the dopant is out-diffused from the first region until a concentration of dopant is obtained that corresponds to the target concentration of the first region.
    Type: Application
    Filed: January 22, 2002
    Publication date: September 19, 2002
    Inventor: Josef Bock
  • Patent number: 6350645
    Abstract: A triple-poly process forms a static random access memory (SRAM) which has a compact four-transistor SRAM cell layout. The cell layout divides structures among the three layers of polysilicon to reduce the area required for each cell. Additionally, a contact between a pull-up resistor formed in an upper polysilicon layer forms a “strapping” via which cross-couples a gate region and a drain region underlying the strapping via. Pull-up resistors extend across boundaries of cell areas to increase the length and resistance of the pull-up resistors.
    Type: Grant
    Filed: July 22, 1997
    Date of Patent: February 26, 2002
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuen-Der Lien, Kyle W. Terrill
  • Publication number: 20020022367
    Abstract: A method for fabricating a semiconductor substrate includes forming a suicide layer at a predetermined portion of a semiconductor substrate, implanting two or more impurity ions before annealing, and forming an impurity region in the semiconductor substrate by annealing the silicide layer and by diffusing the impurity ions from the silicide layer into the semiconductor substrate. Accordingly, the present invention can improve reliability and performance of a semiconductor device by reducing dopant loss and leakage current of a PN junction in the substrate and by decreasing a sheet resistance of the silicide layer. The dose of the second implanter ions is about one hundred to one thousand times less than the dose of the first implanted ions.
    Type: Application
    Filed: November 5, 1999
    Publication date: February 21, 2002
  • Patent number: 6255190
    Abstract: A method for forming very deep pn-junctions without using epitaxy or extensively high temperature processing is provided. At least two parallel deep trenches are etched into a silicon substrate. Then the sidewalls of these trenches are predeposited by dopants. After filling the deep trenches with insulating material, a diffusion process is done. This diffusion process performs in such a way that the formerly predeposited dopant is distributed rather uniformly in between the parallel deep trenches, e.g. is counterdoping the whole region with respect to the monocrystalline silicon substrate. The said lateral trench doped region, which preferably is more deep than wide, serves either as drain or collector region of high voltage transistors or other high voltage devices. Also other devices like hall sensors, which gain advantages from the more deep than wide counterdoped regions, are possible.
    Type: Grant
    Filed: June 18, 1998
    Date of Patent: July 3, 2001
    Assignee: Austria Mikro Systeme International AG
    Inventor: Friedrich Kröner
  • Patent number: 6207540
    Abstract: A MOSFET device and a method of manufacturing the device. The device has a trench formed in a silicon substrate. The channel of the device is at the bottom of the trench. Diffusion layers are formed adjacent to opposite sides of the trench. Each diffusion layer is connected to the edge of the device channel by extending the diffusion layer along the side wall of the trench and under a portion of the trench.
    Type: Grant
    Filed: August 24, 1999
    Date of Patent: March 27, 2001
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, William H. Ma, Jack A. Mandelman
  • Patent number: 6204110
    Abstract: A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the s
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: March 20, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Martin Ceredig Roberts
  • Patent number: 5976940
    Abstract: In a semiconductor device comprising a first bipolar transistor and a second bipolar transistor having different voltages formed on a semiconductor substrate made by forming an epitaxial layer on a silicon substrate, in an upper part of the silicon substrate the first bipolar transistor has an N.sup.+ -type first embedded diffusion layer having an impurity concentration higher than that of the epitaxial layer and the second bipolar transistor has an N-type second embedded diffusion layer having a lower impurity concentration and a deeper diffusion layer depth than the first embedded diffusion layer, whereby a high speed bipolar transistor and a high voltage bipolar transistor are formed on the same substrate.
    Type: Grant
    Filed: December 10, 1996
    Date of Patent: November 2, 1999
    Assignee: Sony Corporation
    Inventors: Takayuki Gomi, Hiroaki Ammo
  • Patent number: 5970343
    Abstract: In the manufacture of an MOS gated semiconductor device, indentations are provided on a surface of a semiconductor wafer extending inwardly of respective spaced apart regions at the wafer surface having doping concentrations greater than that present in the remainder of the wafer. A layer of silicon having a doping concentration less than that of the substrate is conformally provided on the substrate surface whereby the indentations in the substrate surface are replicated on the surface of the silicon layer. Dopants in the substrate regions are then out-diffused into the silicon layer to provide highly doped buried regions within the layer. Then, using the silicon layer surface indentations as photomask alignment marks, gate electrode structures are formed on and within the silicon layer in preselected orientation relative to the buried regions. The buried regions provide low resistance paths for current through the resulting devices.
    Type: Grant
    Filed: August 12, 1998
    Date of Patent: October 19, 1999
    Assignee: Harris Corp.
    Inventor: Christopher Boguslaw Kocon
  • Patent number: 5789282
    Abstract: A method for fabricating a thin film transistor, comprising the steps of: forming a gate electrode; forming a doped polysilicon film for source/drain at the side wall of the gate electrode, to insulate the gate electrode; forming a gate insulating film; forming an amorphous polysilicon film over the resulting structure; and forming a source/drain region by diffusing the dopants of the doped polysilicon film into the amorphous silicon film, whereby it is possible to form the source/drain region and drain offset structure of a thin film transistor without formation of a source/drain mask and ion implantation and thus, thereby simplifying the overall procedure.
    Type: Grant
    Filed: October 28, 1996
    Date of Patent: August 4, 1998
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Sung Wook Yin, Tae Woo Kwon
  • Patent number: 5759887
    Abstract: A method of manufacturing a semiconductor integrated circuit (IC) includes the steps of forming a polycrystalline silicon layer containing impurities on a semiconductor substrate; forming an oxidation-resistant insulating layer on the polycrystalline silicon layer; simultaneously forming resist patterns for forming a capacitor element and a resistor element on the oxidation-resistant insulating layer; and patterning the oxidation-resistant insulating layer and the polycrystalline silicon layer in sequence using resist patterns.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: June 2, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takao Ito, Masayuki Ayabe