Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: A solar cell, comprising: a doped silicon substrate, the silicon substrate comprising a front surface and a rear surface; a front phosphorous diffusion layer formed on the front surface; a front anti-reflective layer formed on the front phosphorous diffusion layer; a front metal electrode on the front surface in ohmic contact with the front phosphorous diffusion layer through the front anti-reflective layer; a rear passivation layer formed on the rear surface; a rear metal electrode in a pattern on the rear surface passing through the rear passivation layer; and a rear p+ diffusion area on the rear surface between the rear passivation layer and a boron-doped region of the silicon substrate, the rear p+ diffusion area surrounding the rear metal electrode.

Abstract: The present invention provides a power transistor device including a substrate, an epitaxial layer, a dopant source layer, a doped drain region, a first insulating layer, a gate structure, a second insulating layer, a doped source region, and a metal layer. The substrate, the doped drain region, and the doped source region have a first conductive type, while the epitaxial layer has a second conductive type. The epitaxial layer is formed on the substrate and has at least one through hole through the epitaxial layer. The first insulating layer, the gate structure, and the second insulating layer are formed sequentially on the substrate in the through hole. The doped drain region and doped source region are formed in the epitaxial layer at one side of the through hole. The metal layer is formed on the epitaxial layer and extends into the through hole to contact the doped source region.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. Embodiments of the invention use a photosensitive self-assembled monolayer to pattern the surface of a substrate into hydrophilic and hydrophobic regions, and an aqueous (or alcohol) solution of a dopant compound is deposited on the substrate surface. The dopant compound only adheres on the hydrophilic regions. After deposition, the substrate is coated with a very thin layer of oxide to cap the compounds, and the substrate is annealed at high temperatures to diffuse the dopant atoms into the silicon and to activate the dopant. In one embodiment, the method comprises providing a semiconductor substrate including an oxide surface, patterning said surface into hydrophobic and hydrophilic regions, depositing a compound including a dopant on the substrate, wherein the dopant adheres to the hydrophilic region, and diffusing the dopant into the oxide surface of the substrate.

Abstract: A masking paste used as a mask for controlling diffusion when diffusing a p-type dopant and an n-type dopant into a semiconductor substrate and forming a high-concentration p-doped region and a high concentration n-doped region is provided that contains at least a solvent, a thickening agent, and SiO2 precursor and/or a TiO2 precursor. Further, a manufacturing method of a solar cell is provided in which the masking paste is pattern-formed on the semiconductor substrate and then the p-type dopant and the n-type dopant are diffused.

Abstract: A semiconductor device has a channel termination region for using a trench 30 filled with field oxide 32 and a channel stopper ring 18 which extends from the first major surface 8 through p-well 6 along the outer edge 36 of the trench 30, under the trench and extends passed the inner edge 34 of the trench. This asymmetric channel stopper ring provides an effective termination to the channel 10 which can extend as far as the trench 30.

Abstract: A method of preparing an array of conducting or semi-conducting nanowires may include forming a vicinal surface of stepped atomic terraces on a substrate, and depositing a fractional layer of dopant material to form nanostripes having a width less than the width of the atomic terraces. Diffusion of the atoms of the dopant nanostripes into the substrate may form the nanowires.

Abstract: A PLZT film (30) is formed as the material film of a capacitor dielectric film and a top electrode film (31) is formed on the PLZT film (30). The top electrode film (31) comprises two IrOx films having different composition. Subsequently, back face of a semiconductor substrate (11) is cleaned and an Ir adhesion film (32) is formed on the top electrode film (31). Substrate temperature is set at 400° C. or above at that time. Thereafter, a TiN film and a TEOS film are formed sequentially as a hard mask. In such a method, carbon remaining on the top electrode film (31) after cleaning the back face is discharged into the chamber while the temperature of the semiconductor substrate (11) is kept at 400° C. or above in order to form the Ir adhesion film (32). Consequently, adhesion is enhanced between a TiN film being formed subsequently and the Ir adhesion film (32) thus preventing the TiN film from being stripped.

Abstract: A method of manufacturing a semiconductor device includes: (A) a wafer process; and (B) a bias application process after the wafer process. The wafer process includes: (a) forming a n-type well in a p-type semiconductor substrate; (b) forming a p-type well in the n-type well; and (c) forming a transistor on the p-type well, the transistor having a n-type source/drain diffusion layer. In the bias application process, a forward bias is applied between the p-type well and the n-type well to move heavy metal ions.

Abstract: JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.

Abstract: Diffusion of As in SiGe of MOS transistors based on Si/SiGe is prevented by ion implanting boron. Embodiments include forming As source/drain extension implants in a strained Si/SiGe substrate, ion implanting boron at between the As source/drain extension implant junctions and subsequently annealing to activate the As source/drain extensions, thereby preventing distortion of the originally formed junction.

Abstract: A method includes forming a material over a substrate, oxidizing the material, and separately from the oxidizing, converting at least a portion of the oxidized material to a perovskite-type crystalline structure. The material can include an alloy material containing at least two metals. The method can further include retarding interdiffusion of the two metals. Such methods exhibit substantial advantage when at least two of the metals exhibit a substantial difference in chemical affinity for oxygen. A passivation layer against carbon and nitrogen reaction can be provided over the material. The passivation layer can be oxidized into a dielectric layer. The perovskite-type material can also be a dielectric layer.

Abstract: A method for forming a transistor having an elevated source/drain structure is described. A gate electrode is formed overlying a substrate and isolated from the substrate by a gate dielectric layer. Isolation regions are formed in and on the substrate wherein the isolation regions have a stepped profile wherein an upper portion of the isolation regions partly overlaps and is offset from a lower portion of the isolation regions in the direction away from the gate electrode. Ions are implanted into the substrate between the gate electrode and the isolation regions to form source/drain extensions. Dielectric spacers are formed on sidewalls of the gate electrode and the isolation regions.

Abstract: A semiconductor device comprises a base substrate, an insulating film formed on the substrate, an undoped first and lattice-relaxed semiconductor layer formed on the insulating film, a second semiconductor layer having a tensile strain and formed on the first semiconductor layer, and a MISFET formed on the second semiconductor layer. Since the MISFET is formed in a strained Si layer, electrons are prevented from scattering in a channel region, improving the electron mobility. Furthermore, since the MISFET is formed in a thin SOI layer having a thickness of 100 nm or less, it is possible to reduce a parasitic capacitance in addition to the improvement of the electron mobility. As a result, the MISFET excellent in drivability can be obtained.

Abstract: An average value of dimensions of resist patterns formed each time exposure processing is effected on semiconductor substrates of a predetermined number of lots, is compared with a target dimension. When a drift between each of the dimensions of the formed resist patterns and the target dimension is larger than a first value, exposure energy is corrected with a relatively large correction value &agr;1. When the drift between each of the dimensions of the formed resist patterns and the target dimension is smaller than the first value and larger than a second value, exposure energy is corrected with a relatively small correction value &agr;2. When the drift between each of the dimensions of the formed resist patterns and the target dimension is smaller than the second value, no exposure energy is corrected. Exposure processing is effected on a semiconductor substrate of the next lot by using the calculated exposure energy.

Abstract: Ions of arsenic are selectively implanted at a high concentration into a substrate through a first passivation film of silicon dioxide to obtain a shallow junction, thereby forming a source region with a low resistivity and a first drain region. Then, after the first passivation film is removed, a second passivation film of silicon dioxide is deposited over the substrate as well as over a stacked cell electrode by a CVD process performed at a relatively low temperature. Thereafter, the substrate is annealed in a nitrogen ambient at such a temperature as activating the dopant introduced. In this manner, the dopant in source region and first drain region is activated.

Abstract: A micromachined structure having electrically isolated components is formed by thermomigrating a dopant through a substrate to form a doped region within the substrate. The doped region separates two portions of the substrate. The dopant is selected such that the doped region electrically isolates the two portions of the substrate from each other via junction isolation.

Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers.

Abstract: Power semiconductor devices having recessed gate electrodes are formed by methods which include the steps of forming a semiconductor substrate having a drift region of first conductivity type therein extending to a face thereof and forming a trench in the substrate so that the trench has a bottom which extends opposite the drift region and a sidewall which extends from the drift region to the face. The sidewall may extend orthogonal to the face or at an angle greater than 90°. A preferred insulated gate electrode is formed by lining the face and trench with a gate electrode insulating layer and then forming a conductive layer on the gate electrode insulating layer. The conductive layer is preferably formed to extend opposite a portion of the face adjacent to the trench and into the trench. A step is then performed to pattern the conductive layer to define a T-shaped or Y-shaped gate electrode which fills the trench and also extends opposite the face at a location adjacent the trench.

Abstract: An opto-electronic device has a diffusion area of one conductive type formed in a semiconductor substrate of another conductive type, an ohmic contact layer making contact with the diffusion area, and an electrode making contact with the ohmic contact layer. The diffusion area is formed by solid-phase diffusion. The same mask is used to define the patterns of both the diffusion source layer and the ohmic contact layer, so that the ohmic contact layer is self-aligned with the diffusion area.

Abstract: A semiconductor processing method of forming a resistor from semiconductive material includes: a) providing a node to which electrical connection to a resistor is to be made; b) providing a first electrically insulative material outwardly of the node; c) providing an exposed vertical sidewall in the first electrically insulative material outwardly of the node; d) providing a second electrically insulative material outwardly of the first material and over the first material vertical sidewall, the first and second materials being selectively etchable relative to one another; e) anisotropically etching the second material selectively relative to the first material to form a substantially vertically extending sidewall spacer over the first material vertical sidewall and to outwardly expose the first material adjacent the sidewall spacer, the spacer having an inner surface and an outer surface; f) etching the first material selectively relative to the second material to outwardly expose at least a portion of the s

Abstract: A purchased silicon substrate 10 is subjected to D-HF treatment, SC-1 treatment, etc. to expose the surface of the silicon substrate 10. Then, the silicon substrate 10 having the surface exposed and containing grown-in defects 12 and micro oxygen precipitates 14 is subjected to oxygen out-diffusion annealing in an argon gas ambient. The annealing is performed, e.g., in an argon gas ambient, at a temperature of about 1000 to about 1300° C. for about 1 hour. Thus, the defects 12, 14 which are near the surface of the silicon substrate 10 are reduced, and the defects in the substrate surface can be decreased.

Abstract: Dual work function doping is provided by doping a selected number of gate structures having self-aligned insulating layer on top of the structures through at least one side wall of the gate structures with a first conductivity type to thereby provide an array of gate structures whereby some are doped with the first conductivity type and others of the gate structures are doped with a second and different conductivity type. Also provided is an array of gate structures whereby the individual gate structures contain self-aligned insulating layer on their top portion and wherein some of the gate structures are doped with a first conductivity type and other of the gate structures are doped with a second and different conductivity type.

Abstract: A method of removing vacancies in the crystal lattice of silicon wafers is provided. In particular, silicon wafers obtained from drawn rods have significantly higher defect densities in the central region as compared to the outer peripheries of the wafers. Before the diffusion of doping materials, the wafers are oxidized at a temperature that is generally lower than the diffusion temperature. As a result, the vacancies in the crystal lattice are filled with silicon which prevents the accumulation of heavy metals into the vacancies during the doping process. The performance and lifespan of the carrier in the central region of the wafers is thereby significantly increased.

Abstract: A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

Abstract: A semiconductor device and manufacturing method wherein a gate insulating film is formed on a semiconductor substrate. A gate is formed on the gate insulating film and a sidewall spacer is formed on respective sides of the gate. The substrate is etched at the respective sides of the gate to form respective recessed parts of the substrate. An insulating film is provided on the recessed parts of the substrate and the recessed parts are filled with a semiconductor layer. Impurity regions are formed contacting the semiconductor layer in the semiconductor substrate on the respective sides of the gate.