Combined With Formation Of Ohmic Contact To Semiconductor Region Patents (Class 438/571)
  • Patent number: 10269950
    Abstract: A compound semiconductor substrate includes a substrate, a channel layer provided over the substrate, a nitride semiconductor layer provided over the channel layer, and a barrier layer provided on the nitride semiconductor layer. The length of the c axis of the nitride semiconductor layer is 0.4990 nm or more.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: April 23, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Atsushi Yamada
  • Patent number: 9652703
    Abstract: A tamper resistant seal including a population of particles embedded in an adhesive, the population including at least one micromachine artifact of a predetermined physical shape.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: May 16, 2017
    Assignee: Sandia Corporation
    Inventor: Peter B. Merkle
  • Patent number: 9219000
    Abstract: Forming an alignment mark on a semiconductor structure using an optical lithography to form a metal alignment mark on a substrate of the structure, using the formed metal alignment mark to form a first feature of a semiconductor device being formed on the substrate using optical lithography, and using the formed metal alignment mark to form a second, different feature for the semiconductor using electron beam lithography. In one embodiment, the first feature is an ohmic contact, the second feature is a Schottky contact, the metal alignment mark is a refractory metal or a refractory metal compound having an atomic weight greater than 60 such as TaN and the semiconductor device is a GaN semiconductor device. A semiconductor structure having a metal alignment mark on a zero layer of the structure, the metal alignment mark is a TaN and the semiconductor is GaN.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: December 22, 2015
    Assignee: RAYTHEON COMPANY
    Inventors: Paul J. Duval, Kamal Tabatabaie, William J. Davis
  • Patent number: 9105681
    Abstract: According to an exemplary embodiment, a semiconductor die including at least one deep silicon via is provided. The deep silicon via comprises a deep silicon via opening that extends through at least one pre-metal dielectric layer of the semiconductor die, at least one epitaxial layer of the semiconductor die, and partially into a conductive substrate of the semiconductor die. The deep silicon via further comprises a conductive plug situated in the deep silicon via opening and forming an electrical contact with the conductive substrate. The deep silicon via may include a sidewall dielectric layer and a bottom conductive layer. A method for making a deep silicon via is also disclosed. The deep silicon via is used to, for example, provide a ground connection for power transistors in the semiconductor die.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: August 11, 2015
    Assignee: Newport Fab, LLC
    Inventors: Volker Blaschke, Todd Thibeault, Chris Cureton, Paul Hurwitz, Arjun Kar-Roy, David Howard, Marco Racanelli
  • Patent number: 9040402
    Abstract: A first metal layer (3) is formed on a back face of a silicon carbide substrate (1) to a degree such that the first metal layer (3) does not fully cover the back face of the silicon carbide substrate. Many holes (4) are formed on the back face of the silicon carbide substrate (1) by dry-etching the back face of the silicon carbide substrate (1) using the first metal layer (3) as a mask therefor. A second metal layer constituting an ohmic contact is formed on the first metal layer (3) and the back face of the silicon carbide substrate (1) including inner surfaces of the many holes (4).
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 26, 2015
    Assignees: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Masahide Goto, Kenji Fukuda, Noriyuki Iwamuro
  • Publication number: 20150123169
    Abstract: Gate metallization structures and methods for semiconductor devices are disclosed, wherein a refractory metal barrier is implemented to provide performance improvements. Transistor devices are disclosed having a compound semiconductor substrate and an electron-beam evaporated gate structure including a layer of tantalum nitride (TaNx), a layer of titanium (Ti) and a layer of gold (Au).
    Type: Application
    Filed: October 29, 2014
    Publication date: May 7, 2015
    Inventors: Shiban Kishan TIKU, Viswanathan RAMANATHAN
  • Patent number: 9018685
    Abstract: The invention relates to a structure comprising an n-type substrate (1) having a bottom surface (10) and a top surface (11), a drain (D) contacting the bottom surface (10) of the substrate (1), a first n-type semiconductor region (2) having a top surface (21) provided with a contact area (210), a source (S) contacting the contact area (210), and a second p-type semiconductor region (3) arranged inside the first semiconductor region (2) and defining first and second conduction channels (C1, C2) between the drain and the source, characterized in that said structure comprises first and second metal gratings (G1, G2), each of which has a portion (40, 71) contacting the first semiconductor region (2) so as to form a Schottky junction.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: April 28, 2015
    Assignees: Institut National des Sciences Appliquees de Lyon, Centre National de la Recherche Scientifique
    Inventors: Dominique Tournier, Pierre Brosselard, Florian Chevalier
  • Patent number: 9006746
    Abstract: A Schottky barrier diode and a method of manufacturing the diode are provided. The diode includes an n? type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate and a plurality of p+ regions disposed within the n? type epitaxial layer. An n+ type epitaxial layer is disposed on the n? type epitaxial layer, a Schottky electrode is disposed on the n+ type epitaxial layer, and an ohmic electrode is disposed on a second surface of the n+ type silicon carbide substrate. The n+ type epitaxial layer includes a plurality of pillar parts disposed on the n? type epitaxial layer and a plurality of openings disposed between the pillar parts and that expose the p+ regions. Each of the pillar parts includes substantially straight parts that contact the n? type epitaxial layer and substantially curved parts that extend from the substantially straight parts.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: April 14, 2015
    Assignee: Hyundai Motor Company
    Inventors: Youngkyun Jung, Dae Hwan Chun, Kyoung-Kook Hong, Jong Seok Lee, Junghee Park
  • Patent number: 8987124
    Abstract: A silicon carbide substrate having a main face is prepared. By applying thermal oxidation to the main face of the silicon carbide substrate at a first temperature, an oxide film is formed on the main face. After the oxide film is formed, heat treatment is applied to the silicon carbide substrate at a second temperature higher than the first temperature. An opening exposing a portion of the main face is formed at the oxide film. A Schottky electrode is formed on the main face exposed by the opening.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomihito Miyazaki, Toru Hiyoshi
  • Patent number: 8969921
    Abstract: A semiconductor device is provided with: a GaN layer; an anode electrode that forms a Schottky junction with a Ga face of the GaN layer; and an InGaN layer positioned between at least a part of the anode electrode and the GaN layer.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Limited
    Inventors: Naoya Okamoto, Yuichi Minoura
  • Publication number: 20150056794
    Abstract: A method for forming a field effect power semiconductor device includes providing a semiconductor body comprising a main horizontal surface and a conductive region arranged next to the main horizontal surface, forming an insulating layer on the main horizontal surface, and etching a narrow trench through the insulating layer so that a portion of the conductive region is exposed, the narrow trench comprising, in a given vertical cross-section, a maximum horizontal extension. The method further includes forming a vertical poly-diode structure comprising a horizontally extending pn-junction. Forming the vertical poly-diode structure includes depositing a polycrystalline semiconductor layer comprising a minimum vertical thickness of at least half of the maximum horizontal extension and maskless back-etching of the polycrystalline semiconductor layer to form a polycrystalline region in the narrow trench.
    Type: Application
    Filed: October 2, 2014
    Publication date: February 26, 2015
    Inventors: Franz Hirler, Anton Mauder, Frank Pfirsch, Hans-Joachim Schulze
  • Patent number: 8956963
    Abstract: A Schottky barrier diode and fabricating method thereof are disclosed. A semiconductor substrate may have a first surface and a second surface positioned oppositely to be provided. Several trenches are formed on the first surface. Each trench has a sidewall with a first depth and a first bottom surface. An insulating material is formed on the first surface of the semiconductor substrate and on the sidewall and the first bottom surface of each trench, wherein the insulating material has a first thickness on the sidewall. The insulating material on the sidewall is patterned to define a second bottom surface having a second depth smaller than the first depth, and the removed portion of the insulating material on the sidewall has a second thickness smaller than the first thickness. Afterward, a contact metal layer is at least formed on the first surface between adjacent trenches.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: February 17, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Tyng Yen, Kuan-Wei Chu, Lurng-Shehng Lee, Chwan-Ying Lee
  • Patent number: 8952481
    Abstract: The present disclosure relates to a semiconductor device having a Schottky contact that provides both super surge capability and low reverse-bias leakage current. In one preferred embodiment, the semiconductor device is a Schottky diode and even more preferably a Silicon Carbide (SiC) Schottky diode. However, the semiconductor device may more generally be any type of semiconductor device having a Schottky contact such as, for example, a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET).
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: February 10, 2015
    Assignee: Cree, Inc.
    Inventors: Qingchun Zhang, Jennifer Duc
  • Patent number: 8951430
    Abstract: Methods of metal assisted chemical etching III-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a III-V semiconductor. At least a portion of the III-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 10, 2015
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Matthew T. Dejarld, Jae Cheol Shin, Winston Chern
  • Publication number: 20150034961
    Abstract: An AlN single crystal Schottky barrier diode including: an AlN single crystal substrate having a defect density of 106 cm?2 or less and a thickness of 300 ?m or more; a first electrode formed on one surface of the AlN single crystal substrate; and a second electrode formed on one surface of the AlN single crystal substrate while being spaced apart from the first electrode, the AlN single crystal Schottky barrier diode being provided with: a rectifying property such that an on-off ratio at the time of applying 10 V and ?40 V is at least 103 even at a high temperature of 573 K; a high voltage resistance such that a voltage can be applied at least within a range of ?40 V to 10 V; and a low on-resistance characteristic such that a current begins to flow at no greater than 5 V.
    Type: Application
    Filed: January 30, 2013
    Publication date: February 5, 2015
    Inventors: Yoshihiro Irokawa, Kiyoshi Shimamura, Encarnacion Antonia Garcia Villora
  • Patent number: 8946070
    Abstract: Producing a transistor includes providing a substrate including in order a first electrically conductive material layer positioned on the substrate and a first electrically insulating material layer positioned on the first electrically conductive material layer. A gate including a reentrant profile is formed from an electrically conductive material layer stack provided on the first electrically insulating material layer in which a first portion of the gate is sized and positioned to extend beyond a second portion of the gate. The gate including the reentrant profile and at least a portion of the first electrically insulating material layer are conformally coated with a second electrically insulating material layer. The second electrically insulating material layer is conformally coated the with a semiconductor material layer. A source and drain electrodes are formed simultaneously by directionally depositing a second electrically conductive material layer on portions of the semiconductor material layer.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: February 3, 2015
    Assignee: Eastman Kodak Company
    Inventors: Lee W. Tutt, Shelby F. Nelson
  • Publication number: 20150024581
    Abstract: A method for manufacturing a semiconductor device in which an electrode structure is formed on a silicon carbide semiconductor substrate, includes forming a Schottky layer including a metal selected from the group titanium, tungsten, molybdenum, and chrome on a front surface of the silicon carbide semiconductor substrate; heating the Schottky layer to form a Schottky electrode which has a Schottky contact with the silicon carbide semiconductor substrate; and forming a surface electrode composed of aluminum or aluminum including silicon on a surface of the Schottky electrode, while heating at a temperature range effective for the surface electrode to closely cover any uneven portion of the Schottky electrode, and provide a surface electrode having a predetermined reflectance or less that is suitable for use in an automatic wire bonding apparatus for image recognition such as positioning.
    Type: Application
    Filed: October 9, 2014
    Publication date: January 22, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Fumikazu IMAI
  • Patent number: 8933532
    Abstract: A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: January 13, 2015
    Assignee: Avogy, Inc.
    Inventors: Andrew Edwards, Hui Nie, Isik C. Kizilyalli, Richard J. Brown, David P. Bour, Linda Romano, Thomas R. Prunty
  • Publication number: 20140370695
    Abstract: The present invention relates to a method for fabricating a semiconductor structure comprising a semiconductor layer and a metallic layer, to improve the breakdown voltage properties of the device and reduce leakage currents, the method comprises the steps of a) providing a semiconductor layer comprising defects and/or dislocations; b) removing material at one or more locations of the defects and/or dislocations thereby forming pits in the semiconductor layer, c) passivating the pits, and c) providing the metallic layer over the semiconductor layer. The invention also relates to a corresponding semiconductor structure.
    Type: Application
    Filed: December 15, 2011
    Publication date: December 18, 2014
    Applicant: SOITEC
    Inventor: Oleg Kononchuk
  • Patent number: 8895421
    Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: November 25, 2014
    Assignee: Transphorm Inc.
    Inventors: Primit Parikh, Yuvaraj Dora, Yifeng Wu, Umesh Mishra, Nicholas Fichtenbaum, Rakesh K. Lal
  • Patent number: 8866156
    Abstract: A silicon carbide semiconductor device includes a silicon carbide substrate and a contact electrode. The silicon carbide substrate includes an n type region and a p type region that makes contact with the n type region. The contact electrode makes contact with the n type region and the p type region. The contact electrode contains Ni atoms and Si atoms. The number of the Ni atoms is not less than 87% and not more than 92% of the total number of the Ni atoms and the Si atoms. Accordingly, there can be provided a silicon carbide semiconductor device, which can achieve ohmic contact with an n type impurity region and can achieve a low contact resistance for a p type impurity region, as well as a method for manufacturing such a silicon carbide semiconductor device.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: October 21, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shunsuke Yamada, Hideto Tamaso
  • Publication number: 20140306232
    Abstract: Disclosed is a semiconductor device comprising at least one active layer (14, 16) on a substrate (10) and a first contact (24, 26, 28) to the at least one active layer, the first contact comprising a metal in contact with the at least one active layer and a titanium tungsten nitride (TiW(N)) layer (30) on the metal. A method of manufacturing such a semiconductor device is also disclosed.
    Type: Application
    Filed: April 9, 2014
    Publication date: October 16, 2014
    Applicant: NXP B.V.
    Inventors: Johannes DONKERS, Hans Broekman, Stephan HEIL, Mark DE KEIJSER, Cecilia van der Schaar
  • Publication number: 20140239346
    Abstract: A semiconductor device includes a substrate comprising a heterostructure configured to support formation of a channel during operation, first and second dielectric layers supported by the substrate, the second dielectric layer being disposed between the first dielectric layer and the substrate, a gate supported by the substrate, disposed in a first opening in the first dielectric layer, and to which a bias voltage is applied during operation to control current flow through the channel, the second dielectric layer being disposed between the gate and the substrate, and an electrode supported by the substrate, disposed in a second opening in the first and second dielectric layers, and configured to establish a Schottky junction with the substrate.
    Type: Application
    Filed: February 26, 2013
    Publication date: August 28, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Bruce M. Green, James A. Teplik
  • Patent number: 8796808
    Abstract: A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: August 5, 2014
    Assignee: PFC Device Corp.
    Inventors: Kuo-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su
  • Patent number: 8772144
    Abstract: A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: July 8, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-se Ho
  • Patent number: 8765523
    Abstract: A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main surface, and forming a Schottky electrode in contact with the main surface that has been exposed by removing the oxide film.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda
  • Publication number: 20140145207
    Abstract: A Schottky barrier diode and fabricating method thereof are disclosed. A semiconductor substrate may have a first surface and a second surface positioned oppositely to be provided. Several trenches are formed on the first surface. Each trench has a sidewall with a first depth and a first bottom surface. An insulating material is formed on the first surface of the semiconductor substrate and on the sidewall and the first bottom surface of each trench, wherein the insulating material has a first thickness on the sidewall. The insulating material on the sidewall is patterned to define a second bottom surface having a second depth smaller than the first depth, and the removed portion of the insulating material on the sidewall has a second thickness smaller than the first thickness. Afterward, a contact metal layer is at least formed on the first surface between adjacent trenches.
    Type: Application
    Filed: July 2, 2013
    Publication date: May 29, 2014
    Inventors: Cheng-Tyng YEN, Kuan-Wei CHU, Lurng-Shehng LEE, Chwan-Ying LEE
  • Publication number: 20140138764
    Abstract: A semiconductor device includes a semiconductor substrate having a first type of conductivity. A first layer is formed on the substrate having the first type of conductivity and is more lightly doped than the substrate. At least one trench is formed in the first layer. A dielectric layer lines the bottom surface and the sidewalls of the trench. A conducting material fills the trench. A lightly doped region is formed in the first layer having the second conductivity type. The lightly doped region is disposed below the bottom surface of the trench. A metal layer is disposed over the first layer and the conducting material. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.
    Type: Application
    Filed: November 16, 2012
    Publication date: May 22, 2014
    Applicant: Vishay General Semiconductor LLC
    Inventors: Chih Wei Hsu, Max Chen
  • Patent number: 8728923
    Abstract: A manufacturing method of a semiconductor device having an ohmic electrode is disclosed. The manufacturing method includes: forming a metal thin film on a rear surface of a semiconductor substrate; forming an ohmic electrode by laser annealing by irradiating the metal thin film with laser beam; and dicing the semiconductor substrate into chips by cutting at a dicing region of the semiconductor substrate. In forming the ohmic electrode, laser irradiation of the metal thin film is performed on a chip-by-chip basis while the dicing region is not being irradiated with the laser beam.
    Type: Grant
    Filed: September 25, 2012
    Date of Patent: May 20, 2014
    Assignee: DENSO CORPORATION
    Inventors: Jun Kawai, Tetsuji Kondou, Kazuhiko Sugiura, Nobuyuki Kato
  • Patent number: 8685848
    Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 1, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Yoichiro Tarui
  • Patent number: 8685802
    Abstract: Methods of forming a graphene-based device are provided. According to an embodiment, a graphene-based device can be formed by subjecting a substrate having a dielectric formed thereon to a chemical vapor deposition (CVD) process using a cracked hydrocarbon or a physical vapor deposition (PVD) process using a graphite source; and performing an annealing process. The annealing process can be performed to temperatures of 1000 K or more. The cracked hydrocarbon of the CVD process can be cracked ethylene. In accordance with one embodiment, the application of the cracked ethylene to a MgO(111) surface followed by an annealing under ultra high vacuum conditions can result in a structure on the MgO(111) surface of an ordered graphene film with an oxidized carbon-containing interfacial layer therebetween. In another embodiment, the PVD process can be used to form single or multiple monolayers of graphene.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: April 1, 2014
    Assignee: Universityof North Texas
    Inventors: Jeffry A. Kelber, Sneha Sen Gaddam, Cameron L. Bjelkevig
  • Publication number: 20140087550
    Abstract: Embodiments include methods of making semiconductor devices with low leakage Schottky contacts. An embodiment includes providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.
    Type: Application
    Filed: November 21, 2013
    Publication date: March 27, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: BRUCE M. GREEN, HALDANE S. HENRY, CHUN-LI LIU, KAREN E. MOORE, MATTHIAS PASSLACK
  • Publication number: 20140077225
    Abstract: A schottky barrier diode may include a first n? type epitaxial layer disposed on a first surface of an n+ type silicon carbide substrate, a first p+ region disposed in the first n? type epitaxial layer, a second n type epitaxial layer disposed on the first n? type epitaxial layer and the first p+ region, a second p+ region disposed in the second n type epitaxial layer, a schottky electrode disposed on the second n type epitaxial layer and the second p+ region, and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein the first p+ region and the second p+ region may be in contact with each other.
    Type: Application
    Filed: December 10, 2012
    Publication date: March 20, 2014
    Applicant: Hyundai Motor Company
    Inventors: Jong Seok Lee, Kyoung-Kook Hong
  • Publication number: 20140073098
    Abstract: A method for forming a Schottky diode including forming first and second trenches in a semiconductor layer, forming a thin dielectric layer lining sidewalls of the first and second trenches; forming a trench conductor layer in the first and second trenches where the trench conductor layer fills a portion of each of the first and second trenches and being the only one trench conductor layer in the first and second trenches; forming a first dielectric layer in the first and second trenches to fill the remaining portions of the first and second trenches; and forming a Schottky metal layer on a top surface of the lightly doped semiconductor layer between the first trench and the second trench to form a Schottky junction. The Schottky diode is formed with the Schottky metal layer as the anode and the lightly doped semiconductor layer between the first and second trenches as the cathode.
    Type: Application
    Filed: November 18, 2013
    Publication date: March 13, 2014
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Daniel Calafut, Yi Su, Jongoh Kim, Hong Chang, Hamza Yilmaz, Daniel S. Ng
  • Publication number: 20140048846
    Abstract: Transistor devices can be fabricated with an integrated diode using a self-alignment. The device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One or more body regions are formed in a top portion of the substrate proximate each gate trench. One or more source regions are formed in a self-aligned fashion in a top portion of the body regions proximate each gate trench. One or more thick insulator portions are formed over the gate electrodes on a top surface of the substrate with spaces between adjacent thick insulator portions. A metal is formed on top of the substrate over the thick insulator portions. The metal forms a self-aligned contact to the substrate through the spaces between the thick insulator portions. An integrated diode is formed under the self-aligned contact.
    Type: Application
    Filed: October 23, 2013
    Publication date: February 20, 2014
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: Sik Lui, Anup Bhalla
  • Publication number: 20140038397
    Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.
    Type: Application
    Filed: October 3, 2013
    Publication date: February 6, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yoshinori MATSUNO, Yoichiro Tarui
  • Patent number: 8643062
    Abstract: A III-N device is described with a III-N layer, an electrode thereon, a passivation layer adjacent the III-N layer and electrode, a thick insulating layer adjacent the passivation layer and electrode, a high thermal conductivity carrier capable of transferring substantial heat away from the III-N device, and a bonding layer between the thick insulating layer and the carrier. The bonding layer attaches the thick insulating layer to the carrier. The thick insulating layer can have a precisely controlled thickness and be thermally conductive.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: February 4, 2014
    Assignee: Transphorm Inc.
    Inventors: Primit Parikh, Yuvaraj Dora, Yifeng Wu, Umesh Mishra, Nicholas Fichtenbaum, Rakesh K. Lal
  • Patent number: 8637339
    Abstract: An improved diode energy converter for chemical kinetic electron energy transfer is formed using nanostructures and includes identifiable regions associated with chemical reactions isolated chemically from other regions in the converter, a region associated with an area that forms energy barriers of the desired height, a region associated with tailoring the boundary between semiconductor material and metal materials so that the junction does not tear apart, and a region associated with removing heat from the semiconductor.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 28, 2014
    Assignee: Neokismet L.L.C.
    Inventors: Anthony C. Zuppero, Jawahar M. Gidwani
  • Patent number: 8637872
    Abstract: A high-performance semiconductor device capable of suppressing a leak current with little electric field concentration, reducing an invalid region in a PN junction region, securing a sufficient area for a Schottky junction region, and achieving efficient and easy manufacturing, in which, in one surface of a semiconductor substrate (1) having a first conduction type made of SiC, a PN junction region (7a) and a Schottky junction region (7b) are provided, in the PN junction region (7a), a convex portion (2a) which has a trapezoidal shape in sectional view and includes a second conduction type layer (2) provided on the semiconductor substrate (1) and a contact layer (3) which is in ohmic contact with the second conduction type layer (2) of the convex portion (2a) are provided, and Schottky electrode (4) covers the side surface of the convex portion (2a) and the contact layer (3), and is provided continuously over the PN junction region (7a) and the Schottky junction region (7b).
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: January 28, 2014
    Assignee: Showa Denko K.K.
    Inventor: Akihiko Sugai
  • Publication number: 20140001363
    Abstract: A Schottky barrier diode includes a first semiconductor layer, a LOCOS layer arranged in contact with the first semiconductor layer, a Schottky junction region provided on a contact surface between the first semiconductor layer and a first electrode, a second semiconductor layer connected to the first semiconductor layer and having a higher carrier concentration than that of the first semiconductor layer, and a second electrode forming an ohmic contact with the second semiconductor layer. In this case, the Schottky junction region and the LOCOS layer are in contact.
    Type: Application
    Filed: June 24, 2013
    Publication date: January 2, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Yasushi Koyama
  • Publication number: 20140001594
    Abstract: A Schottky diode includes a device structure having a central portion and a plurality of fingers. Distal portions of the fingers overlie leakage current control (LCC) regions. An LCC region is relatively narrow and deep, terminating in proximity to a buried layer of like polarity. Under reverse bias, depletion regions forming in an active region lying between the buried layer and the LCC regions occupy the entire extent of the active region and thereby provide a carrier depleted wall. An analogous depletion region occurs in the active region residing between any pair of adjacent fingers. If the fingers include latitudinal oriented fingers and longitudinal oriented fingers, depletion region blockades in three different orthogonal orientations may occur. The formation of the LCC regions may include the use of a high dose, low energy phosphorous implant using an LCC implant mask and the isolation structures as an additional hard mask.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Weize Chen, Xin Lin, Patrice M. Parris
  • Publication number: 20130334647
    Abstract: A semiconductor device has a gate electrode including a leg part and a canopy part. A barrier layer is formed on a bottom face of the leg part of the gate electrode. In addition, on the lower surface of the barrier layer, a Schottky metal layer with an electrode width wider than the electrode width of the barrier layer is formed to have a Schottky junction with a semiconductor layer.
    Type: Application
    Filed: February 21, 2013
    Publication date: December 19, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Fumio SASAKI
  • Patent number: 8592293
    Abstract: A method for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey B. Johnson, Xuefeng Liu, Bradley A. Orner, Robert M. Rassel
  • Patent number: 8586461
    Abstract: Systems and methods which provide a multimode tuner architecture implementing direct frequency conversion are shown. Embodiments provide a highly integrated configuration wherein low noise amplifier, tuner, analog and digital channel filter, and analog demodulator functionality are provided in a single integrated circuit. A LNA of embodiments implements a multi-path configuration with seamless switching to provide desired gain control while meeting noise and linearity design parameters. Embodiments of the invention implement in-phase and quadrature (IQ) equalization and a multimode channelization filter architecture to facilitate the use of direct frequency conversion. Embodiments implement spur avoidance techniques for improving tuner system operation and output using a clock signal generation architecture in which a system clock, sampling clock frequencies, local oscillator (LO) reference clock frequencies, and/or the like are dynamically movable.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: November 19, 2013
    Assignee: CSR Technology Inc.
    Inventor: Jan-Michael Stevenson
  • Publication number: 20130299840
    Abstract: The present invention discloses a Schottky barrier diode (SBD) and a manufacturing method thereof. The SBD includes: a semiconductor layer, which has multiple openings forming an opening array; and an anode, which has multiple conductive protrusions protruding into the multiple openings and forming a conductive array; wherein a Schottky contact is formed between the semiconductor layer and the anode.
    Type: Application
    Filed: May 8, 2012
    Publication date: November 14, 2013
    Inventors: Chieh-Hsiung Kuan, Ting-Wei Liao, Chien-Wei Chiu, Tsung-Yi Huang
  • Publication number: 20130299846
    Abstract: Disclosed is a semiconductor device comprising a substrate (10); at least one semiconducting layer (12) comprising a nitride of a group 13 element on said substrate; and an ohmic contact (20) on the at least one semiconducting layer, said ohmic contact comprising a silicon-comprising portion (22) on the at least one semiconducting layer and a metal portion (24) adjacent to and extending over said silicon-comprising portion, the metal portion comprising titanium and a further metal. A method of manufacturing such a semiconductor device is also disclosed.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 14, 2013
    Applicant: NXP B.V
    Inventors: Johannes Theodorus Marinus Donkers, Stephan Heil, Romain Delhougne, Hans Broekman
  • Patent number: 8575627
    Abstract: A semiconductor light emitting element of the present invention includes a support substrate, a semiconductor film including a light emitting layer, a surface electrode provided on the surface on a light-extraction-surface side of the semiconductor film, and a light reflecting layer. The surface electrode includes first electrode pieces that form ohmic contact with the semiconductor film and a second electrode piece electrically connected to the first electrode pieces. The light reflecting layer includes a reflecting electrode, and the reflecting electrode includes third electrode pieces that form ohmic contact with the semiconductor film and a fourth electrode piece electrically connected to the third electrode pieces and placed opposite to the second electrode piece. Both the second electrode piece and the fourth electrode piece form Schottky contact with the semiconductor film so as to form barriers to prevent forward current in the semiconductor film.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: November 5, 2013
    Assignee: Stanley Electric Co., Ltd.
    Inventor: Takuya Kazama
  • Publication number: 20130256688
    Abstract: According to an embodiment, a nitride semiconductor Schottky diode includes a first layer including a first nitride semiconductor and a second layer provided on the first layer and including a second nitride semiconductor having a wider band gap than the first nitride semiconductor. The diode also includes an ohmic electrode provided on the second layer and a Schottky electrode provided on the second layer. The second layer includes a region containing an acceptor in the vicinity of the Schottky electrode between the Schottky electrode and the ohmic electrode.
    Type: Application
    Filed: March 7, 2013
    Publication date: October 3, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Mayumi MORIZUKA
  • Publication number: 20130221376
    Abstract: A semiconductor device provided with a silicon carbide semiconductor substrate, and an ohmic metal layer joined to one surface of the silicon carbide semiconductor substrate in an ohmic contact and composed of a metal material whose silicide formation free energy and carbide formation free energy respectively take negative values. The ohmic metal layer is composed of, for example, a metal material such as molybdenum, titanium, chromium, manganese, zirconium, tantalum, or tungsten.
    Type: Application
    Filed: April 12, 2013
    Publication date: August 29, 2013
    Applicant: ROHM CO., LTD.
    Inventor: ROHM CO., LTD.
  • Patent number: 8513674
    Abstract: A method of manufacturing of a semiconductor device (101) includes: a fine pattern forming step of forming p-type impurity regions (3, 4) and surface ohmic contact electrodes (5) using a stepper, after forming an N-type epitaxial layer (2) on a SiC single-crystal substrate (1); a protective film planarizing step of forming a protective film so as to cover the surface ohmic contact electrodes (5) and performing planarization of the protective film; a substrate thinning step of thinning the SiC single-crystal substrate (1); a backside ohmic contact electrode forming step of forming a backside ohmic contact electrode (7) on the SiC single-crystal substrate (1); a surface Schottky contact electrode forming step of forming a Schottky metal portion (8) connected to the p-type impurity regions (3, 4) and the surface ohmic contact electrodes (5); and a step of forming a surface pad electrode (9) that covers the Schottky metal portion (8).
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: August 20, 2013
    Assignee: Showa Denko K.K.
    Inventors: Akihiko Sugai, Yasuyuki Sakaguchi