Combined With Formation Of Ohmic Contact To Semiconductor Region Patents (Class 438/571)
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Patent number: 6649497Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon carbide substrate and with at least one metal contact for the device on the first surface of the substrate. The opposite, second surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished second surface of the silicon carbide substrate to define a predetermined location for a via that is opposite the device metal contact on the first surface; etching the desired via through the desired masked location until the etch reaches the metal contact on the first surface; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.Type: GrantFiled: November 8, 2001Date of Patent: November 18, 2003Assignee: Cree, Inc.Inventor: Zoltan Ring
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Publication number: 20030203604Abstract: A method of fabricating a layered structure including a substrate, a first semiconductor layer with a first thermal expansion coefficient &agr;A, and a second semiconductor layer with a second thermal expansion coefficient &agr;B deposited on the first semiconductor layer, wherein &agr;A is greater than &agr;B or smaller than &agr;B, includes: forming the first semiconductor layer, the second semiconductor layer, and a third semiconductor layer with a third thermal expansion coefficient &agr;C in this order on the substrate at a first temperature using a film deposition technique such as MOCVD, thereby forming a structural body including the substrate and the first to third semiconductor layers, wherein &agr;C is greater than &agr;B if &agr;A is greater than &agr;B or &agr;C is smaller than &agr;B if &agr;A is smaller than &agr;B; cooling the structural body to a second temperature, which is lower than the first temperature; and removing the third semiconductor layer from the structural body to expose the secType: ApplicationFiled: April 1, 2003Publication date: October 30, 2003Inventor: Takehiko Makita
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Patent number: 6610999Abstract: A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.Type: GrantFiled: May 8, 2001Date of Patent: August 26, 2003Assignee: California Institute of TechnologyInventors: Zvonimir Z. Bandic, Eric C. Piquette, Thomas C. McGill
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Patent number: 6607955Abstract: A method of forming self-aligned contacts in a semiconductor device wherein a silicon nitride layer and a polysilicon layer are formed on a gate electrode layer. The polysilicon layer, the silicon nitride layer, and the gate electrode layer are etched to form gate electrode configurations. Sidewall spacers are formed on both sidewalls of the gate electrode configurations. An oxide layer is then deposited on the resulting structure. Selected portions of the oxide layer are etched to form self-aligned contacts that expose the semiconductor substrate. Because the polysilicon has an excellent etch selectivity with respect to the oxide layer, the gate electrode layer can be sufficiently protected during the etching of the oxide layer resulting in a good shoulder margin at the exposed upper edges of the silicon nitride gate mask layer.Type: GrantFiled: April 4, 2001Date of Patent: August 19, 2003Assignee: Samsung Electronics Co., Ltd.Inventor: Kyu-Hyun Lee
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Patent number: 6605519Abstract: A method for forming an etching mask structure on a substrate includes etching the substrate, laterally expanding the etching mask structure, and depositing a self-aligned metal layer that is aligned to the originally masked area. The etching can be isotropic or anisotropic. The self-aligned metal layer can be distanced from the original etching masked area based on the extent of the intentionally laterally expanded etching mask layer. Following metal deposition, the initial mask structure can be removed, thus lifting off the metal atop it. The etching mask structure can be a resist and can be formed using conventional photolithography materials and techniques and can have nearly vertical sidewalls. The lateral extension can include a silylation technique of the etching mask layer following etching. The above method can be utilized to form bipolar, hetero-bipolar, or field effect transistors.Type: GrantFiled: May 2, 2001Date of Patent: August 12, 2003Assignee: Unaxis USA, Inc.Inventor: David G. Lishan
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Publication number: 20030129813Abstract: In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.Type: ApplicationFiled: May 30, 2002Publication date: July 10, 2003Applicant: Rutgers, The State University Of New JerseyInventors: Yicheng Lu, Haifeng Sheng, Sriram Muthukumar, Nuri William Emanetoglu, Jian Zhong
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Patent number: 6544674Abstract: An electrical contact for a silicon carbide component comprises a material that is in thermodynamic equilibrium with silicon carbide. The electrical contact is typically formed of Ti3SiC2 that is deposited on the silicon carbide component.Type: GrantFiled: August 27, 2001Date of Patent: April 8, 2003Assignee: Boston MicroSystems, Inc.Inventors: Harry L. Tuller, Marlene A. Spears, Richard Micak
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Patent number: 6541319Abstract: The present invention provides a self-aligned gate transistor. The present invention implants P-type impurity ions only below a channel region below a gate and below a source and drain electrode on semiconductor substrate having an ion implantation channel layer without implanting the P-type impurity ions into a narrow region between the source-gate and the gate-drain, deposits a gate metal and etches the gate pattern. In this case, the length (Lg) of the gate is defined to be narrower than the length (Lch-g) into which P-type impurity ions are implanted below the channel layer, thus improving a pinch-off characteristic. A method of manufacturing a field effect transistor having a self aligned gate according to the present invention comprises the steps of implanting P-type impurity ions only below a channel region below a gate and below a source and drain electrode; and depositing a refractory gate metal having a good high temperature stability to form a gate pattern using a dry etch method.Type: GrantFiled: December 26, 2001Date of Patent: April 1, 2003Assignee: Electronics & Telecommunications Research InstituteInventors: Jae Kyoung Mun, Hea Cheon Kim, Jong Won Lim
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Publication number: 20030036252Abstract: A Schottky barrier diode has a Schottky electrode formed on an operation region of a GaAs substrate and an ohmic electrode surrounding the Schottky electrode. The ohmic electrode is disposed directly on an impurity-implanted region formed on the substrate. A nitride film insulates the ohmic electrode from a wiring layer connected to the Schottky electrode crossing over the ohmic electrode. The planar configuration of this device does not include the conventional polyimide layer, and thus has a better high frequency characteristics than conventional devices.Type: ApplicationFiled: July 26, 2002Publication date: February 20, 2003Applicant: Sanyo Electric Company, Ltd.Inventors: Tetsuro Asano, Katsuaki Onoda, Yoshibumi Nakajima, Shigeyuki Murai, Hisaaki Tominaga, Koichi Hirata, Mikito Sakakibara, Hidetoshi Ishihara
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Publication number: 20030032270Abstract: The invention is directed to a fabrication method for a device for regulating the flow of electric current with high dielectric constant gate insulating layer and a source and/or drain forming a Schottky contact or Schottky-like region with a substrate. In one aspect, the gate insulating layer has a dielectric constant greater than the dielectric constant of silicon. In another aspect, the current regulating device may be a MOSFET device, optionally a planar P-type or N-type MOSFET, having any orientation. In another aspect, the source and/or drain may consist partially or fully of a silicide.Type: ApplicationFiled: August 10, 2001Publication date: February 13, 2003Inventors: John Snyder, John Larson
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Patent number: 6486524Abstract: A FRED device having an ultralow Irr employs a contact layer which contacts spaced P diffusions in an N type silicon substrate and also contacts the silicon surface spanning between the P diffusions. The contact layer is formed of a contact having a lower barrier height than the conventional aluminum, and is palladium silicide with a top contact layer of aluminum.Type: GrantFiled: February 22, 2000Date of Patent: November 26, 2002Assignee: International Rectifier CorporationInventor: Iftikhar Ahmed
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Patent number: 6483164Abstract: A Schottky electrode is formed of an alloy, which is composed of two or more kinds of metal materials in combinations that provide different Schottky barrier heights with respect to a semiconductor and that form no intermetallic compound.Type: GrantFiled: July 7, 2000Date of Patent: November 19, 2002Assignee: Fuji Electric Co., Ltd.Inventors: Hiroshi Kanemaru, Shinji Ogino
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Patent number: 6479843Abstract: A method of fabricating apparatus, and the apparatus, for providing low voltage temperature compensation in a single power supply HFET including a stack of epitaxially grown compound semiconductor layers with an HFET formed in the stack. A Schottky diode is formed in the stack adjacent the HFET during the formation of the HFET. The HFET and the Schottky diode are formed simultaneously, with a portion of one of the layers of metal forming the gate of the HFET being positioned in contact with a layer of the stack having a low bandgap (e.g. less than 0.8 eV) to provide a turn-on voltage for the Schottky diode of less than 1.8 Volts. The Schottky diode is connected to the gate contact of the HFET by a gate circuit to compensate for changes in current loading in the gate circuit with changes in temperature.Type: GrantFiled: April 27, 2000Date of Patent: November 12, 2002Assignee: Motorola, Inc.Inventors: Jenn-Hwa Huang, Elizabeth C. Glass, Olin Hartin, Wendy L. Valentine, Julio Costa
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Patent number: 6475889Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon carbide substrate and with at least one metal contact for the device on the first surface of the substrate. The opposite, second surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished second surface of the silicon carbide substrate to define a predetermined location for a via that is opposite the device metal contact on the first surface; etching the desired via through the desired masked location until the etch reaches the metal contact on the first surface; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.Type: GrantFiled: April 11, 2000Date of Patent: November 5, 2002Assignee: Cree, Inc.Inventor: Zoltan Ring
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Patent number: 6465804Abstract: A heterojunction bipolar transistor (HBT) having an emitter structure capable of reducing the current crowding effect and preventing thermal instabilities is disclosed, wherein a negative differential resistance. (NDR) element is added to the layer structure of the conventional emitter. In accordance with the invention, the NDR element can be implemented, for example, by a Resonant Tunnel Diode (RTD) or an Esaki Diode structure. The NDR element is designed to limit the tunneling current to the maximal emitter current density required for safe transistor operation, thereby also reducing the current crowding effect.Type: GrantFiled: July 10, 2000Date of Patent: October 15, 2002Assignee: Technion Research & Development Foundation Ltd.Inventors: Nachum Shamir, Dan Ritter
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Patent number: 6458675Abstract: A semiconductor device includes: a semiconductor substrate; an active layer; and a plasma-processed layer provided between the semiconductor substrate and the active layer. The plasma-processed layer has a deep level. First and second electrodes are electrically connected by ohmic contact with first and second portions of the active layer, respectively. The first and second portions are spaced apart at a predetermined interval from each other. A third electrode is formed on a third respective portion of the active layer and is located between the first and second portions of the active layer.Type: GrantFiled: December 14, 1999Date of Patent: October 1, 2002Assignee: Murata Manufacturing Co., Ltd.Inventor: Takashi Marukawa
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Patent number: 6455403Abstract: A method for fabricating a Schottky diode using a shallow trench contact to reduce leakage current in the fabrication of an integrated circuit device is described. The method provides a simple and effective method for decreasing the possibility of forming a bad Schottky diode.Type: GrantFiled: January 4, 1999Date of Patent: September 24, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jei-Fung Hwang, Ruey-Hsing Liou, Chih-Kang Chiu
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Patent number: 6444553Abstract: Method and apparatus are provided for a semiconductor device including a junction and contact having a diffusion barrier to control silicidation of a silicon substrate. A dopant is applied in excess of an amount required to form a junction and the dopant chemically reacts with a metal to form a compound which serves as a barrier layer to prevent silidication in the substrate.Type: GrantFiled: September 15, 1997Date of Patent: September 3, 2002Assignee: University of HoustonInventors: Wanda Zagozdson-Wosik, Jia Li
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Publication number: 20020102825Abstract: A method of selectively forming contact regions on a substrate having a plurality of exposed regions includes selectively forming a contact region on each of the exposed regions of the substrate. During formation, each contact region has a first growth rate in a first direction and a second growth rate in a second direction. While each contact region is being selectively formed on the respective exposed region, the contact region is heated to increase the first growth rate of the contact region in the first direction relative to the second growth rate of the contact region in the second direction. The first growth rate may be a vertical growth rate and the second growth rate may be a lateral growth rate. The contact may be heated by applying electromagnetic radiation to an upper surface of the substrate and not applying the radiation to the vertical portions of the contact region to thereby increase the vertical growth rate relative to the lateral growth rate.Type: ApplicationFiled: January 26, 2001Publication date: August 1, 2002Inventors: Michael Nuttall, Garry Anthony Mercaldi
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Patent number: 6410947Abstract: A semiconductor device operable with a single positive power source, enabling an increase in efficiency, and improved in high-frequency characteristics by lowering the resistivity of a gate contact, including a carrier run layer formed on a substrate for running of carriers; a carrier supply layer formed on the carrier run layer, having a larger bandgap than the carrier run layer, and containing a first conductivity type impurity; a barrier layer formed on the carrier supply layer and having a smaller bandgap than the carrier supply layer; a source electrode and a drain electrode formed on the barrier layer at a predetermined distance from each other; a gate electrode formed on the barrier layer between the source electrode and the drain electrode away from the source electrode and the drain electrode; and a first low resistivity region formed at least below the gate electrode in the barrier layer and containing a second conductivity type impurity opposite in conductivity to the first conductivity type, and aType: GrantFiled: May 12, 2000Date of Patent: June 25, 2002Assignee: Sony CorporationInventor: Shinichi Wada
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Patent number: 6406964Abstract: The present invention is directed to a method of forming a transistor. In one embodiment, the method comprises providing a substrate, the substrate being doped with a first type of dopant material, forming a transistor above the substrate in an active area of the substrate as defined by an isolation structure, and performing at least one ion implant process to implant dopant atoms in the substrate adjacent the gate electrode of the transistor. The method further comprises performing at least two angled ion implant processes on the transistor with a dopant material that is of an opposite type to the first type of dopant material and performing at least one anneal process.Type: GrantFiled: November 1, 2000Date of Patent: June 18, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Derick J. Wristers, Jon D. Cheek, John G. Pellerin
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Publication number: 20020058401Abstract: A metal line of a semiconductor device and method of fabricating the same are provided in which the metal line deterioration due to electromigration is minimized to improve its reliability.Type: ApplicationFiled: January 14, 2002Publication date: May 16, 2002Applicant: LG Semicon Co., Ltd.Inventor: Chang Yong Kim
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Patent number: 6380054Abstract: The silicon real estate consumed by a conventional Schottky diode is reduced in the present invention by forming the Schottky diode through a field oxide isolation region. Etching through the field oxide isolation region requires extra etch time which is provided by conventional etch steps that typically specify a 50-100% overetch during contact formation.Type: GrantFiled: November 21, 2000Date of Patent: April 30, 2002Assignee: National Semiconductor CorporationInventors: Alexander Kalnitsky, Pavel Poplevine, Albert Bergemont
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Publication number: 20020048841Abstract: A silicon on insulator transistor is disclosed which has a Schottky contact to the body. The Schottky contact may be formed on the source and/or drain side of the gate conductor. A spacer, with at least a part thereof being disposable, is formed on the sidewalls of the gate conductor. Extension regions are provided in the substrate which extend under the spacer and the gate conductor. Source and drain diffusion regions are implanted into the substrate adjacent to the extension regions. The disposable part of the spacer is then removed to expose a portion of the extension region. A metal layer is formed at least in the extension regions, resulting in the Schottky contact.Type: ApplicationFiled: October 17, 2001Publication date: April 25, 2002Applicant: International Business Machines CorporationInventors: Andres Bryant, Jerome B. Lasky, Effendi Leobandung, Dominic J. Schepis
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Patent number: 6376288Abstract: A method of forming a TFT structure is performed on a glass substrate. A first metal layer deposited on the glass substrate is patterned with a first mask to form a gate line and a gate electrode. Next, a gate insulating layer, a first semiconductor layer and an etch-stop layer are successively formed, and backside exposure patterns the etch-stop layer. Thus, the remaining part of the etch-stop layer is disposed over the gate electrode and the gate line. Next, a second semiconductor layer and a second metal layer are successively formed, and then the second metal layer is patterned with a second mask to form a data line perpendicular to the gate line. Thereafter, the second semiconductor layer and the first semiconductor layer not covered by the second metal layer are removed.Type: GrantFiled: May 22, 2001Date of Patent: April 23, 2002Assignee: Hannstar Display Corp.Inventors: Tean-Sen Jen, Te-Cheng Chung, Ming-Tien Lin
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Method of manufacturing a gate electrode with low resistance metal layer remote from a semiconductor
Patent number: 6372613Abstract: In a semiconductor device, a gate electrode is formed by sequentially forming a Schottky metal film, a barrier metal film, and a low-resistance metal film from the lower side. The Schottky metal film or barrier metal film has a gap in a lower gate vertical portion. The gap is closed at its upper and lower portions. The overlaying low-resistance metal film does not extend into the lower gate vertical portion. A method for this semiconductor device is also disclosed.Type: GrantFiled: May 4, 1999Date of Patent: April 16, 2002Assignee: NEC CorporationInventor: Naoki Sakura -
Patent number: 6365494Abstract: A component is produced on a substrate made of SiC. The component has at least one ohmic contact and at least one Schottky contact. The component is brought to a temperature of more than 1300° C. at least during the growth of an epitaxial layer. To ensure that the production of the ohmic contact does not lead to impairment of other structures on the component and that the ohmic contact, for its part, is insensitive with respect to later method steps at high temperatures, the first metal is applied to the substrate for the ohmic contact before the epitaxial layer is grown.Type: GrantFiled: March 23, 2001Date of Patent: April 2, 2002Assignee: SiCED Electronics Development GmbH & Co. KG.Inventors: Roland Rupp, Arno Wiedenhofer
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Publication number: 20010049184Abstract: A high-sensitivity Pd/InP hydrogen sensor was made by a) forming an n-type or p-type semiconductor film on a semiconductor substrate; b) forming a patterned first metal electrode on said semiconductor film, wherein said first metal electrode forms an Ohmic contact with said semiconductor film; and c) forming a second metal electrode on said semiconductor film, said second metal electrode being isolated from said first metal electrode, wherein said second metal electrode forms a Schottky contact with said semiconductor film, wherein a thickness of said second metal electrode and a material of which said second metal electrode is made enable a Schottky barrier height of said Schottky contact to decrease when hydrogen contacts said second metal electrode. The second metal electrode can be physical vapor deposited or electroless plated.Type: ApplicationFiled: December 5, 2000Publication date: December 6, 2001Inventors: Huey-Ing Chen, Wen-Chau Liu, Yen-I Chou, Chin-Yi Chu, Hsi-Jen Pan
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METHOD OF MANUFACTURING A GATE ELECTRODE WITH LOW RESISTANCE METAL LAYER REMOTE FROM A SEMICONDUCTOR
Publication number: 20010046759Abstract: In a semiconductor device, a gate electrode is formed by sequentially forming a Schottky metal film, a barrier metal film, and a low-resistance metal film from the lower side. The Schottky metal film or barrier metal film has a gap in a lower gate vertical portion. The gap is closed at its upper and lower portions. The overlayering low-resistance metal film does not extend into the lower gate vertical portion. A method for this semiconductor device is also disclosed.Type: ApplicationFiled: May 4, 1999Publication date: November 29, 2001Inventor: NAOKI SAKURA -
Publication number: 20010039105Abstract: A component is produced on a substrate made of SiC. The component has at least one ohmic contact and at least one Schottky contact. The component is brought to a temperature of more than 1300° C. at least during the growth of an epitaxial layer. To ensure that the production of the ohmic contact does not lead to impairment of other structures on the component and that the ohmic contact, for its part, is insensitive with respect to later method steps at high temperatures, the first metal is applied to the substrate for the ohmic contact before the epitaxial layer is grown.Type: ApplicationFiled: March 23, 2001Publication date: November 8, 2001Inventors: Roland Rupp, Arno Wiedenhofer
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Patent number: 6307245Abstract: A method of producing a semiconductor device includes a semiconductor substrate and a gate embedding layer. A pair of side walls made of insulating layers having a width are formed on the inner surface of a first opening and the gate embedding layer is formed by using the pair of side walls and a first insulating layer as masks so that the embedded portion and the first extending portion are self-aligned and, consequently, the first extending portion is symmetrical with respect to the embedded portion. Accordingly, the first extending portion of the gate electrode is offset toward the drain electrode or source electrode.Type: GrantFiled: January 10, 2000Date of Patent: October 23, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuo Kunii, Naohito Yoshida
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Patent number: 6294445Abstract: A single mask process for manufacture of a FRED employs a thick oxide layer over an N type silicon surface and a thin nitride layer over the oxide. A single mask defines FRED device spaced P diffusions. The oxide spanning the P diffusions is laterally etched away, under the nitride layer to expose the surface of adjacent P diffusions and the spanning N type silicon surface. All nitride is then removed and a top contact layer of aluminum is applied atop the silicon surface, contacting a P guard ring diffusion; the surface of the P diffusions defining PN junctions; and the top of the N silicon to define a Schottky diode contact.Type: GrantFiled: February 22, 2000Date of Patent: September 25, 2001Assignee: International Rectifier Corp.Inventors: Igor Bol, Iftikhar Ahmed
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Patent number: 6287946Abstract: A method of reducing the specific contact resistivity of a metal to semiconductor interface between a metal contact and an InP semiconductor compound. The method includes the step of increasing the amount of the group V element (P) in the semiconductor compound so that the semiconductor compound is non-stoichiometric having an excess concentration of the group V element in an amount of at least 0.1% above stoichiometric levels.Type: GrantFiled: May 5, 1999Date of Patent: September 11, 2001Assignee: HRL Laboratories, LLCInventors: Miroslav Micovic, Daniel P. Docter
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Patent number: 6245602Abstract: A top gate, self-aligned polysilicon (poly-Si) thin film transistor (TFT) is formed using a single laser anneal to crystallize the active silicon and to activate the source-drain region. The poly-Si TFT includes a substrate, dummy gate, a barrier oxide layer, a polysilicon pattern having a source region and a drain region, a gate oxide, and a gate.Type: GrantFiled: November 18, 1999Date of Patent: June 12, 2001Assignee: Xerox CorporationInventors: Jackson Ho, Ronald T. Fulks
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Patent number: 6229193Abstract: A Schottky rectifier has multiple stages with substantially identical or very similar structures. Each stage includes a nitride-based semiconductor layer, a Schottky contact formed on one surface of the semiconductor layer, and an ohmic contact formed on an opposite surface of the semiconductor layer. The Schottky layer is formed from a metallic material with a high metal work function, and the ohmic contact is formed from a metallic material with a low metal work function. At least one of the stages is a middle stage located between two adjacent stages, such that the Schottky contact of the middle stage and the ohmic contact of one of the adjacent stages are joined together, and such that the ohmic contact of the middle stage and the Schottky contact of another one of the adjacent stages are joined together.Type: GrantFiled: April 1, 1999Date of Patent: May 8, 2001Assignee: California Institute of TechnologyInventors: Zvonimir Z. Bandic, Eric C. Piquette, Thomas C. McGill
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Patent number: 6225200Abstract: A semiconductor device has an improved schottky barrier junction. The device includes: a substrate; an epitaxial layer covering the substrate and lightly doped with a dopant selected from a group consisting of a rare earth element and an oxidant of a rare earth element; and a metal layer covering the epitaxial layer and forming said schottky barrier junction with said epitaxial layer.Type: GrantFiled: September 11, 1998Date of Patent: May 1, 2001Assignee: National Science CouncilInventors: Liann-Be Chang, Hang-Thung Wang
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Patent number: 6218688Abstract: The silicon real estate consumed by a conventional Schottky diode is reduced in the present invention by forming the Schottky diode through a field oxide isolation region. Etching through the field oxide isolation region requires extra etch time which is provided by conventional etch steps that typically specify a 50-100% overetch during contact formation.Type: GrantFiled: March 29, 1999Date of Patent: April 17, 2001Assignee: National Semiconductor CorporationInventors: Alexander Kalnitsky, Pavel Poplevine, Albert Bergemont
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Patent number: 6165824Abstract: A crystal growth 301 is carried out by diffusing a metal element, and a nickel element is moved into regions 108 and 109 which has been doped with phosphorus. An axis coincident with the moving directions 302 and 303 of the nickel element at this time is made to coincide with an axis coincident with the direction of the crystal growth, and a TFT having the regions as channel forming regions is manufactured. In the path of the region where nickel moved, since high crystallinity is obtained in the moving direction, the TFT having high characteristics can be obtained by this way.Type: GrantFiled: March 3, 1998Date of Patent: December 26, 2000Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Tamae Takano, Hideto Ohnuma, Hisashi Ohtani, Setsuo Nakajima, Shunpei Yamazaki
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Patent number: 6156611Abstract: A vertical FET is fabricated by etching through a contact layer into a drift layer on a compound semiconductor substrate to form a plurality of mesas, each mesa having an upper surface and each adjacent pair of mesas defining therebetween a trench with sidewalls and a bottom. A conductive layer is conformally deposited over the plurality of mesas and the trenches and anisotropically etched to form contacts on the sidewalls of the trenches and depositing source contacts on the upper surfaces of the mesas and a drain contact on a reverse side of the substrate.Type: GrantFiled: July 20, 1998Date of Patent: December 5, 2000Assignee: Motorola, Inc.Inventors: Ellen Lan, Jenn-Hwa Huang, Kurt Eisenbeiser, Yang Wang
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Patent number: 6150245Abstract: On a channel layer, there are disposed a gate electrode and a first contact layer of which a side surface is brought into contact with the gate electrode on the source side and of which a side surface is apart from the gate electrode on the drain side. Provided on the first contact layer is a second contact layer on which ohmic source and drain electrodes are arranged. A connection wiring is disposed on an upper end of the gate electrode. Specifically, there are provided a thin contact layer and a thick contact layer such that the thin contact layer is brought into contact with the gate electrode. Therefore, the problems of the contact resistance of the ohmic electrode and the gate parasitic capacitance are removed and both drawbacks can be improved at the same time.Type: GrantFiled: October 19, 1999Date of Patent: November 21, 2000Assignee: NEC CorporationInventor: Shuji Asai
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Patent number: 6133107Abstract: A DMOS device in a complex integrated circuit having a well region defined by a buried isolation region and an overlapping deep drain region within an epitaxial layer formed over a substrate, a body region having two source regions within the well region, insulated gates over the two source regions, and a Schottky contact over a central portion of the well region and spaced from the body region. The Schottky contact defines a Schottky diode within the epitaxial layer for diverting current from the substrate in the event of a below ground effect or an oversupply effect. The invention reduces or eliminates altogether the effects of parasitic transistors in the complex integrated circuit.Type: GrantFiled: February 3, 1999Date of Patent: October 17, 2000Assignee: STMicroelectronics, Inc.Inventor: Paolo Menegoli
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Patent number: 6127272Abstract: A method of performing electron beam lithography on high resistivity substrates including forming semiconductor material on a high resistivity substrate and etching the semiconductor material to form mesas with electrically interconnecting bridges between the mesas. Semiconductor devices are formed in the mesas employing electron beam lithography and charges generated by the electron beam lithography are dispersed along the interconnecting bridges thereby preventing charge accumulation on the mesas. The bridges are removed by etching or sawing during die separation.Type: GrantFiled: January 26, 1998Date of Patent: October 3, 2000Assignee: Motorola, Inc.Inventors: Charles E. Weitzel, Karen E. Moore
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Patent number: 6121122Abstract: A method of contacting a silicide-based Schottky diode including the step of providing a contact to the silicide that is fully bordered with respect to an internal edge of the guard ring area. A Schottky diode having silicide contacting a guard ring of the Schottky diode and a contact to the silicide that is fully bordered by silicide with respect to an internal edge of the guard ring.Type: GrantFiled: May 17, 1999Date of Patent: September 19, 2000Assignee: International Business Machines CorporationInventors: James Stuart Dunn, Peter Brian Gray, Kenneth Knetch Kieft, III, Nicholas Theodore Schmidt, Stephen St. onge
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Patent number: 6117713Abstract: An insulating layer is formed on a semiconductor substrate, and a first resist layer having a first resist opening portion is formed on the insulating layer. Then, the insulating layer is etched thought the opening portion to expose the substrate. After removing the first resist layer, a second resist layer having second resist opening portions are formed. One of the second resist opening portions is provided to expose the substrate, and a recess is formed in the substrate through the opening portion. Further, the insulating layer exposed from the other of the second resist opening portions is removed. Then, an electrode member for gate, source, and drain electrodes is deposited on the substrate. As a result, variations in intervals between the gate and drain electrodes and between the gate and source electrodes can be reduced.Type: GrantFiled: February 6, 1998Date of Patent: September 12, 2000Assignee: Denso CorporationInventors: Koichi Hoshino, Tetsuya Katayama
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Patent number: 6093628Abstract: A method for fabricating a deep sub-micron gate electrode, comprising polysilicon and metal, having ultra-low sheet resistance. The process begins by forming shallow trench isolation regions 14 in a silicon substrate 10. A gate oxide layer is formed on device areas. A doped blanket polysilicon layer 16 is formed on the gate oxide layer. A cap layer 20 composed of silicon nitride is formed on the polysilicon layer 16. The cap layer 20 and the polysilicon layer 16 are patterned by photoresist masking and anisotropic etching to form a bottom gate electrode 16A and a gate cap 20A. Lightly doped source/drain areas 22 are formed adjacent to the gate bottom electrodes 16A by ion implantation. Sidewall spacers 21 are formed on the gate electrode 16A and gate cap 20A. Source/drain regions 24 are formed by ion implantation adjacent to said sidewall spacers 21. A metal silicide 23 is formed on the source/drain regions 24.Type: GrantFiled: October 1, 1998Date of Patent: July 25, 2000Assignees: Chartered Semiconductor Manufacturing, Ltd, National University of SingaporeInventors: Chong Wee Lim, Kin Leong Pey, Soh Yun Siah, Eng Hwa Lim, Lap Chan
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Patent number: 6090649Abstract: A Schottky barrier layer in separate regions between a source electrode and a gate electrode and between a drain electrode and the gate electrode is completely covered with an etching stopper layer. The gate electrode is separated from a cap layer.Type: GrantFiled: December 23, 1999Date of Patent: July 18, 2000Assignee: Nippon Telegraph and Telephone CorporationInventors: Tetsuya Suemitsu, Takatomo Enoki
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Patent number: 6083782Abstract: An improved GaAs MESFET includes a source contact ohmically coupled to a buffer layer or substrate to stabilize band bending at the interface of the active layer and buffer layer or substrate when an RF signal is applied to a gate electrode.Type: GrantFiled: October 21, 1999Date of Patent: July 4, 2000Assignee: Samsung Electronics Co., Ltd.Inventor: Jong Boong Lee
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Patent number: 6078067Abstract: On a semiconductor substrate, a channel layer, an electron supply layer, a third semiconductor layer, a second etching stopper layer, a second semiconductor layer and a first etching stopper layer and a first semiconductor layer are grown in sequential order to form E-type and D-type FETs. The third semiconductor layer and the second semiconductor layer have equal layer thickness, and the second etching stopper layer and the first etching stopper layer have the equal layer thickness. Thus, Vth of the E-type and D-type FETs can be controlled at the predetermined value with high reproduction ability.Type: GrantFiled: September 29, 1997Date of Patent: June 20, 2000Assignee: NEC CorporationInventor: Hirokazu Oikawa
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Patent number: 6057219Abstract: An ohmic contact to a III-V semiconductor material is fabricated by dry etching a silicon nitride layer overlying the III-V semiconductor material with a chemical comprised of a group VI element. An ohmic metal layer is formed on the III-V semiconductor material after the silicon nitride layer is etched and before any exposure of the III-V semiconductor material to a chemical which etches the III-V semiconductor material or removes the group VI element.Type: GrantFiled: July 1, 1994Date of Patent: May 2, 2000Assignee: Motorola, Inc.Inventors: Jaeshin Cho, Gregory L. Hansell, Naresh Saha
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Patent number: 6033929Abstract: A II-VI group compound semiconductor device includes a semiconductor substrate, a Zn.sub.X Mg.sub.1-X S.sub.Y Se.sub.1-Y (0.ltoreq.X.ltoreq.1, 0.ltoreq.Y.ltoreq.1) semiconductor layer formed on the semiconductor substrate, and an electrode layer formed on the semiconductor layer, the electrode layer containing an additive element of Cd or Te and a metal which can form a eutectic alloy with the additive element, thus achieving an electrode layer having a small contact resistance, especially an electrode layer with an ohmic contact.Type: GrantFiled: March 22, 1996Date of Patent: March 7, 2000Assignee: Sharp Kabushiki KaishaInventors: Masanori Murakami, Yasuo Koide, Nobuaki Teraguchi