Forming Schottky Junction (i.e., Semiconductor-conductor Rectifying Junction Contact) Patents (Class 438/570)
  • Patent number: 11119012
    Abstract: An apparatus and method for cleaving a liquid sample are disclosed. The apparatus includes a load lock chamber containing a cleaving module, a cryo-cooler, a vacuum chamber configured to receive the cleaving module from the load lock chamber, and a gate valve between the load lock chamber and the vacuum chamber. The cleaving module is configured to cleave a crystalline sample holder and the liquid sample. The liquid sample includes one or more liquid phase materials and is cleavable by the cleaving module when in the solid phase. The cryo-cooler is configured to cool and/or maintain a temperature of the sample holder and the sample below the melting point of each of the liquid phase materials. The gate valve has at least one opening therein configured to (i) allow the cleaving module to enter and exit the vacuum chamber and/or (ii) permit gaseous communication between the load lock chamber and the vacuum chamber.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: September 14, 2021
    Assignee: IB Labs, Inc.
    Inventors: Dimitry Boguslavsky, Mark Kovler
  • Patent number: 9893049
    Abstract: The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region, a first well region having a first conductive type formed in the active region, a first doped region having the first conductive type formed in the first well region, a first metal contact disposed on the first doped region, and a second metal contact disposed on the active region, connecting to the first well region, wherein no doped region is formed between the second metal contact and the first well region.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: February 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Zheng Zeng, Ching-Chung Ko, Bo-Shih Huang
  • Patent number: 9287414
    Abstract: An integrated circuit including a Schottky diode, and a method of making the same. The diode includes an active region bordered by an isolation region in a semiconductor substrate of the integrated circuits, a first electrode having a metal contact provided on a surface of the active region, and a second electrode having a silicide contact also provided on the surface of the active region.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: March 15, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Georgios Vellianitis, Gilberto Curatola, Kyriaki Fotopoulou, Nader Akil
  • Patent number: 9035414
    Abstract: A semiconductor device includes a semiconductor layer and a Schottky electrode, a Schottky junction being formed between the semiconductor layer and the Schottky electrode. The Schottky electrode includes a metal part containing a metal, a Schottky junction being formed between the semiconductor layer and the metal part; and a nitride part around the metal part, the nitride part containing a nitride of the metal, and a Schottky junction being formed between the semiconductor layer and the nitride part.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Yuichi Minoura, Naoya Okamoto
  • Publication number: 20150132932
    Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.
    Type: Application
    Filed: January 21, 2015
    Publication date: May 14, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Bruce M. Green, Darrell G. Hill, Jenn Hwa Huang, Karen E. Moore
  • Publication number: 20150130013
    Abstract: A semiconductor device includes at least one ohmic contact region between a semiconductor substrate of the semiconductor device and an electrically conductive structure arranged adjacent to the semiconductor substrate. Further, the semiconductor device includes at least one Schottky contact region between the semiconductor substrate of the semiconductor device and the electrically conductive structure. The at least one ohmic contact region is arranged adjacent to the at least one Schottky contact region. The semiconductor substrate includes a first doping layer arranged adjacent to the electrically conductive structure. An average doping concentration of the surface region of the first doping layer in an area of the at least one ohmic contact region differs from an average doping concentration of the surface region of the first doping layer in an area of the at least one Schottky contact region by less than 10%.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 14, 2015
    Applicant: Infineon Technologies AG
    Inventors: Holger Hüsken, Anton Mauder, Hans-Joachim Schulze, Wolfgang Rösner, Holger Schulze
  • Publication number: 20150123235
    Abstract: A semiconductor device includes a substrate, a counter-doping region, and a Schottky barrier diode (SBD) in which a breakdown voltage is improved by using counter doping, and a manufacturing method thereof. A breakdown voltage may be improved by lowering a concentration of impurity on the region and enhancing the characteristics of the semiconductor device including the SBD.
    Type: Application
    Filed: June 25, 2014
    Publication date: May 7, 2015
    Applicant: MagnaChip Semiconductor, Ltd.
    Inventors: Yong Won LEE, Jin Woo HAN, Dae Won HWANG, Kyung Wook KIM
  • Patent number: 9018638
    Abstract: A MOSFET device is provided. An N-type epitaxial layer is disposed on an N-type substrate. An insulating trench is disposed in the epitaxial layer. A P-type well region is disposed in the epitaxial layer at one side of the insulating trench. An N-type heavily doped region is disposed in the well region. A gate structure is disposed on the epitaxial layer and partially overlaps with the heavily doped region. At least two P-type first doped regions are disposed in the epitaxial layer below the well region. At least one P-type second doped region is disposed in the epitaxial layer and located between the first doped regions. Besides, the first and second doped regions are separated from each other. The first doped regions extend along a first direction, and the second doped region extends along a second direction different from the first direction.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: April 28, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Chee-Wee Liu, Hui-Hsuan Wang
  • Patent number: 9000550
    Abstract: A semiconductor component having a low resistance conduction path and a method for manufacturing the semiconductor component. When the semiconductor component is a Schottky diode, one or more trenches are formed in an epitaxial layer of a first conductivity type that is formed over a semiconductor substrate of the first conductivity type. The trenches may extend into the semiconductor material. Epitaxial semiconductor material of a second conductivity type is selectively grown along the sidewalls of the trenches. An anode contact is formed in contact with the epitaxial layer and the selectively grown epitaxial material and a cathode contact is formed in contact with the semiconductor substrate.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: April 7, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventor: Mohammed Tanvir Quddus
  • Patent number: 8980732
    Abstract: The present invention provides a method for manufacturing a silicon carbide Schottky barrier diode. In the method, an n? epitaxial layer is deposited on an n+ substrate. A sacrificial oxide film is formed on the n? epitaxial layer by heat treatment, and then a portion where a composite oxide film is to be formed is exposed by etching. Nitrogen is implanted into the n? epitaxial layer and the sacrificial oxide film using nitrogen plasma. A silicon nitride is deposited on the n? epitaxial layer and the sacrificial oxide film. The silicon nitride is thermally oxidized to form a composite oxide film. An oxide film in a portion where a Schottky metal is to be deposited is etched, and then the Schottky metal is deposited, thereby forming a silicon carbide Schottky barrier diode.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: March 17, 2015
    Assignee: Hyundai Motor Company
    Inventors: Kyoung Kook Hong, Jong Seok Lee
  • Patent number: 8969994
    Abstract: An MPS diode includes a III-nitride substrate characterized by a first conductivity type and a first dopant concentration and having a first side and a second side. The MPS diode also includes a III-nitride epitaxial structure comprising a first III-nitride epitaxial layer coupled to the first side of the substrate, wherein a region of the first III-nitride epitaxial layer comprises an array of protrusions. The III-nitride epitaxial structure also includes a plurality of III-nitride regions of a second conductivity type, each partially disposed between adjacent protrusions. Each of the plurality of III-nitride regions of the second conductivity type comprises a first section laterally positioned between adjacent protrusions and a second section extending in a direction normal to the first side of the substrate. The MPS diode further includes a first metallic structure electrically coupled to one or more of the protrusions and to one or more of the second sections.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: March 3, 2015
    Assignee: Avogy, Inc.
    Inventors: Madhan M. Raj, Brian Alvarez, David P. Bour, Andrew P. Edwards, Hui Nie, Isik C. Kizilyalli
  • Patent number: 8969995
    Abstract: High-efficiency Schottky diodes (HED) and rectifier systems having such semiconductor devices are provided, which Schottky diodes (HED) are composed of at least one Schottky diode combined with an additional semiconductor element, e.g., with magnetoresistors (TMBS) or with pn diodes (TJBS), and have trenches. Such high-efficiency Schottky diodes make it possible to construct rectifiers which are suitable for higher temperatures and can therefore be used in motor vehicle generators, without particular cooling measures such as heat sinks being required.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: March 3, 2015
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Gert Wolf, Markus Mueller
  • Publication number: 20150056788
    Abstract: A semiconductor device includes a semiconductor body with a first surface, a contact electrode arranged on the first surface, and a passivation layer on the first surface adjacent the contact electrode. The passivation layer includes a layer stack with an amorphous semi-insulating layer on the first surface, a first nitride layer on the amorphous semi-insulating layer, and a second nitride layer on the first nitride layer.
    Type: Application
    Filed: September 30, 2014
    Publication date: February 26, 2015
    Inventors: Gerhard Schmidt, Josef-Georg Bauer, Carsten Schaeffer, Oliver Humbel, Angelika Koprowski, Sirinpa Monayakul
  • Patent number: 8963275
    Abstract: A resistive-switching random access memory device includes a memory cell disposed between a bit line and a word line, the memory cell having a resistive-switching element (40) and a Schottky diode (30). The Schottky diode (30) and the resistive-switching element (40) are connected in series. The Schottky diode (30) includes a metal layer and a semiconductor layer contacting each other. An interface between the metal layer and the semiconductor layer has a non-planar shape.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: February 24, 2015
    Assignee: Peking University
    Inventors: Jinfeng Kang, Bin Gao, Lifeng Liu, Xiaoyan Liu
  • Patent number: 8962461
    Abstract: Consistent with an example embodiment, a GaN heterojunction structure has a three-layer dielectric structure. The lowermost and middle portions of the gate electrode together define the gate foot, and this is associated with two dielectric layers. A thinner first dielectric layer is adjacent the gate edge at the bottom of the gate electrode. The second dielectriclayer corresponds to the layer in the conventional structure, and it is level with the main portion of the gate foot.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: February 24, 2015
    Assignee: NXP B.V.
    Inventors: Godefridus Adrianus Maria Hurkx, Jeroen Antoon Croon, Johannes Josephus Theodorus Marinus Donkers, Stephan Heil, Jan Sonsky
  • Patent number: 8957494
    Abstract: A high-voltage Schottky diode and a manufacturing method thereof are disclosed in the present disclosure. The diode includes: a P-type substrate and two N-type buried layers, a first N-type buried layer is located below a cathode lead-out area, and a second N-type buried layer is located below a cathode region; an epitaxial layer; two N-type well regions located on the epitaxial layer, a first N-type well region is a lateral drift region and it is provided with a cathode lead-out region, and a second N-type well region is located on the second N-type buried layer and it is a cathode region; a first P-type well region located on the second N-type buried layer and surrounding the cathode region; a field oxide isolation region located on the lateral drift region; an anode located on the cathode region and a cathode located on the surface of the cathode lead-out region.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: February 17, 2015
    Assignee: CSMC Technologies FAB1 Co., Ltd.
    Inventor: Lihui Gu
  • Patent number: 8951832
    Abstract: Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Patent number: 8936964
    Abstract: The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n? epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n? epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n? epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: January 20, 2015
    Assignee: Hyundai Motor Company
    Inventors: Kyoung Kook Hong, Jong Seok Lee
  • Patent number: 8916459
    Abstract: A compound semiconductor device having mesa-shaped element region, and excellent characteristics are provided. The compound semiconductor device has: an InP substrate; an epitaxial lamination mesa formed above the InP substrate and including a channel layer, a carrier supply layer above the channel layer and a contact cap layer above the carrier supply layer; ohmic source electrode and drain electrode formed on the cap layer; a recess formed by removing the cap layer between the source and drain electrodes, and exposing the carrier supply layer; an insulating film formed on the cap layer and retracted from an edge of the cap layer away from the recess; a gate electrode extending from the carrier supply layer in the recess to outside of the mesa; and air gap formed by removing side portion of the channel layer facing the gate electrode outside the mesa.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: December 23, 2014
    Assignee: Fujitsu Limited
    Inventors: Tsuyoshi Takahashi, Kozo Makiyama
  • Publication number: 20140349470
    Abstract: A Schottky diode includes a deep well formed in a substrate, an isolation layer formed in the substrate, a first conductive type guard ring formed in the deep well along an outer sidewall of the isolation layer and located at a left side of the isolation layer, a second conductive type well formed in the deep well along the outer sidewall of the isolation layer and located at a right side of the isolation layer, an anode electrode formed over the substrate and coupled to the deep well and the guard ring, and a cathode electrode formed over the substrate and coupled to the well. A part of the guard ring overlaps the isolation layer.
    Type: Application
    Filed: August 7, 2014
    Publication date: November 27, 2014
    Applicant: MAGNACHIP SEMICONDUCTOR, LTD.
    Inventor: Jin-Yeong Son
  • Patent number: 8884395
    Abstract: A Schottky diode includes a deep well formed in a substrate, an isolation layer formed in the substrate, a first conductive type guard ring formed in the deep well along an outer sidewall of the isolation layer and located at a left side of the isolation layer, a second conductive type well formed in the deep well along the outer sidewall of the isolation layer and located at a right side of the isolation layer, an anode electrode formed over the substrate and coupled to the deep well and the guard ring, and a cathode electrode formed over the substrate and coupled to the well. A part of the guard ring overlaps the isolation layer.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: November 11, 2014
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jin-Yeong Son
  • Patent number: 8872235
    Abstract: An embodiment of a transistor device includes a compound semiconductor material on a semiconductor carrier and a source region and a drain region spaced apart from each other in the compound semiconductor material with a channel region interposed between the source and drain regions. A Schottky diode is integrated with the semiconductor carrier, and contacts extend from the source and drain regions through the compound semiconductor material. The contacts are in electrical contact with the Schottky diode so that the Schottky diode is connected in parallel between the source and drain regions. In another embodiment, the integrated Schottky diode is formed by a region of doped amorphous silicon or doped polycrystalline silicon disposed in a trench structure on the drain side of the device.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: October 28, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen
  • Patent number: 8871621
    Abstract: MIMCAP devices are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP devices can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a low defect dielectric layer, a high defect dielectric layer, sandwiched between two electrodes having different work function values.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: October 28, 2014
    Assignee: Intermolecular, Inc.
    Inventors: Venkat Ananthan, Imran Hashim, Prashant B. Phatak
  • Publication number: 20140264713
    Abstract: Embodiments of a gate contact for a semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, a semiconductor device includes a semiconductor structure and a dielectric layer on a surface of the semiconductor structure, where the dielectric layer has an opening that exposes an area of the semiconductor structure. A gate contact for the semiconductor device is formed on the exposed area of the semiconductor structure through the opening in the dielectric layer. The gate contact includes a proximal end on a portion of the exposed area of the semiconductor structure, a distal end opposite the proximal end, and sidewalls that each extend between the proximal end and the distal end of the gate contact. For each sidewall of the gate contact, an air region separates the sidewall and the distal end of the gate contact from the dielectric layer.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 18, 2014
    Applicant: CREE, INC.
    Inventors: Fabian Radulescu, Helmut Hagleitner
  • Patent number: 8836071
    Abstract: A method of fabricating a Schottky diode using gallium nitride (GaN) materials includes providing an n-type GaN substrate having a first surface and a second surface. The second surface opposes the first surface. The method also includes forming an ohmic metal contact electrically coupled to the first surface of the n-type GaN substrate and forming an n-type GaN epitaxial layer coupled to the second surface of the n-type GaN substrate. The method further includes forming an n-type aluminum gallium nitride (AlGaN) surface layer coupled to the n-type GaN epitaxial layer and forming a Schottky contact electrically coupled to the n-type AlGaN surface layer.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: September 16, 2014
    Assignee: Avogy, Inc.
    Inventors: Richard J. Brown, Thomas R. Prunty, David P. Bour, Isik C. Kizilyalli, Hui Nie, Andrew P. Edwards, Linda Romano, Madhan Raj
  • Patent number: 8815716
    Abstract: A semiconductor device includes a semiconductor layer (1) containing GaN and an electrode. The electrode includes an electrode main body (6), a connection-use electrode (8) containing Al and formed at a position farther from the semiconductor layer (1) than the electrode main body (6), and a barrier layer (7) formed between the electrode main body (6) and the connection-use electrode (8), the barrier layer (7) containing at least one selected from the group consisting of W, TiW, WN, TiN, Ta, and TaN. A surface roughness RMS of the barrier layer (7) is 3.0 nm or less.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: August 26, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomihito Miyazaki, Makoto Kiyama, Taku Horii
  • Patent number: 8796808
    Abstract: A MOS P-N junction Schottky diode device includes a substrate having a first conductivity type, a field oxide structure defining a trench structure, a gate structure formed in the trench structure and a doped region having a second conductivity type adjacent to the gate structure in the substrate. An ohmic contact and a Schottky contact are formed at different sides of the gate structure. The method for manufacturing such diode device includes several ion-implanting steps to form several doped sub-regions with different implantation depths to constitute the doped regions. The formed MOS P-N junction Schottky diode device has low forward voltage drop, low reverse leakage current, fast reverse recovery time and high reverse voltage tolerance.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: August 5, 2014
    Assignee: PFC Device Corp.
    Inventors: Kuo-Liang Chao, Hung-Hsin Kuo, Tse-Chuan Su
  • Patent number: 8772900
    Abstract: The present invention discloses a trench Schottky barrier diode (SBD) and a manufacturing method thereof. The trench SBD includes: an epitaxial layer, formed on a substrate; multiple mesas, defined by multiple trenches; a field plate, formed on the epitaxial layer and filled in the multiple trenches, wherein a Schottky contact is formed between the field plate and top surfaces of the mesas; a termination region, formed outside the multiple mesas and electrically connected to the field plate; a field isolation layer, formed on the upper surface and located outside the termination region; and at least one mitigation electrode, formed below the upper surface outside the termination region, and is electrically connected to the field plate through the field isolation layer, wherein the mitigation electrode and the termination region are separated by part of a dielectric layer and part of the epitaxial layer.
    Type: Grant
    Filed: July 8, 2012
    Date of Patent: July 8, 2014
    Assignee: Richteck Technology Corporation
    Inventors: Tsung-Yi Huang, Chien-Hao Huang
  • Publication number: 20140183439
    Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Applicant: Intermolecular, Inc.
    Inventors: Imran Hashim, Venkat Ananthan, Tony P. Chiang, Prashant B. Phatak
  • Patent number: 8766395
    Abstract: A device includes a Schottky barrier formed by a metal-semiconductor junction between a semiconductor nanowire and a metal contact. The metal contact at least partly encloses a circumferential area of each nanowire along the length thereof. The nanowire includes a low doped region that is part of the metal-semiconductor junction. The device can be fabricated using a method where two different growth modes are used, the first step including axial growth from a substrate giving a suitable template for formation of the metal-semiconductor junction, and the second step including radial growth enabling control of the doping levels in the low doped region.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: July 1, 2014
    Assignee: Qunano AB
    Inventor: Steven Konsek
  • Patent number: 8765523
    Abstract: A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main surface, and forming a Schottky electrode in contact with the main surface that has been exposed by removing the oxide film.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda
  • Patent number: 8759922
    Abstract: Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: June 24, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Peter Javorka, Stefan Flachowsky, Thilo Scheiper
  • Patent number: 8749014
    Abstract: The present invention discloses a Schottky diode. The Schottky diode comprises a cathode region, an anode region and a guard ring region. The anode region may comprise a metal Schottky contact. The guard ring region may comprise an outer guard ring and a plurality of inner guard stripes inside the outer guard ring. And wherein the inner guard stripe has a shallower junction depth than the outer guard ring.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: June 10, 2014
    Assignee: Monolithic Power Systems, Inc.
    Inventor: Ji-Hyoung Yoo
  • Publication number: 20140145290
    Abstract: A high-voltage Schottky diode and a manufacturing method thereof are disclosed in the present disclosure. The diode includes: a P-type substrate and two N-type buried layers, a first N-type buried layer is located below a cathode lead-out area, and a second N-type buried layer is located below a cathode region; an epitaxial layer; two N-type well regions located on the epitaxial layer, a first N-type well region is a lateral drift region and it is provided with a cathode lead-out region, and a second N-type well region is located on the second N-type buried layer and it is a cathode region; a first P-type well region located on the second N-type buried layer and surrounding the cathode region; a field oxide isolation region located on the lateral drift region; an anode located on the cathode region and a cathode located on the surface of the cathode lead-out region.
    Type: Application
    Filed: October 23, 2012
    Publication date: May 29, 2014
    Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.
    Inventor: Lihui Gu
  • Patent number: 8735228
    Abstract: A trench isolation metal-oxide-semiconductor (MOS) P-N junction diode device and a manufacturing method thereof are provided. The trench isolation MOS P-N junction diode device is a combination of an N-channel MOS structure and a lateral P-N junction diode, wherein a polysilicon-filled trench oxide layer is buried in the P-type structure to replace the majority of the P-type structure. As a consequence, the trench isolation MOS P-N junction diode device of the present invention has the benefits of the Schottky diode and the P-N junction diode. That is, the trench isolation MOS P-N junction diode device has rapid switching speed, low forward voltage drop, low reverse leakage current and short reverse recovery time.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: May 27, 2014
    Assignee: PFC Device Corp.
    Inventors: Mei-Ling Chen, Hung-Hsin Kuo, Kuo-Liang Chao
  • Patent number: 8735257
    Abstract: Apparatus and methods for a MOS varactor structure are disclosed. An apparatus is provided, comprising an active area defined in a portion of a semiconductor substrate; a doped well region in the active area extending into the semiconductor substrate; at least two gate structures disposed in parallel over the doped well region; source and drain regions disposed in the well region formed on opposing sides of the gate structures; a gate connector formed in a first metal layer overlying the at least two gate structures and electrically coupling the at least two gate structures; source and drain connectors formed in a second metal layer and electrically coupled to the source and drain regions; and interlevel dielectric material separating the source and drain connectors in the second metal layer from the gate connector formed in the first metal layer. Methods for forming the structure are disclosed.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Feng Huang, Chia-Chung Chen
  • Patent number: 8735861
    Abstract: A semiconductor storage device according to an embodiment includes a first conductive layer, a variable resistance layer, an electrode layer, a first liner layer, a stopper layer, and a second conductive layer. The first liner layer is configured by a material having a property for canceling an influence of an orientation of a lower layer of the first liner layer, the property of the first liner layer being superior compared with that of the stopper layer. The stopper layer is acted upon by an internal stress in a compressive direction at room temperature.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: May 27, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kotaro Noda
  • Publication number: 20140138705
    Abstract: The present disclosure relates to a semiconductor device having a Schottky contact that provides both super surge capability and low reverse-bias leakage current. In one preferred embodiment, the semiconductor device is a Schottky diode and even more preferably a Silicon Carbide (SiC) Schottky diode. However, the semiconductor device may more generally be any type of semiconductor device having a Schottky contact such as, for example, a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET).
    Type: Application
    Filed: November 20, 2012
    Publication date: May 22, 2014
    Applicant: CREE, INC.
    Inventors: Qingchun Zhang, Jennifer Duc
  • Patent number: 8679954
    Abstract: A schottky diode includes a SiC substrate which has a first surface and a second surface facing away from the first surface, a semiconductor layer which is formed on the first surface of the SiC substrate, a schottky electrode which is in contact with the semiconductor layer, and an ohmic electrode which is in contact with the second surface of the SiC substrate. The first surface of the SiC substrate is a (000-1) C surface, upon which the semiconductor layer is formed.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: March 25, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Shingo Ohta, Tatsuya Kiriyama, Takashi Nakamura, Yuji Okamura
  • Patent number: 8674333
    Abstract: Variable-resistance memory material cells are contacted by vertical bottom spacer electrodes. Variable-resistance material memory spacer cells are contacted along the edge by electrodes. Processes include the formation of the bottom spacer electrodes as well as the variable-resistance material memory spacer cells. Devices include the variable-resistance memory cells.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: March 18, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jun Liu
  • Publication number: 20140061848
    Abstract: An integrated circuit structure includes a substrate, a semiconductor device supported by the substrate, and a guard ring structure disposed around the semiconductor device, the guard ring structure forming a Schottky junction. In an embodiment, the Schottky junction is formed from a p-type metal contact and an n-type guard ring. In an embodiment, the guard ring structure is electrically coupled to a positive or negative supply voltage.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Feng Chang, Jam-Wem Lee
  • Patent number: 8647971
    Abstract: An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: February 11, 2014
    Assignee: Intersil Americas Inc.
    Inventors: Dev Alok Girdhar, Michael David Church, Alexander Kalnitsky
  • Publication number: 20140021827
    Abstract: Primary voltaic sources include nanofiber Schottky barrier arrays and a radioactive source including at least one radioactive element configured to emit radioactive particles. The arrays have a semiconductor component and a metallic component joined at a metal-semiconductor junction. The radioactive source is positioned proximate to the arrays such that at least a portion of the radioactive particles impinge on the arrays to produce a flow of electrons across the metal-semiconductor junction. Methods of producing voltaic sources include reacting at least one carbon oxide and a reducing agent in the presence of a substrate comprising a catalyst to form a solid carbon product over the substrate. Material is disposed over at least a portion of the solid carbon product to form a nanofiber Schottky barrier array. A radioactive source is disposed adjacent the nanofiber Schottky barrier array.
    Type: Application
    Filed: July 17, 2013
    Publication date: January 23, 2014
    Inventor: Dallas B. Noyes
  • Publication number: 20130341705
    Abstract: In an LDMOS device leakage and forward conduction parameters are adjusted by integrating an Schottky diode into the LDMOS by substituting one or more n+ source regions with Schottky diodes.
    Type: Application
    Filed: August 30, 2013
    Publication date: December 26, 2013
    Applicant: Texas Instruments Incorporated
    Inventors: Venkat Raghavan, Andrew D. Strachan
  • Patent number: 8604525
    Abstract: An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: December 10, 2013
    Assignee: Vishay-Siliconix
    Inventor: Kyle Terrill
  • Patent number: 8592293
    Abstract: A method for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey B. Johnson, Xuefeng Liu, Bradley A. Orner, Robert M. Rassel
  • Patent number: 8592298
    Abstract: A method for fabricating edge termination structures in gallium nitride (GaN) materials includes providing a n-type GaN substrate having a first surface and a second surface, forming an n-type GaN epitaxial layer coupled to the first surface of the n-type GaN substrate, and forming a growth mask coupled to the n-type GaN epitaxial layer. The method further includes patterning the growth mask to expose at least a portion of the n-type GaN epitaxial layer, and forming at least one p-type GaN epitaxial structure coupled to the at least a portion of the n-type GaN epitaxial layer. The at least one p-type GaN epitaxial structure comprises at least one portion of an edge termination structure. The method additionally includes forming a first metal structure electrically coupled to the second surface of the n-type GaN substrate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: November 26, 2013
    Assignee: Avogy, Inc.
    Inventors: Linda Romano, David P. Bour, Andrew Edwards, Hui Nie, Isik C. Kizilyalli, Richard J. Brown, Thomas R. Prunty
  • Patent number: 8581360
    Abstract: A trench Schottky diode and a manufacturing method thereof are provided. A plurality of trenches are formed in A semiconductor substrate. A plurality of doped regions are formed in the semiconductor substrate and under some of the trenches. A gate oxide layer is formed on a surface of the semiconductor substrate and the surfaces of the trenches. A polysilicon structure is formed on the gate oxide layer. Then, the polysilicon structure is etched, so that the gate oxide layer within the trenches is covered by the polysilicon structure. Then, a mask layer is formed to cover the polysilicon structure within a part of the trenches and a part of the gate oxide layer, and the semiconductor substrate uncovered by the mask layer is exposed. Afterwards, a metal sputtering layer is formed to cover a part of the surface of the semiconductor substrate.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: November 12, 2013
    Inventor: Tzu-Hsiung Chen
  • Publication number: 20130292695
    Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.
    Type: Application
    Filed: July 3, 2013
    Publication date: November 7, 2013
    Inventors: Taku HORII, Tomihito Miyazaki, Makato Kiyama
  • Publication number: 20130288449
    Abstract: A diode (200) is disclosed having improved efficiency, smaller form factor, and reduced reverse biased leakage current. Schottky diodes (212) are formed on the sidewalls (210) of a mesa region (206). The mesa region (206) is a cathode of the Schottky diode (212). The current path through the mesa region (206) has a lateral and a vertical current path. The diode (200) further comprises a MOS structure (214), p-type regions (220), MOS structures (230), and p-type regions (232). MOS structure (214) with the p-type regions (220) pinch-off the lateral current path under reverse bias conditions. P-type regions (220), MOS structures (230), and p-type regions (232) each pinch-off the vertical current path under reverse bias conditions. MOS structure (214) and MOS structures (230) reduce resistance of the lateral and vertical current path under forward bias conditions. The mesa region (206) can have a uniform or non-uniform doping concentration.
    Type: Application
    Filed: June 28, 2013
    Publication date: October 31, 2013
    Inventors: Gordon M. Grivna, Jefferson W. Hall, Mohammed Tanvir Quddus