Abstract: A semiconductor fabrication method for fabricating a flash EEPROM (electrically erasable and programmable read-only memory) device uses STI (shallow-trench isolation) technique to form the field oxide isolation layers so as to make the EEPROM device suitable for fabrication at the submicron level of integration. By this method, the first step is to prepare a semiconductor substrate. Next, a plurality of field oxide isolation layers are formed through the STI technique to define active region in the substrate. After this, at least one gate structure is formed within the active region, which includes a tunnel oxide layer, a first conductive layer serving as a floating gate, a dielectric layer, a second conductive layer serving as a control gate, and a topping layer. Subsequently, an ion-implantation process is performed to form source/drain regions beside the gate structure. A sidewall spacer is then formed on the sidewall of the gate structure.

Abstract: The specification describes methods for making T-shaped metal gates for Schottky gate devices such as MESFETs and HEMTs. The method uses a bi-level photoresist technique to create a T-shaped feature for the gate structure. The metal gate is evaporated into the photoresist T-shaped feature and a lift-off process is used to remove unwanted metal. The photoresist is the dissolved away leaving the T-shaped gate. An important aspect of the process is the use of a plasma treatment of the first patterned resist level to harden it so that it is unaffected by the subsequent deposition and patterning of the second level resist.

Abstract: A method for fabricating a periodic table group III-IV field-effect transistor device is described. The disclosed fabrication arrangement uses a single metallization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent semiconductor material secondary mask element, a mask element which can be grown epitaxially during wafer fabrication. The invention includes provisions for both an all optical lithographic process and a combined optical and electron beam lithographic process These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state of the art electrical performance.

Abstract: Fabricating a device including a Schottky diode by growing a dielectric film on a SiC substrate structure and forming an ohmic contact on the opposite surface of the substrate structure by depositing a layer of metal and annealing at a temperature above 900.degree. C. Implanting doping material in the substrate structure through spaced apart openings to form high resistivity areas and depositing a dielectric layer on the dielectric film to define a contact opening positioned between the spaced apart high resistivity areas. Annealing the implant at a temperature less than approximately 400.degree. C. to reduce reverse leakage current and depositing metal in the contact opening to form a Schottky contact.

Abstract: There is provided a technique for fabricating a thin film transistor having excellent performance. A configuration is employed in which when the thin film transistor is in an on-state, the flowing direction of the on-current coincides with the direction of crystal growth. With such a configuration, grain boundaries of the crystalline silicon in the active layer will not block the on-current. Further, when the thin film transistor is in an off-state, the off-current is always orthogonal to the grain boundaries of the crystalline silicon. The grain boundaries of the crystalline silicon effectively suppresses the off-current in such locations.

Abstract: A method for forming a contact opening is described and which includes providing a node location to which electrical connection is to be made; forming a conductive line adjacent the node location, the conductive line having a conductive top and sidewall surfaces; forming electrically insulative oxide in covering relation relative to the top surface of the conductive line; forming electrically insulative nitride sidewall spacers over the conductive sidewall surfaces, the nitride sidewall spacers projecting outwardly of the conductive line top conductive surface, the electrically insulative oxide positioned between the nitride sidewall spacers; forming an electrically insulative layer outwardly of the conductive line, and the node location; and etching a contact opening to the node location or the top surface through the electrically insulative layer substantially selective relative to the nitride sidewall spacers.

Abstract: A method for fabricating a periodic table group III-IV metal semiconductor metal field-effect transistor device is described. The disclosed fabrication arrangement uses a single metalization for ohmic and Schottky barrier contacts, employs selective etching with a permanent etch stop layer, employs a non-alloyed ohmic contact semiconductor layer and includes a permanent non photosensitive secondary mask element. The invention includes provisions for both an all optical lithographic process and a combined optical and electron beam lithographic process. These concepts are combined to provide a field-effect transistor device of reduced fabrication cost, increased dimensional accuracy and state-of-the-art electrical performance.

Abstract: An apparatus and method of processing a planar HEMT or FET semiconductor device is disclosed. An ohmic metalization is patterned on a semiconductor surface then lifted-off. A plurality of process control monitors are isolated, preferably using a wet etch process. The process control monitors preferably include transmission line patterns (TLMs) and etch field effect transistors The TLMs measure the contact resistance during the ohmic alloy process, and the etch field effect transistors monitor the drain current during the gate-recess step. The ohmic metalizations are then alloyed, and a gate is written using an electron beam. The semiconductor device is isolated, followed by application of an overlay which connects all resulting planar device connecting pads.

Abstract: A method for fabricating a compound semiconductor device includes the steps of depositing a first group III-V compound semiconductor layer on a surface of a Si substrate while holding a temperature of the Si substrate at a first temperature, depositing a second group III-V compound semiconductor layer on the first group III-V compound semiconductor layer while holding the temperature of the substrate at a second, higher temperature, and depositing a third group III-V compound semiconductor layer on the second group III-V compound semiconductor layer while holding the temperature of the substrate at a third temperature higher than said second temperature, wherein the second group III-V compound semiconductor layer contains Al.

Abstract: On a semiconductor substrate with an active layer, a first-stage recess groove is formed by photolithography and wet or dry etching. On the semiconductor substrate and the surface of the first-stage recess groove, a surface passivation film a crystalline material such as i-GaAs or an insulating film of, e.g., SiON, is formed. The surface passivation film on an area where an ohmic electrodes is to be formed is removed and the ohmic electrode is formed on the area by vapor deposition. Thereafter, in the first-stage recess groove, a second-stage recess groove is formed by photolithography and wet or dry etching. A gate electrode is formed on the second-stage recess groove by sputtering or the like.

Abstract: A Schottky electrode is formed on an n-type SiC base member with an Al--Ti alloy or by laying Al films and Ti films alternately, and a resulting structure is subjected to a heat treatment of 600.degree. C. to 1,200.degree. C. A p-type SiC layer may be formed around the Schottky junction so as to form a p-n junction with the n-type SiC base member.

Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration and then inverted onto a new permanent substrate member and an original surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Electrical characteristics including curve tracer electrical data originating in both dark and illuminated devices and devices of varying size and both depletion mode and enhancement mode operation are also disclosed. Fabrication of the device from gallium arsenide semiconductor material and utilization for infrared energy transducing in a number of differing electronic applications are also disclosed.

Abstract: A method of manufacturing a semiconductor device comprising a buried channel field effect transistor, which method comprises the formation of a stack of layers on a substrate (1) with an active semiconductor layer (13, 14) having a non-zero aluminium (Al) content, a semiconductor cap layer (4) without aluminium (Al), a masking layer (100) provided with a gate opening (51); a first selective etching step by means of a fluorine (F) compound in the cap layer (4) down to the upper surface (22) of the active layer (13, 14) on which a stopper layer (3) of aluminum fluoride (AlF.sub.

Abstract: Voltage breakdown resistant monocrystalline silicon carbide semiconductor devices are obtained by forming an amorphous silicon carbide termination region in a monocrystalline silicon carbide substrate, at a face thereof, adjacent and surrounding a silicon carbide device. The amorphous termination region is preferably formed by implanting electrically inactive ions, such as argon, into the substrate face at sufficient energy and dose to amorphize the substrate face. The device contact or contacts act as an implantation mask to provide a self-aligned termination region for the device. The terminated devices may exhibit voltage breakdown resistance which approaches the ideal value for silicon carbide.

Abstract: A silicon nitride film 2 is formed on a GaAs substrate 1 and patterned to selectively expose the GaAS substrate surface in uniformly distributed areas having a width of not greater than 1 .mu.m. A non-doped GaAs buffer layer is grown on the GaAs substrate to completely cover the silicon nitride film. Then, a semiconductor multilayer structure including a non-doped GaAs layer is formed on the non-doped GaAs buffer layer. When a semiconductor integrated circuit device is manufactured using this semiconductor substrate, side gate effect can be effectively reduced due to the existence of the silicon nitride pattern and the buffer layer.

Abstract: A power GaAs Schottky diode with a chemically deposited Ni barrier having a reverse breakdown voltage of 140 V, a forward voltage drop at 50 A/cm.sup.2 of 0.7 V at 23.degree. C., 0.5 V at 150.degree. C. and 0.3 V at 250.degree. C. and having a reverse leakage current density at -50 V of 0.1 .mu.A/cm.sup.2 at 23.degree. C. and 1 mA/cm.sup.2 at 150.degree. C. The high-voltage high-speed power Schottky semiconductor device is made by chemically depositing a nickel barrier electrode on a semiconductor which includes gallium arsenide and then etching the device to create side portions which are treated and protected to create the Schottky device.