Abstract: The invention includes providing gallium nitride material devices having backside vias and methods to form the devices. The devices include a gallium nitride material formed over a substrate, such as silicon. The device also may include one or more non-conducting layers between the substrate and the gallium nitride material which can aid in the deposition of the gallium nitride material. A via is provided which extends from the backside of the device through the non-conducting layer(s) to enable electrical conduction between an electrical contact deposited within the via and, for example, an electrical contact on the topside of the device. Thus, devices of the invention may be vertically conducting. Exemplary devices include laser diodes (LDs), light emitting diodes (LEDs), power rectifier diodes, FETs (e.g., HFETs), Gunn-effect diodes, and varactor diodes, among others.

Abstract: It is an object of the invention to solve a problem that a gate breakdown voltage and RF characteristics of a field effect transistor, which is provided with a double recess composed of a wide recess and a narrow recess, is not satisfactory. This problem results from the fact that a AlGaAs layer is exposed on a surface of the wide recess. The method for fabricating the field effect transistor comprise the steps of successively forming the first active layer, the first stopper layer, the second active layer, the second stopper layer and the third active layer on a substrate, forming a wide recess by etching a predetermined part of the third active layer till the second stopper is exposed, exposing the second active layer by removing the second stopper layer exposed on the bottom surface of the wide recess, and forming a narrow recess, which has a smaller aperture area than that of the wide recess, by etching a predetermined part of the exposed second active layer till the first stopper layer is exposed.

Abstract: The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1˜1016 to 1˜1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer. Otherwise, in the steps of manufacturing the high electron mobility field effect transistor, after a silicon nitride film has been formed on a GaAs buried layer in which a second recess is formed and in a region on the inside of a first recess formed in a GaAs contact layer, the GaAs buried layer is still heated.

Abstract: A method for depositing metal lines for semiconductor devices, in accordance with the present invention includes the step of providing a semiconductor wafer including a dielectric layer formed on the wafer. The dielectric layer has vias formed therein. The wafer is placed in a deposition chamber wherein the wafer has a first temperature achieved without preheating. A metal is deposited on the wafer which fills the vias wherein the metal depositing is initiated at a substantially same time as heating the wafer from the first temperature.

Abstract: In a semiconductor device, a gate electrode is formed by sequentially forming a Schottky metal film, a barrier metal film, and a low-resistance metal film from the lower side. The Schottky metal film or barrier metal film has a gap in a lower gate vertical portion. The gap is closed at its upper and lower portions. The overlayering low-resistance metal film does not extend into the lower gate vertical portion. A method for this semiconductor device is also disclosed.

Abstract: A method is described which forms an MOS transistor having a narrow diffusion region that is smaller than the diffusion region defined using photoresist in a conventional CMOS processing. In one embodiment, LOCOS can be used to form isolation (e.g., shallow trench) between active devices. A polysilicon layer is then deposited and doped either n+ or p+ selectively. The polysilicon layer is then patterned. Next, a dielectric layer and a refractory layer are deposited over he patterned polysilicon layer. Next, a contact hole with a high aspect ratio is defined in the oxide where the transistor will be formed. Angled implant of lightly-doped drain (LDD) regions or graft source/drain regions are formed on two opposite sides of the contact hole. The refractory metal layer is then removed. Spacers are then formed on opposite sidewall of the contact hole. A gate oxide layer is either thermally grown or deposited in the contact, before or after spacer formation.

Abstract: A method is provided for isotropically etching pairs of sidewall spacers to reduce the lateral thickness of each sidewall spacer. In an embodiment, first and second pairs of sidewall spacers are concurrently formed upon the opposed sidewall surfaces of respective first and second gate conductors. The first and second gate conductors are spaced laterally apart upon isolated first and second active areas of a semiconductor substrate, respectively. Advantageously, a single set of sidewall spacer pairs are used as masking structures during the formation of source and drain regions of an NMOS transistor and LDD areas of a PMOS transistor. That is, the n+ source/drain (“S/D”) implant is self-aligned to the outer lateral edge of the first pair of sidewall spacers prior to reducing the lateral thicknesses of the sidewall spacers. However, the p− LDD implant is self-aligned to the outer lateral edge of the second pair of sidewall spacers after the spacer thicknesses have been reduced.

Abstract: The invention is a Pseudomorphic transistor structure having a semiconductor layer having a 2DEG layer therein, a Schottky layer, a transition layer and an ohmic contact layer on the transition layer, wherein a double recess structure is disposed through the ohmic layer onto the transition layer in which one or two layers of InyGa1−yP are used as etch-stop layers to define the depth of the recess.

Abstract: The invention is a method for fabricating a pseudomorphic HEMT transistor structure with a semiconductor layer having a 2DEG layer therein, a Schottky layer, a transition layer, and an ohmic contact layer on the transition layer. A double recess structure is disposed through the ohmic layer into the transition layer in which one or two layers of INYGa1−YAs are used as etch-stop layers to define the depth of the recess(es).

Abstract: The silicon real estate consumed by a conventional Schottky diode is reduced in the present invention by forming the Schottky diode through a field oxide isolation region. Etching through the field oxide isolation region requires extra etch time which is provided by conventional etch steps that typically specify a 50-100% overetch during contact formation.

Abstract: A method of forming a gate electrode of a compound semiconductor device includes forming a first insulating film pattern having a first aperture, forming a second insulating film pattern having a second aperture consisting of inverse V-type on the first insulating film pattern, forming a T-type gate electrode by depositing a conductivity film on the entire structure, removing a second insulating film pattern, forming a insulating spacer on a pole sidewall by etching a first insulating film pattern, and forming an ohmic electrode of the source and drain by self-aligning method using T-type gate electrode as a mask. Thereby T-type gate electrode of materials such as refractory metals can be prevented to be deteriorate because of high annealing, as well as it is stably formed, by using an insulating film. Ohmic metal and gate electrodes formed by self-aligning method can be prevented an interconnection by forming an insulating film spacer between these electrodes.

Abstract: The present invention provides a method of fabricating a field-effect transistor comprising the steps of forming a masking layer having an opening therein on laminated compound semiconductor layers, removing a portion of the laminated layers using an etching solution acting through the opening and creating a gate-forming recess having sidewalls tapering in a direction away from the masking layer, filling the gate-forming recess with gate metal and forming a gate electrode, and forming a recess around the gate electrode.

Abstract: A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode.

Abstract: A vertical FET is fabricated by etching through a contact layer into a drift layer on a compound semiconductor substrate to form a plurality of mesas, each mesa having an upper surface and each adjacent pair of mesas defining therebetween a trench with sidewalls and a bottom. A conductive layer is conformally deposited over the plurality of mesas and the trenches and anisotropically etched to form contacts on the sidewalls of the trenches and depositing source contacts on the upper surfaces of the mesas and a drain contact on a reverse side of the substrate.

Abstract: A method of performing electron beam lithography on high resistivity substrates including forming semiconductor material on a high resistivity substrate and etching the semiconductor material to form mesas with electrically interconnecting bridges between the mesas. Semiconductor devices are formed in the mesas employing electron beam lithography and charges generated by the electron beam lithography are dispersed along the interconnecting bridges thereby preventing charge accumulation on the mesas. The bridges are removed by etching or sawing during die separation.

Abstract: A tungsten nitride (6b) is provided also on side surface of a tungsten (6c), to increase an area where the tungsten (6c) and the tungsten nitride (6b) are in contact with each other. On a gate insulating film (2), a polysilicon side wall (5) having high adhesive strength to the gate insulating film is disposed. The polysilicon side wall (5) is brought into a close contact with the tungsten nitride (6b) on the side surface of the tungsten (6c). With this structure improved is adhesive strength of a metal wire or a metal electrode which is formed on an insulating film of a semiconductor device.

Abstract: An improved GaAs MESFET includes a source contact ohmically coupled to a buffer layer or substrate to stabilize band bending at the interface of the active layer and buffer layer or substrate when an RF signal is applied to a gate electrode.

Abstract: An exemplary implementation of the present invention includes a method for forming conductive lines fabricated in a semiconductor device, the method comprising the steps of forming a first layer of patterned conductive lines, having substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines, formed by a double metal process, are recessed into a supporting material that has a substantially planar surface.

Abstract: An ohmic contact to a III-V semiconductor material is fabricated by dry etching a silicon nitride layer overlying the III-V semiconductor material with a chemical comprised of a group VI element. An ohmic metal layer is formed on the III-V semiconductor material after the silicon nitride layer is etched and before any exposure of the III-V semiconductor material to a chemical which etches the III-V semiconductor material or removes the group VI element.

Abstract: In a method for fabricating a semiconductor device, an insulating layer is formed on a semiconductor substrate, then a resist layer is formed on the insulating layer to have an opening therein. Next, removing the insulating layer at the bottom of the opening, then a reflow process is performed to the resist layer to have a curved surface thereon.

Abstract: The specification describes methods for making T-shaped metal gates for Schottky gate devices such as MESFETs and HEMTs. The method uses a bi-level photoresist technique to create a T-shaped feature for the gate structure. The metal gate is evaporated into the photoresist T-shaped feature and a lift-off process is used to remove unwanted metal. The photoresist is the dissolved away leaving the T-shaped gate. An important aspect of the process is the use of a plasma treatment of the first patterned resist level to harden it so that it is unaffected by the subsequent deposition and patterning of the second level resist.

Abstract: A superlattice buffer layer, an AlGaAs layer, an InGaAs layer, an AlGaAs layer, and an N+GaAs layer are successively deposited on a GaAs layer by epitaxial growth. Using an electron-beam resist as a mask, a patterning layer in the form of an SiO2 film is formed on the N+GaAs layer. Then, only the N+GaAs layer is selectively etched through an opening in the electron-beam resist with a water-diluted etchant which comprises a mixture of ammonia water and hydrogen peroxide solution which are mixed at a ratio of at least 1:4000, thereby forming a recess in the N+GaAs layer. Using the electron-beam resist also as a mask, a gate metal member serving as the base end of a T-shaped gate electrode is deposited on the AlGaAs layer in the recess. The width of an opening in the electron-beam resist determines the gate length.

Abstract: A method of manufacturing a semiconductor device comprising a buried channel field effect transistor, which method comprises the formation of a stack of layers on a substrate (1) with an active semiconductor layer (13, 14) having a non-zero aluminium (Al) content, a semiconductor cap layer (4) without aluminium (Al), a masking layer (100) provided with a gate opening (51); a first selective etching step by means of a fluorine (F) compound in the cap layer (4) down to the upper surface (22) of the active layer (13, 14) on which a stopper layer (3) of aluminum fluoride (AlF.sub.