Compound Semiconductor Patents (Class 438/572)
  • Patent number: 9947806
    Abstract: A Schottky barrier diode (semiconductor device) includes at least: a semiconductor substrate of an N type (first conductivity type); a semiconductor portion (first portion) of a P type (second conductivity type) opposite to the N type, the semiconductor portion being formed on a part of a one main surface side of the semiconductor substrate; a metal portion (second portion) with conductivity formed on the one main surface of the semiconductor substrate so as to be electrically connected to a part of the P type semiconductor portion; and a high resistance portion (third portion) formed so as to be electrically connected to a part of the P type semiconductor portion and to be in contact with a side surface and a bottom surface connected thereto of the P type semiconductor portion.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: April 17, 2018
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Masaaki Tomita
  • Patent number: 9450111
    Abstract: A Schottky barrier diode includes a substrate, a buffer layer formed on the substrate, an upper layer formed on the buffer layer, a first electrode layer formed on the upper layer as an anode of the Schottky barrier diode, a second electrode layer formed on the upper layer as a cathode of the Schottky barrier diode, and a first n-type doping region formed in the upper layer and under the first electrode layer, and contacting the first electrode layer. An edge of the first n-type doping region and an edge of the first electrode layer are separated by a first predetermined distance at a first direction at which the first electrode layer faces the second electrode layer.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: September 20, 2016
    Assignee: National Tsing Hua University
    Inventors: Yi-Wei Lian, Shuo-Hung Hsu
  • Patent number: 9378965
    Abstract: In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the III-Nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions. The method further comprises forming a blanket diffusion barrier over the gate dielectric layer, and then removing respective portions of the blanket diffusion barrier from the source and drain regions. Thereafter, gate dielectric is removed from the source and drain regions to substantially expose the source and drain regions. Then, ohmic contacts are formed by depositing contact metal in the source and drain regions. The method results in highly conductive source/drain contacts that are particularly suitable for power transistors, for example, III-Nitride transistors, such as GaN transistors.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: June 28, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Michael A. Briere
  • Patent number: 9246019
    Abstract: A method for forming a rectifier device is provided. The method forms a first layer on a substrate, a second layer is formed on the first layer and a photoresist layer is deposited on the second layer in which a plurality of trench patterns are formed. A plurality of trenches are formed in the first layer and the second layer by etching based on the trench patterns in the photoresist. The method then laterally etches the second layer to expose a corner portion of the first layer at mesas formed in between the two trenches. A portion of the second layer is preserved at an edge of the rectifier device.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: January 26, 2016
    Assignee: Diodes Incorporated
    Inventors: Lee Spencer Riley, Ze Rui Chen
  • Patent number: 9035323
    Abstract: Improved semiconductor devices are fabricated utilizing nickel gallide and refractory borides deposited onto a silicon carbide semiconductor substrate. Varying the deposition and annealing parameters of fabrication can provide a more thermally stable device that has greater barrier height and a low ideality. This improvement in the electrical properties allows use of Schottky barrier diodes in high power and high temperature applications. In one embodiment, a refractory metal boride layer is joined to a surface of a silicon carbide semiconductor substrate. The refractory metal boride layer is deposited on the silicon carbon semiconductor substrate at a temperature greater than 200° C. In another embodiment, a Schottky barrier diode is fabricated via deposition of nickel gallide on a SiC substrate.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: May 19, 2015
    Assignee: Youngstown State University
    Inventor: Tom Nelson Oder
  • Publication number: 20150129896
    Abstract: A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm. A method for manufacturing a semiconductor device according to the present invention includes: a step of forming a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, on the surface of a first conductive-type SiC semiconductor layer; and a step for heat treating the Schottky metal whilst the surface thereof is exposed, and structuring the junction of the SiC semiconductor layer to the Schottky metal to be planar, or to have recesses and protrusions of equal to or less than 5 nm.
    Type: Application
    Filed: June 5, 2013
    Publication date: May 14, 2015
    Applicant: ROHM CO., LTD.
    Inventor: Yasuhiro Kawakami
  • Patent number: 8987124
    Abstract: A silicon carbide substrate having a main face is prepared. By applying thermal oxidation to the main face of the silicon carbide substrate at a first temperature, an oxide film is formed on the main face. After the oxide film is formed, heat treatment is applied to the silicon carbide substrate at a second temperature higher than the first temperature. An opening exposing a portion of the main face is formed at the oxide film. A Schottky electrode is formed on the main face exposed by the opening.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomihito Miyazaki, Toru Hiyoshi
  • Patent number: 8969921
    Abstract: A semiconductor device is provided with: a GaN layer; an anode electrode that forms a Schottky junction with a Ga face of the GaN layer; and an InGaN layer positioned between at least a part of the anode electrode and the GaN layer.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Limited
    Inventors: Naoya Okamoto, Yuichi Minoura
  • Patent number: 8962462
    Abstract: Design constraints for a self protecting GaN HFET and in general any group III V HFET are described. The design constraints depend on the separation between the gate and the drain and the thickness of the buffer material between the channel layer and the substrate. In one embodiment the buffer region is thinned to provide a preferred breakdown location.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: February 24, 2015
    Assignee: HRL Laboratories, LLC
    Inventor: Brian Hughes
  • Patent number: 8956963
    Abstract: A Schottky barrier diode and fabricating method thereof are disclosed. A semiconductor substrate may have a first surface and a second surface positioned oppositely to be provided. Several trenches are formed on the first surface. Each trench has a sidewall with a first depth and a first bottom surface. An insulating material is formed on the first surface of the semiconductor substrate and on the sidewall and the first bottom surface of each trench, wherein the insulating material has a first thickness on the sidewall. The insulating material on the sidewall is patterned to define a second bottom surface having a second depth smaller than the first depth, and the removed portion of the insulating material on the sidewall has a second thickness smaller than the first thickness. Afterward, a contact metal layer is at least formed on the first surface between adjacent trenches.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: February 17, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Cheng-Tyng Yen, Kuan-Wei Chu, Lurng-Shehng Lee, Chwan-Ying Lee
  • Patent number: 8937319
    Abstract: A third insulating layer is formed in a periphery region of a substrate over a first surface (main surface) of the substrate so as to straddle a second semiconductor layer closest to a guard ring layer and a second semiconductor layer closest to the second semiconductor layer. In other words, the third insulating layer is formed to cover a portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers. Thereby, the third insulating layer electrically insulates the metal layer from the portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: January 20, 2015
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Yusuke Maeyama, Ryohei Osawa, Yoshitaka Araki, Yoshiyuki Watanabe
  • Patent number: 8933532
    Abstract: A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: January 13, 2015
    Assignee: Avogy, Inc.
    Inventors: Andrew Edwards, Hui Nie, Isik C. Kizilyalli, Richard J. Brown, David P. Bour, Linda Romano, Thomas R. Prunty
  • Patent number: 8901698
    Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: December 2, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Taku Horii, Tomihito Miyazaki, Makoto Kiyama
  • Patent number: 8895422
    Abstract: Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 25, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Roland Rupp, Thomas Gutt, Michael Treu
  • Patent number: 8872156
    Abstract: A group III nitride semiconductor light emitting device includes an n-type cladding layer and a p-type cladding layer on a primary surface of a substrate, the c-axes of which tilt relative to the normal axis of the primary surface of the substrate. The p-type cladding layer is doped with a p-type dopant providing an acceptor level, and the p-type cladding layer contains an n-type impurity providing a donor level. An active layer is disposed between the n-type cladding layer and the p-type cladding layer. The concentration of the p-type dopant is greater than that of the n-type impurity. The difference (E(BAND)?E(DAP)) between the energy E(BAND) of a band-edge emission peak value in the photoluminescence spectrum of the p-type cladding layer and the energy E(DAP) of a donor-acceptor pair emission peak value in the photoluminescence spectrum is not more than 0.42 electron volts.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takumi Yonemura, Takashi Kyono, Yohei Enya
  • Patent number: 8866193
    Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT).
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: October 21, 2014
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8859354
    Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a quantum well layer on the semiconductor substrate. The method also includes forming a potential energy barrier layer on the semiconductor substrate, and forming an isolation structure to isolate different transistor regions. Further, the method includes patterning the transistor region to form trenches by removing portions of the quantum well layer and the potential energy barrier layer corresponding to a source region and a drain region, and filling trenches with a semiconductor material to form a source and a drain. Further, the method also includes forming a gate structure on a portion of the quantum well layer and the potential energy barrier layer corresponding to a gate region.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Manufacturing International Corp
    Inventor: Deyuan Xiao
  • Publication number: 20140264714
    Abstract: The invention provides a power semiconductor device including an aluminum nitride single crystalline substrate, wherein the dislocation density of the substrate is less than about 105 cm?2 and the Full Width Half Maximum (FWHM) of the double axis rocking curve for the (002) and (102) crystallographic planes is less than about 200 arcsec; and a power semiconductor structure comprising at least one doped AlxGa1?xN layer overlying the aluminum nitride single crystalline substrate.
    Type: Application
    Filed: March 13, 2014
    Publication date: September 18, 2014
    Applicant: HEXATECH, INC.
    Inventors: Baxter Moody, Seiji Mita, Jinqiao Xie
  • Publication number: 20140231827
    Abstract: A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.
    Type: Application
    Filed: December 26, 2013
    Publication date: August 21, 2014
    Applicants: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yukihiko WATANABE, Sachiko AOI, Masahiro SUGIMOTO, Akitaka SOENO, Shinichiro MIYAHARA
  • Patent number: 8809987
    Abstract: Structures, devices and methods are provided for creating heterojunction AlGaN/GaN metal two-dimensional electron gas (2DEG) tunnel-junction field-effect transistors (TJ-FET). In one aspect, metal-2DEG Schottky tunnel junctions can be employed in group III-Nitride field-effect devices that enable normally-off operation, large breakdown voltage, low leakage current, and high on/off current ratio. As a further advantage, AlGaN/GaN metal-2DEG TJ-FETs are disclosed that can be fabricated in a lateral configuration and/or a vertical configuration. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: August 19, 2014
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Jing Chen, Li Yuan, Hongwei Chen, Chunhua Zhou
  • Patent number: 8778788
    Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial structure including a first III-nitride epitaxial layer coupled to the first side of the III-nitride substrate and a plurality of III-nitride regions of a second conductivity type. The plurality of III-nitride regions have at least one III-nitride epitaxial region of the first conductivity type between each of the plurality of III-nitride regions. The semiconductor structure further includes a first metallic structure electrically coupled to one or more of the plurality of III-nitride regions and the at least one III-nitride epitaxial region. A Schottky contact is created between the first metallic structure and the at least one III-nitride epitaxial region.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: July 15, 2014
    Assignee: Avogy, Inc.
    Inventors: Andrew P. Edwards, Hui Nie, Isik C. Kizilyalli, Linda Romano, David P. Bour, Richard J. Brown, Thomas R. Prunty
  • Patent number: 8779439
    Abstract: The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n? epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n? epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n? epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: July 15, 2014
    Assignee: Hyundai Motor Company
    Inventors: Kyoung Kook Hong, Jong Seok Lee
  • Patent number: 8772144
    Abstract: A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: July 8, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: TingGang Zhu, Anup Bhalla, Ping Huang, Yueh-se Ho
  • Publication number: 20140183558
    Abstract: A schottky barrier diode includes: an n? type epitaxial layer that is disposed at a first surface of an n+ type silicon carbide substrate; a plurality of n type pillar areas that are disposed at the inside of the n? type epitaxial layer and that are disposed at a first portion of the first surface of the n+ type silicon carbide substrate; a p type area that is disposed at the inside of the n? type epitaxial layer and that is extended in a direction perpendicular to the n type pillar areas; a plurality of p+ areas in which the n? type epitaxial layer is disposed at a surface thereof and that are separated from the n type pillar areas and the p type area; a schottky electrode that is disposed on the n? type epitaxial layer and the p+ areas; and an ohmic electrode that is disposed at a second surface of the n+ type silicon carbide substrate.
    Type: Application
    Filed: December 5, 2013
    Publication date: July 3, 2014
    Applicant: HYUNDAI MOTOR COMPANY
    Inventors: Jong Seok LEE, Kyoung-Kook HONG, Dae Hwan CHUN, Youngkyun JUNG
  • Patent number: 8765523
    Abstract: A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main surface, and forming a Schottky electrode in contact with the main surface that has been exposed by removing the oxide film.
    Type: Grant
    Filed: November 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda
  • Patent number: 8766395
    Abstract: A device includes a Schottky barrier formed by a metal-semiconductor junction between a semiconductor nanowire and a metal contact. The metal contact at least partly encloses a circumferential area of each nanowire along the length thereof. The nanowire includes a low doped region that is part of the metal-semiconductor junction. The device can be fabricated using a method where two different growth modes are used, the first step including axial growth from a substrate giving a suitable template for formation of the metal-semiconductor junction, and the second step including radial growth enabling control of the doping levels in the low doped region.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: July 1, 2014
    Assignee: Qunano AB
    Inventor: Steven Konsek
  • Publication number: 20140138698
    Abstract: A semiconductor device includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. The first portion of the first electrode has a lower Schottky potential barrier than the second portion of the first electrode. A second electrode is in contact with the first active layer.
    Type: Application
    Filed: November 16, 2012
    Publication date: May 22, 2014
    Applicant: Vishay General Semiconductor LLC
    Inventor: Yih-Yin Lin
  • Publication number: 20140138697
    Abstract: A semiconductor device such as a Schottky diode is provided which includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer.
    Type: Application
    Filed: November 16, 2012
    Publication date: May 22, 2014
    Applicant: Vishay General Semiconductor LLC
    Inventor: Yih-Yin Lin
  • Publication number: 20140103357
    Abstract: The disclosed technology relates to a device including a diode. In one aspect, the device includes a lower group III metal nitride layer and an upper group III metal nitride layer and a heterojunction formed therebetween, where the heterojunction extends horizontally and is configured to form a two-dimensional electron gas (2DEG) that is substantially confined in a vertical direction and within the lower group III metal nitride layer. The device additionally includes a cathode forming an ohmic contact with the upper group III metal nitride layer. The device additionally includes an anode, which includes a first portion that forms a Schottky barrier contact with the upper group III metal nitride layer, and a second portion that is separated vertically from the upper group III metal nitride layer by a layer of dielectric material.
    Type: Application
    Filed: October 17, 2013
    Publication date: April 17, 2014
    Applicant: IMEC
    Inventors: STEFAAN DECOUTERE, Nicolo Ronchi
  • Patent number: 8697467
    Abstract: Compound semiconductor devices and methods of doping compound semiconductors are provided. Embodiments of the invention provide post-deposition (or post-growth) doping of compound semiconductors, enabling nanoscale compound semiconductor devices including diodes and transistors. In one method, a self-limiting monolayer technique with an annealing step is used to form shallow junctions. By forming a sulfur monolayer on a surface of an InAs substrate and performing a thermal annealing to drive the sulfur into the InAs substrate, n-type doping for InAs-based devices can be achieved. The monolayer can be formed by surface chemistry reactions or a gas phase deposition of the dopant. In another method, a gas-phase technique with surface diffusion is used to form doped regions. By performing gas-phase surface diffusion of Zn into InAs, p-type doping for InAs-based devices can be achieved.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: April 15, 2014
    Assignee: The Regents of the University of California
    Inventors: Ali Javey, Alexandra C. Ford, Johnny C. Ho
  • Publication number: 20140092637
    Abstract: A compound semiconductor device includes: a compound semiconductor layered structure; a gate electrode formed above the compound semiconductor layered structure; a first protective insulating film that covers a surface of the compound semiconductor layered structure and is made of silicon nitride as a material; a second protective insulating film that covers the gate electrode on the first protective insulating film and is made of silicon oxide as a material; and a third protective insulating film that contains silicon oxynitride and is formed between the first protective insulating film and the second protective insulating film.
    Type: Application
    Filed: August 27, 2013
    Publication date: April 3, 2014
    Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITED
    Inventors: Yuichi Minoura, Yoshitaka WATANABE
  • Patent number: 8685848
    Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: April 1, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yoshinori Matsuno, Yoichiro Tarui
  • Patent number: 8679954
    Abstract: A schottky diode includes a SiC substrate which has a first surface and a second surface facing away from the first surface, a semiconductor layer which is formed on the first surface of the SiC substrate, a schottky electrode which is in contact with the semiconductor layer, and an ohmic electrode which is in contact with the second surface of the SiC substrate. The first surface of the SiC substrate is a (000-1) C surface, upon which the semiconductor layer is formed.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: March 25, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Shingo Ohta, Tatsuya Kiriyama, Takashi Nakamura, Yuji Okamura
  • Publication number: 20140061671
    Abstract: A wide gap semiconductor device includes a substrate and a Schottky electrode. The substrate formed of a wide gap semiconductor material has a main face, and includes a first-conductivity-type region and a second-conductivity-type region. The Schottky electrode is arranged adjoining the main face of the substrate. At the substrate, there is foamed a trench having a side face continuous with the main face and a bottom continuous with the side face. The Schottky electrode adjoins the first-conductivity-type region at the side face of the trench and the main face, and adjoins the second-conductivity-type region at the bottom of the trench. The side face of the trench is inclined relative to the main face of the substrate.
    Type: Application
    Filed: July 25, 2013
    Publication date: March 6, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Takeyoshi Masuda, Toru Hiyoshi
  • Publication number: 20140061670
    Abstract: A wide gap semiconductor device has a substrate and a Schottky electrode. The substrate is made of a wide gap semiconductor material and has a first conductivity type. The Schottky electrode is arranged on the substrate to be in contact therewith and is made of a single material. The Schottky electrode includes a first region having a first barrier height and a second region having a second barrier height higher than the first barrier height. The second region includes an outer peripheral portion of the Schottky electrode. Thus, a wide gap semiconductor device capable of achieving less leakage current and a method for manufacturing the same can be provided.
    Type: Application
    Filed: July 22, 2013
    Publication date: March 6, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Wada, Kenji Kanbara
  • Publication number: 20140054680
    Abstract: A method of forming a group III nitride semiconductor comprises: preparing a group III nitride semiconductor which contains a p-type dopant or an n-type dopant; and performing a treatment of the group III nitride semiconductor by using a reducing gas and a nitrogen source gas to form a conductive group III nitride semiconductor. The treatment includes performing a first treatment of the group III nitride semiconductor by using a first treatment gas including the reducing gas and the nitrogen source gas, which are supplied to a treatment apparatus at a first flow rate and a second flow rate, respectively, and after the first treatment is performed, performing a second treatment of the group III nitride semiconductor by using a second treatment gas including the reducing gas and the nitrogen source gas, which are supplied to the treatment apparatus at a third flow rate and a fourth flow rate, respectively.
    Type: Application
    Filed: August 21, 2013
    Publication date: February 27, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shin HASHIMOTO, Takao NAKAMURA, Hiroshi AMANO
  • Publication number: 20140048815
    Abstract: A Schottky barrier diode (SBD) is disclosed, which includes: a gallium nitride (GaN) layer, formed on a substrate; an aluminum gallium nitride (AlGaN), formed on the GaN layer; an insulation layer, formed on the AlGaN layer; an anode conducive layer, formed on the insulation layer, wherein Schottky contact is formed between a part of the anode conductive layer and the AlGaN layer or between a part of the anode conductive layer and the GaN layer, and another part of the anode conductive layer is separated from the AlGaN layer by the insulation layer; and a cathode conductive layer, formed on the AlGaN layer, wherein an ohmic contact is formed between the cathode conductive layer and the GaN layer or between the cathode conductive layer and the AlGaN layer, and wherein the anode conductive layer is not directly connected to the cathode conductive layer.
    Type: Application
    Filed: August 20, 2012
    Publication date: February 20, 2014
    Inventors: Tsung-Yi Huang, Chien-Wei Chiu, Chih-Fang Huang, Tsung-Yu Yang
  • Patent number: 8652949
    Abstract: A method of manufacturing a semiconductor wafer, which includes: a semiconductor substrate made of silicon and having both a central area and an outer periphery area; and a compound semiconductor layer made of a nitride-based semiconductor and formed on the semiconductor substrate, the method comprising: forming a growth inhibition layer to inhibit the compound semiconductor layer from growing on a tapered part provided in the outer periphery area of the semiconductor substrate; and growing the compound semiconductor layer on at least the central area of the semiconductor substrate, after the growth inhibition layer has been formed.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: February 18, 2014
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Ken Sato
  • Publication number: 20140027877
    Abstract: A manufacturing method for antenna switching circuit includes the following steps of: providing a GaAs wafer, which includes a capping layer; disposing an isolation layer to the GaAs wafer for forming a device area; and disposing a gate metal on the capping layer within the device area, wherein an interface between the gate metal and the capping layer forms a Schottky contact, and the Schottky contact is parallel connected with an impedance. The present invention also discloses a semiconductor structure for antenna switching circuit.
    Type: Application
    Filed: May 3, 2013
    Publication date: January 30, 2014
    Applicant: MAXTEK TECHNOLOGY CO., LTD.
    Inventors: Ke-Kung LIAO, Tung-Sheng CHANG, Chun-Yen KU, Shih-Yu CHEN
  • Patent number: 8603903
    Abstract: In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta2O5 under a gate electrode.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: December 10, 2013
    Assignee: Fujitsu Limited
    Inventors: Masahito Kanamura, Toshihide Kikkawa
  • Patent number: 8557644
    Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT).
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: October 15, 2013
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Publication number: 20130267085
    Abstract: A method for fabricating a metal structure for a semiconductor device is disclosed. The method begins with providing a wafer with a current input contact and current output contact. Remaining steps include loading the wafer into a deposition apparatus, depositing a layer of metal onto a predefined metal region, removing the wafer from the deposition apparatus, and performing an ex-situ passivation process. If additional layers are to be deposited and passivated, the steps are repeated until a predetermined number of layers of metal are deposited onto the predefined metal region. The predefined metal region is a gate metal opening if the metal structure is a gate contact for a field effect transistor. The ex-situ passivation process is achievable through oxidation or nitridation of the wafer using either oxygen plasma or a nitrogen plasma, respectively. Alternately, oxidation is also achievable through exposing the wafer to air at an elevated temperature.
    Type: Application
    Filed: March 28, 2013
    Publication date: October 10, 2013
    Inventors: Liping Daniel Hou, Chuanxin Lian
  • Publication number: 20130256680
    Abstract: The present invention discloses a vertical semiconductor device and a manufacturing method thereof. The vertical semiconductor device includes: a substrate having a first surface and a second surface, the substrate including a conductive array formed by multiple conductive plugs through the substrate; a semiconductor layer formed on the first surface, the semiconductor layer having a third surface and a fourth surface, wherein the fourth surface faces the first surface; a first electrode formed on the third surface; and a second electrode formed on the second surface for electrically connecting to the conductive array.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Chien-Wei Chiu, Tsung-Yi Huang
  • Patent number: 8513674
    Abstract: A method of manufacturing of a semiconductor device (101) includes: a fine pattern forming step of forming p-type impurity regions (3, 4) and surface ohmic contact electrodes (5) using a stepper, after forming an N-type epitaxial layer (2) on a SiC single-crystal substrate (1); a protective film planarizing step of forming a protective film so as to cover the surface ohmic contact electrodes (5) and performing planarization of the protective film; a substrate thinning step of thinning the SiC single-crystal substrate (1); a backside ohmic contact electrode forming step of forming a backside ohmic contact electrode (7) on the SiC single-crystal substrate (1); a surface Schottky contact electrode forming step of forming a Schottky metal portion (8) connected to the p-type impurity regions (3, 4) and the surface ohmic contact electrodes (5); and a step of forming a surface pad electrode (9) that covers the Schottky metal portion (8).
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: August 20, 2013
    Assignee: Showa Denko K.K.
    Inventors: Akihiko Sugai, Yasuyuki Sakaguchi
  • Patent number: 8501557
    Abstract: A method of manufacturing a nitride semiconductor device including: forming a nitride semiconductor layer over a substrate wherein the nitride semiconductor layer has a 2DEG channel inside; forming a drain electrode in ohmic contact with the nitride semiconductor layer and a source electrode spaced apart from the drain electrode, in Schottky contact with the nitride semiconductor layer, wherein the source electrode has an ohmic pattern in ohmic contact with the nitride semiconductor layer inside; forming a dielectric layer on the nitride semiconductor layer between the drain electrode and the source electrode and on at least a portion of the source electrode; and forming a gate electrode on the dielectric layer to be spaced apart from the drain electrode, wherein a portion of the gate electrode is formed on the dielectric layer over a drain-side edge portion of the source electrode.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: August 6, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Woo Chul Jeon, Ki Yeol Park, Young Hwan Park
  • Publication number: 20130193449
    Abstract: Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.
    Type: Application
    Filed: March 14, 2013
    Publication date: August 1, 2013
    Applicant: Infineon Technologies Austria AG
    Inventor: Infineon Technologies Austria AG
  • Publication number: 20130196494
    Abstract: A target made of a metal material is sputtered to form a metal film on a silicon carbide wafer. At this time, the metal film is formed under a condition that an incident energy of incidence, on the silicon carbide wafer, of the metal material sputtered from the target and a sputtering gas flowed in through a gas inlet port is lower than a binding energy of silicon carbide, and more specifically lower than 4.8 eV. For example, the metal film is formed while a high-frequency voltage applied between a cathode and an anode is set to be equal to or higher than 20V and equal to or lower than 300V.
    Type: Application
    Filed: November 9, 2012
    Publication date: August 1, 2013
    Inventors: Daisuke CHIKAMORI, Yasuhiko NISHIO, Naoki YUTANI
  • Patent number: 8466051
    Abstract: A method for fabricating a Schottky device includes the following sequences. First, a substrate with a first conductivity type is provided and an epitaxial layer with the first conductivity type is grown on the substrate. Then, a patterned dielectric layer is formed on the epitaxial layer, and a metal silicide layer is formed on a surface of the epitaxial layer. A dopant source layer with a second conductivity type is formed on the metal silicide layer, followed by applying a thermal drive-in process to diffuse the dopants inside the dopant source layer into the epitaxial layer. Finally, a conductive layer is formed on the metal silicide layer.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: June 18, 2013
    Assignee: Anpec Electronics Corporation
    Inventors: Yung-Fa Lin, Shou-Yi Hsu, Meng-Wei Wu, Main-Gwo Chen, Chia-Hao Chang, Chia-Wei Chen
  • Publication number: 20130140607
    Abstract: Disclosed are structures and methods related to metallization of a doped gallium arsenide (GaAs) layer. In some embodiments, such metallization can include a tantalum nitride (TaN) layer formed on the doped GaAs layer, and a metal layer formed on the TaN layer. Such a combination can yield a Schottky diode having a low turn-on voltage, with the metal layer acting as an anode and an electrical contact connected to the doped GaAs layer acting as a cathode. Such a Schottky diode can be utilized in applications such as radio-frequency (RF) power detection, reference-voltage generation using a clamp diode, and photoelectric conversion. In some embodiments, the low turn-on Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.
    Type: Application
    Filed: November 15, 2012
    Publication date: June 6, 2013
    Applicant: Skywork Solutions, Inc.
    Inventor: Skywork Solutions, Inc.
  • Patent number: 8450826
    Abstract: Disclosed herein is a nitride based semiconductor device. There is provided a nitride based semiconductor device including a base substrate; a semiconductor layer disposed on the base substrate; and an electrode structure disposed on the semiconductor layer, wherein the electrode structure includes: a first electrode ohmic-contacting the semiconductor layer; a ohmic contact unit ohmic-contacting the semiconductor layer and spaced apart from the first electrode; and a schottky contact unit schottky-contacting the semiconductor layer and covering the ohmic contact unit.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: May 28, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Younghwan Park, Kiyeol Park, Woochul Jeon