Abstract: Provided are a multilayer structure in which crystal defects due to stress concentration in a semiconductor layer caused by an insulator film are prevented and a semiconductor device using the multilayer structure, the multilayer structure and the semiconductor device that are particularly useful for power devices. A multilayer structure in which an insulator film is arranged on a part of a semiconductor film, wherein the semiconductor film has a corundum structure and contains a crystalline oxide semiconductor containing one or two or more metals selected from groups 9 and 13 of the periodic table, and wherein the insulator film has a taper angle of 20° or less.

Abstract: An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of which may include aluminum silicon oxide, and an upper active pattern on the buffer structure.

Abstract: A method includes forming a semiconductor device, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure consisting essentially of an elemental metal that is not copper from a physically exposed conductive surface located at a bottom of the via portion of the integrated line-and-via cavity without filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that includes copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity.

Abstract: The invention provides a laser rapid fabrication method for flexible gallium nitride (GaN) photodetector which comprises the following steps: (1) bonding a flexible substrate to a GaN epitaxial wafer; (2) adjusting the focal plane position of a light beam, and ensuring that the light beam is incident from the side of a GaN epitaxial wafer substrate; (3) enabling the light beam to perform scanning irradiation from the edge of a sample structure obtained in the step (1); (4) adjusting the process parameters, and scanning irradiation in the reverse direction along the path in the step (3); (5) remove the original rigid transparent substrate of the epitaxial wafer to obtain a Ga metal nanoparticle/GaN film/flexible substrate structure; and (6) preparing interdigital electrodes on the surfaces of the Ga metal nanoparticles obtained in the step (5).

Abstract: The present disclosure relates to a method of forming a transistor device. The method may be performed by forming a gate structure onto a semiconductor substrate and forming a source/drain recess within the semiconductor substrate adjacent to a side of the gate structure. One or more strain inducing materials are formed within the source/drain recess. The one or more strain inducing materials include a strain inducing component with a strain inducing component concentration profile that continuously decreases from a bottommost surface of the one or more strain inducing materials to a position above the bottommost surface. The bottommost surface contacts the semiconductor substrate.

Abstract: An object of the present invention is to provide a Schottky barrier diode less liable to cause dielectric breakdown due to concentration of an electric field. A Schottky barrier diode according to this disclosure includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and provided on the semiconductor substrate, an anode electrode 40 brought into Schottky contact with the drift layer, a cathode electrode brought into ohmic contact with the semiconductor substrate, an insulating layer provided on the drift layer so as to surround the anode electrode in a plan view, and a semiconductor layer provided on a surface of a part of the drift layer that is positioned between the anode electrode and the insulating layer and on the insulating layer. The semiconductor layer has a conductivity type opposite to that of the drift layer.

Abstract: A bidirectional blocking monolithic heterogeneous integrated Cascode-structure field effect transistor, which mainly solves a problem that the existing monolithic heterogeneous integrated Cascode-structure field effect transistor has no reverse blocking characteristic. The field effect transistor includes a substrate, a GaN buffer layer, an AlGaN barrier layer and a SiN isolation layer, wherein an isolation groove is etched in the middle of the SiN isolation layer, a Si active layer is printed on the SiN isolation layer on one side of the isolation groove so as to prepare a Si metal oxide semiconductor field effect transistor, and a GaN high-electron-mobility transistor is prepared on the other side of the isolation groove, and a drain electrode of the GaN high-electron-mobility transistor is in Schottky contact with the AlGaN barrier layer to form a bidirectional blocking monolithic heterogeneous integrated Cascode-structure field effect transistor.

Abstract: The present invention relates to a compound that is capable of being used in thin-film deposition using vapor deposition. Particularly, the present invention relates to a rare earth compound, which is capable of being applied to atomic layer deposition (ALD) or chemical vapor deposition (CVD) and which has excellent thermal stability and reactivity, a rare earth precursor including the same, a method of manufacturing the same, and a method of forming a thin film using the same.

Abstract: A Schottky barrier diode (semiconductor device) includes at least: a semiconductor substrate of an N type (first conductivity type); a semiconductor portion (first portion) of a P type (second conductivity type) opposite to the N type, the semiconductor portion being formed on a part of a one main surface side of the semiconductor substrate; a metal portion (second portion) with conductivity formed on the one main surface of the semiconductor substrate so as to be electrically connected to a part of the P type semiconductor portion; and a high resistance portion (third portion) formed so as to be electrically connected to a part of the P type semiconductor portion and to be in contact with a side surface and a bottom surface connected thereto of the P type semiconductor portion.

Abstract: A Schottky barrier diode includes a substrate, a buffer layer formed on the substrate, an upper layer formed on the buffer layer, a first electrode layer formed on the upper layer as an anode of the Schottky barrier diode, a second electrode layer formed on the upper layer as a cathode of the Schottky barrier diode, and a first n-type doping region formed in the upper layer and under the first electrode layer, and contacting the first electrode layer. An edge of the first n-type doping region and an edge of the first electrode layer are separated by a first predetermined distance at a first direction at which the first electrode layer faces the second electrode layer.

Abstract: In one embodiment, a method for fabricating a III-Nitride transistor on a III-Nitride semiconductor body is disclosed. The method comprises etching dielectric trenches in a field dielectric overlying gate, source, and drain regions of the III-Nitride semiconductor body, and thereafter forming a gate dielectric over the gate, source and drain regions. The method further comprises forming a blanket diffusion barrier over the gate dielectric layer, and then removing respective portions of the blanket diffusion barrier from the source and drain regions. Thereafter, gate dielectric is removed from the source and drain regions to substantially expose the source and drain regions. Then, ohmic contacts are formed by depositing contact metal in the source and drain regions. The method results in highly conductive source/drain contacts that are particularly suitable for power transistors, for example, III-Nitride transistors, such as GaN transistors.

Abstract: A method for forming a rectifier device is provided. The method forms a first layer on a substrate, a second layer is formed on the first layer and a photoresist layer is deposited on the second layer in which a plurality of trench patterns are formed. A plurality of trenches are formed in the first layer and the second layer by etching based on the trench patterns in the photoresist. The method then laterally etches the second layer to expose a corner portion of the first layer at mesas formed in between the two trenches. A portion of the second layer is preserved at an edge of the rectifier device.

Abstract: Improved semiconductor devices are fabricated utilizing nickel gallide and refractory borides deposited onto a silicon carbide semiconductor substrate. Varying the deposition and annealing parameters of fabrication can provide a more thermally stable device that has greater barrier height and a low ideality. This improvement in the electrical properties allows use of Schottky barrier diodes in high power and high temperature applications. In one embodiment, a refractory metal boride layer is joined to a surface of a silicon carbide semiconductor substrate. The refractory metal boride layer is deposited on the silicon carbon semiconductor substrate at a temperature greater than 200° C. In another embodiment, a Schottky barrier diode is fabricated via deposition of nickel gallide on a SiC substrate.

Abstract: A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm. A method for manufacturing a semiconductor device according to the present invention includes: a step of forming a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, on the surface of a first conductive-type SiC semiconductor layer; and a step for heat treating the Schottky metal whilst the surface thereof is exposed, and structuring the junction of the SiC semiconductor layer to the Schottky metal to be planar, or to have recesses and protrusions of equal to or less than 5 nm.

Abstract: A silicon carbide substrate having a main face is prepared. By applying thermal oxidation to the main face of the silicon carbide substrate at a first temperature, an oxide film is formed on the main face. After the oxide film is formed, heat treatment is applied to the silicon carbide substrate at a second temperature higher than the first temperature. An opening exposing a portion of the main face is formed at the oxide film. A Schottky electrode is formed on the main face exposed by the opening.

Abstract: A semiconductor device is provided with: a GaN layer; an anode electrode that forms a Schottky junction with a Ga face of the GaN layer; and an InGaN layer positioned between at least a part of the anode electrode and the GaN layer.

Abstract: Design constraints for a self protecting GaN HFET and in general any group III V HFET are described. The design constraints depend on the separation between the gate and the drain and the thickness of the buffer material between the channel layer and the substrate. In one embodiment the buffer region is thinned to provide a preferred breakdown location.

Abstract: A Schottky barrier diode and fabricating method thereof are disclosed. A semiconductor substrate may have a first surface and a second surface positioned oppositely to be provided. Several trenches are formed on the first surface. Each trench has a sidewall with a first depth and a first bottom surface. An insulating material is formed on the first surface of the semiconductor substrate and on the sidewall and the first bottom surface of each trench, wherein the insulating material has a first thickness on the sidewall. The insulating material on the sidewall is patterned to define a second bottom surface having a second depth smaller than the first depth, and the removed portion of the insulating material on the sidewall has a second thickness smaller than the first thickness. Afterward, a contact metal layer is at least formed on the first surface between adjacent trenches.

Abstract: A third insulating layer is formed in a periphery region of a substrate over a first surface (main surface) of the substrate so as to straddle a second semiconductor layer closest to a guard ring layer and a second semiconductor layer closest to the second semiconductor layer. In other words, the third insulating layer is formed to cover a portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers. Thereby, the third insulating layer electrically insulates the metal layer from the portion of the first semiconductor layer, which is exposed to the first surface (main surface) of the substrate and which is between the second semiconductor layers.

Abstract: A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.

Abstract: A method for manufacturing a Schottky barrier diode includes the following steps. First, a GaN substrate is prepared. A GaN layer is formed on the GaN substrate. A Schottky electrode including a first layer made of Ni or Ni alloy and in contact with the GaN layer is formed. The step of forming the Schottky electrode includes a step of forming a metal layer to serve as the Schottky electrode and a step of heat treating the metal layer. A region of the GaN layer in contact with the Schottky electrode has a dislocation density of 1×108 cm?2 or less.

Abstract: Production of an integrated circuit including an electrical contact on SiC is disclosed. One embodiment provides for production of an electrical contact on an SiC substrate, in which a conductive contact is produced on a boundary surface of the SiC substrate by irradiation and absorption of a laser pulse on an SiC substrate.

Abstract: A group III nitride semiconductor light emitting device includes an n-type cladding layer and a p-type cladding layer on a primary surface of a substrate, the c-axes of which tilt relative to the normal axis of the primary surface of the substrate. The p-type cladding layer is doped with a p-type dopant providing an acceptor level, and the p-type cladding layer contains an n-type impurity providing a donor level. An active layer is disposed between the n-type cladding layer and the p-type cladding layer. The concentration of the p-type dopant is greater than that of the n-type impurity. The difference (E(BAND)?E(DAP)) between the energy E(BAND) of a band-edge emission peak value in the photoluminescence spectrum of the p-type cladding layer and the energy E(DAP) of a donor-acceptor pair emission peak value in the photoluminescence spectrum is not more than 0.42 electron volts.

Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group semiconductor device may be a III-nitride high electron mobility transistor (HEMT).

Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate, and forming a quantum well layer on the semiconductor substrate. The method also includes forming a potential energy barrier layer on the semiconductor substrate, and forming an isolation structure to isolate different transistor regions. Further, the method includes patterning the transistor region to form trenches by removing portions of the quantum well layer and the potential energy barrier layer corresponding to a source region and a drain region, and filling trenches with a semiconductor material to form a source and a drain. Further, the method also includes forming a gate structure on a portion of the quantum well layer and the potential energy barrier layer corresponding to a gate region.

Abstract: The invention provides a power semiconductor device including an aluminum nitride single crystalline substrate, wherein the dislocation density of the substrate is less than about 105 cm?2 and the Full Width Half Maximum (FWHM) of the double axis rocking curve for the (002) and (102) crystallographic planes is less than about 200 arcsec; and a power semiconductor structure comprising at least one doped AlxGa1?xN layer overlying the aluminum nitride single crystalline substrate.

Abstract: A method of manufacturing a semiconductor device includes forming an ohmic electrode in a first area on one of main surfaces of a silicon carbide layer, siliciding the ohmic electrode, and forming a Schottky electrode in a second area on the one of the main surfaces of the silicon carbide layer with self alignment. The second area is exposed where the ohmic electrode is not formed.

Abstract: Structures, devices and methods are provided for creating heterojunction AlGaN/GaN metal two-dimensional electron gas (2DEG) tunnel-junction field-effect transistors (TJ-FET). In one aspect, metal-2DEG Schottky tunnel junctions can be employed in group III-Nitride field-effect devices that enable normally-off operation, large breakdown voltage, low leakage current, and high on/off current ratio. As a further advantage, AlGaN/GaN metal-2DEG TJ-FETs are disclosed that can be fabricated in a lateral configuration and/or a vertical configuration. Further non-limiting embodiments are provided that illustrate the advantages and flexibility of the disclosed structures.

Abstract: The present invention provides a silicon carbide Schottky-barrier diode device and a method for manufacturing the same. The silicon carbide Schottky bather diode device includes a primary n? epitaxial layer, an n+ epitaxial region, and a Schottky metal layer. The primary n? epitaxial layer is deposited on an n+ substrate joined with an ohmic metal layer at an undersurface thereof. The n+ epitaxial region is formed by implanting n+ ions into a central region of the primary n? epitaxial layer. The Schottky metal layer is deposited on the n+ epitaxial layer.

Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure also includes a III-nitride epitaxial structure including a first III-nitride epitaxial layer coupled to the first side of the III-nitride substrate and a plurality of III-nitride regions of a second conductivity type. The plurality of III-nitride regions have at least one III-nitride epitaxial region of the first conductivity type between each of the plurality of III-nitride regions. The semiconductor structure further includes a first metallic structure electrically coupled to one or more of the plurality of III-nitride regions and the at least one III-nitride epitaxial region. A Schottky contact is created between the first metallic structure and the at least one III-nitride epitaxial region.

Abstract: A vertical conduction nitride-based Schottky diode is formed using an insulating substrate which was lifted off after the diode device is encapsulated on the front side with a wafer level molding compound. The wafer level molding compound provides structural support on the front side of the diode device to allow the insulating substrate to be lifted off so that a conductive layer can be formed on the backside of the diode device as the cathode electrode. A vertical conduction nitride-based Schottky diode is thus realized. In another embodiment, a protection circuit for a vertical GaN Schottky diode employs a silicon-based vertical PN junction diode connected in parallel to the GaN Schottky diode to divert reverse bias avalanche current.

Abstract: A schottky barrier diode includes: an n? type epitaxial layer that is disposed at a first surface of an n+ type silicon carbide substrate; a plurality of n type pillar areas that are disposed at the inside of the n? type epitaxial layer and that are disposed at a first portion of the first surface of the n+ type silicon carbide substrate; a p type area that is disposed at the inside of the n? type epitaxial layer and that is extended in a direction perpendicular to the n type pillar areas; a plurality of p+ areas in which the n? type epitaxial layer is disposed at a surface thereof and that are separated from the n type pillar areas and the p type area; a schottky electrode that is disposed on the n? type epitaxial layer and the p+ areas; and an ohmic electrode that is disposed at a second surface of the n+ type silicon carbide substrate.

Abstract: A method for manufacturing a semiconductor device includes the steps of preparing a substrate made of silicon carbide and having an n type region formed to include a main surface, forming a p type region in a region including the main surface, forming an oxide film on the main surface across the n type region and the p type region, by heating the substrate having the p type region formed therein at a temperature of 1250° C. or more, removing the oxide film to expose at least a part of the main surface, and forming a Schottky electrode in contact with the main surface that has been exposed by removing the oxide film.

Abstract: A device includes a Schottky barrier formed by a metal-semiconductor junction between a semiconductor nanowire and a metal contact. The metal contact at least partly encloses a circumferential area of each nanowire along the length thereof. The nanowire includes a low doped region that is part of the metal-semiconductor junction. The device can be fabricated using a method where two different growth modes are used, the first step including axial growth from a substrate giving a suitable template for formation of the metal-semiconductor junction, and the second step including radial growth enabling control of the doping levels in the low doped region.

Abstract: A semiconductor device includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. The first portion of the first electrode has a lower Schottky potential barrier than the second portion of the first electrode. A second electrode is in contact with the first active layer.

Abstract: A semiconductor device such as a Schottky diode is provided which includes a substrate, a first active layer disposed over the substrate and a second active layer disposed on the first active layer. The second active layer has a higher bandgap than the first active layer such that a two-dimensional electron gas layer arises between the first active layer and the second active layer. A first electrode has a first portion disposed in a recess in the second active layer and a second portion disposed on the second active layer such that a Schottky junction is formed therewith. A second electrode is in contact with the first active layer. The second electrode establishes an ohmic junction with the first active layer.

Abstract: The disclosed technology relates to a device including a diode. In one aspect, the device includes a lower group III metal nitride layer and an upper group III metal nitride layer and a heterojunction formed therebetween, where the heterojunction extends horizontally and is configured to form a two-dimensional electron gas (2DEG) that is substantially confined in a vertical direction and within the lower group III metal nitride layer. The device additionally includes a cathode forming an ohmic contact with the upper group III metal nitride layer. The device additionally includes an anode, which includes a first portion that forms a Schottky barrier contact with the upper group III metal nitride layer, and a second portion that is separated vertically from the upper group III metal nitride layer by a layer of dielectric material.

Abstract: Compound semiconductor devices and methods of doping compound semiconductors are provided. Embodiments of the invention provide post-deposition (or post-growth) doping of compound semiconductors, enabling nanoscale compound semiconductor devices including diodes and transistors. In one method, a self-limiting monolayer technique with an annealing step is used to form shallow junctions. By forming a sulfur monolayer on a surface of an InAs substrate and performing a thermal annealing to drive the sulfur into the InAs substrate, n-type doping for InAs-based devices can be achieved. The monolayer can be formed by surface chemistry reactions or a gas phase deposition of the dopant. In another method, a gas-phase technique with surface diffusion is used to form doped regions. By performing gas-phase surface diffusion of Zn into InAs, p-type doping for InAs-based devices can be achieved.

Abstract: A compound semiconductor device includes: a compound semiconductor layered structure; a gate electrode formed above the compound semiconductor layered structure; a first protective insulating film that covers a surface of the compound semiconductor layered structure and is made of silicon nitride as a material; a second protective insulating film that covers the gate electrode on the first protective insulating film and is made of silicon oxide as a material; and a third protective insulating film that contains silicon oxynitride and is formed between the first protective insulating film and the second protective insulating film.

Abstract: A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.

Abstract: A schottky diode includes a SiC substrate which has a first surface and a second surface facing away from the first surface, a semiconductor layer which is formed on the first surface of the SiC substrate, a schottky electrode which is in contact with the semiconductor layer, and an ohmic electrode which is in contact with the second surface of the SiC substrate. The first surface of the SiC substrate is a (000-1) C surface, upon which the semiconductor layer is formed.

Abstract: A wide gap semiconductor device has a substrate and a Schottky electrode. The substrate is made of a wide gap semiconductor material and has a first conductivity type. The Schottky electrode is arranged on the substrate to be in contact therewith and is made of a single material. The Schottky electrode includes a first region having a first barrier height and a second region having a second barrier height higher than the first barrier height. The second region includes an outer peripheral portion of the Schottky electrode. Thus, a wide gap semiconductor device capable of achieving less leakage current and a method for manufacturing the same can be provided.

Abstract: A wide gap semiconductor device includes a substrate and a Schottky electrode. The substrate formed of a wide gap semiconductor material has a main face, and includes a first-conductivity-type region and a second-conductivity-type region. The Schottky electrode is arranged adjoining the main face of the substrate. At the substrate, there is foamed a trench having a side face continuous with the main face and a bottom continuous with the side face. The Schottky electrode adjoins the first-conductivity-type region at the side face of the trench and the main face, and adjoins the second-conductivity-type region at the bottom of the trench. The side face of the trench is inclined relative to the main face of the substrate.

Abstract: A method of forming a group III nitride semiconductor comprises: preparing a group III nitride semiconductor which contains a p-type dopant or an n-type dopant; and performing a treatment of the group III nitride semiconductor by using a reducing gas and a nitrogen source gas to form a conductive group III nitride semiconductor. The treatment includes performing a first treatment of the group III nitride semiconductor by using a first treatment gas including the reducing gas and the nitrogen source gas, which are supplied to a treatment apparatus at a first flow rate and a second flow rate, respectively, and after the first treatment is performed, performing a second treatment of the group III nitride semiconductor by using a second treatment gas including the reducing gas and the nitrogen source gas, which are supplied to the treatment apparatus at a third flow rate and a fourth flow rate, respectively.

Abstract: A Schottky barrier diode (SBD) is disclosed, which includes: a gallium nitride (GaN) layer, formed on a substrate; an aluminum gallium nitride (AlGaN), formed on the GaN layer; an insulation layer, formed on the AlGaN layer; an anode conducive layer, formed on the insulation layer, wherein Schottky contact is formed between a part of the anode conductive layer and the AlGaN layer or between a part of the anode conductive layer and the GaN layer, and another part of the anode conductive layer is separated from the AlGaN layer by the insulation layer; and a cathode conductive layer, formed on the AlGaN layer, wherein an ohmic contact is formed between the cathode conductive layer and the GaN layer or between the cathode conductive layer and the AlGaN layer, and wherein the anode conductive layer is not directly connected to the cathode conductive layer.

Abstract: A method of manufacturing a semiconductor wafer, which includes: a semiconductor substrate made of silicon and having both a central area and an outer periphery area; and a compound semiconductor layer made of a nitride-based semiconductor and formed on the semiconductor substrate, the method comprising: forming a growth inhibition layer to inhibit the compound semiconductor layer from growing on a tapered part provided in the outer periphery area of the semiconductor substrate; and growing the compound semiconductor layer on at least the central area of the semiconductor substrate, after the growth inhibition layer has been formed.

Abstract: A manufacturing method for antenna switching circuit includes the following steps of: providing a GaAs wafer, which includes a capping layer; disposing an isolation layer to the GaAs wafer for forming a device area; and disposing a gate metal on the capping layer within the device area, wherein an interface between the gate metal and the capping layer forms a Schottky contact, and the Schottky contact is parallel connected with an impedance. The present invention also discloses a semiconductor structure for antenna switching circuit.

Abstract: In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta2O5 under a gate electrode.

Abstract: According to one disclosed embodiment, a monolithic vertically integrated composite device comprises a double sided semiconductor substrate having first and second sides, a group IV semiconductor layer formed over the first side and comprising at least one group IV semiconductor device, and a group III-V semiconductor body formed over the second side and comprising at least one group III-V semiconductor device electrically coupled to the at least one group IV semiconductor device. The composite device may further comprise a substrate via and/or a through-wafer via providing electric coupling. In one embodiment, the group IV semiconductor layer may comprise an epitaxial silicon layer, and the at least one group IV semiconductor device may be a combined FET and Schottky diode (FETKY) fabricated on the epitaxial silicon layer. In one embodiment, the at least one group III-V semiconductor device may be a III-nitride high electron mobility transistor (HEMT).

Abstract: A method for fabricating a metal structure for a semiconductor device is disclosed. The method begins with providing a wafer with a current input contact and current output contact. Remaining steps include loading the wafer into a deposition apparatus, depositing a layer of metal onto a predefined metal region, removing the wafer from the deposition apparatus, and performing an ex-situ passivation process. If additional layers are to be deposited and passivated, the steps are repeated until a predetermined number of layers of metal are deposited onto the predefined metal region. The predefined metal region is a gate metal opening if the metal structure is a gate contact for a field effect transistor. The ex-situ passivation process is achievable through oxidation or nitridation of the wafer using either oxygen plasma or a nitrogen plasma, respectively. Alternately, oxidation is also achievable through exposing the wafer to air at an elevated temperature.