Abstract: An integrated circuit device includes a substrate including active regions, a direct contact electrically connected to a first active region selected from the active regions, a buried contact plug electrically connected to a second active region selected from the active regions, the second active region adjacent to the first active region in a first horizontal direction, and including a conductive semiconductor layer, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction and electrically connected to the direct contact, a conductive landing pad extending toward the buried contact plug in a vertical direction, having a sidewall facing the bit line in the first horizontal direction, and including a metal, and an outer insulating spacer between the bit line and the conductive landing pad, in contact with the sidewall of the conductive landing pad, and spaced apart from the buried contact plug.

Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating layer on a substrate, forming a first mask layer on the interlayer insulating layer, forming a second mask layer and a first spacer on the first mask layer, forming a photoresist pattern on the second mask layer, forming a second mask pattern by patterning the second mask layer through a first etching process, forming a first mask pattern by patterning the first mask layer through a second etching process, forming a trench by etching a portion of the interlayer insulating layer through a third etching process, and forming an interconnection pattern within the trench. A width of the first mask pattern after the second etching process is less than a width of the photoresist pattern.

Abstract: The present disclosure relates to a lateral double-diffused transistor and a manufacturing method of the transistor. The transistor comprises: a substrate; a well region and a drift region both located in the top of the substrate, a source region located in the well region, and a drain region located in the drift region; a first dielectric layer located on a surface of the drift region; a first field plate layer located above the drift region and covering a first portion of the first dielectric layer; a second dielectric layer covering a surface of part of the first field plate layer and stacked on a surface of a second portion of the first dielectric layer; a second field plate layer located on a surface of the second dielectric layer, comprising at least one contact channel. According to the present disclosure, the transistor increases breakdown voltage and reduces on-state resistance.

Abstract: A semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (ESL) on the first conductive contact, and a second conductive contact extending through the ESL. The first conductive contact has a first width. The second conductive contact has a second width, the second width being smaller than the first width. The ESL overhangs a portion of the second conductive contact. A convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact.

Abstract: A semiconductor device includes a line; a source structure on the line; a stack structure on the source structure; a first slit structure penetrating the stack structure; a second slit structure penetrating the stack structure; and a contact plug adjacent to the first slit structure in a first direction. The first slit structure and the second slit structure may be spaced apart from each other by a first distance in a second direction that is perpendicular to the first direction. The contact plug penetrates the source structure, the contact plug being electrically connected to the lower line. The first slit structure and the contact plug may be spaced apart from each other by a second distance in the first direction, and the second distance may be longer than the first distance.

Abstract: A semiconductor device includes a semiconductor substrate, a gate electrode, a source/drain contact, a conductive structure, an interlayer dielectric (ILD) layer, an etch stop layer, and a dielectric liner. The semiconductor substrate has a channel region and a source/drain region. The gate electrode is over the channel region. The source/drain contact is over the source/drain region. The conductive structure is over a top surface of the source/drain contact. The ILD layer surrounds the conductive structure and over the gate electrode. The etch stop layer is over the conductive structure and the ILD layer. The etch stop layer comprises a material different from that of the ILD layer. A dielectric liner at a sidewall the conductive structure. The dielectric liner extends from the top surface of the source/drain contact to a bottom surface of the etch stop layer.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: Interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the interconnects are disclosed herein. An exemplary interconnect is disposed in an insulating layer. The interconnect has a metal contact, a contact isolation layer surrounding sidewalls of the metal contact, and an air gap disposed between the contact isolation layer and the insulating layer. An air gap seal for the air gap has a first portion disposed over a top surface of the contact isolation layer, but not disposed on a top surface of the insulating layer, and a second portion disposed between the contact isolation layer and the insulating layer, such that the second portion surrounds a top portion of sidewalls of the metal contact. The air gap seal may include amorphous silicon and/or silicon oxide. The contact isolation layer may include silicon nitride. The insulating layer may include silicon oxide.

Abstract: A semiconductor device includes a line; a source structure on the line; a stack structure on the source structure; a first slit structure penetrating the stack structure; a second slit structure penetrating the stack structure; and a contact plug adjacent to the first slit structure in a first direction. The first slit structure and the second slit structure may be spaced apart from each other by a first distance in a second direction that is perpendicular to the first direction. The contact plug penetrates the source structure, the contact plug being electrically connected to the lower line. The first slit structure and the contact plug may be spaced apart from each other by a second distance in the first direction, and the second distance may be longer than the first distance.

Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate strip disposed over the substrate. The gate strip includes a high-k layer disposed over the substrate, an N-type work function metal layer disposed over the high-k layer, and a barrier layer disposed over the N-type work function metal layer. The barrier layer includes at least one first film containing TiAlN, TaAlN or AlN.

Abstract: The present invention relates to an LDMOS device and a method for preparing same. When a field plate hole is formed by etching an interlayer dielectric layer, the etching of the field plate hole is stopped on a blocking layer by means of providing the blocking layer between a semiconductor base and the interlayer dielectric layer. Since the blocking layer is provided with at least one layer of an etch stop layer, and steps are formed on the surface of the blocking layer, at least two levels of formed hole field plates are distributed in a step shape, and lower ends of the first level of hole field plates to the nth level of hole field plates are gradually further away from the drift area in the direction from a gate structure to a drain area.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.

Abstract: The invention discloses a semiconductor memory device, which is characterized by comprising a substrate defining a cell region and an adjacent periphery region, a plurality of bit lines are arranged on the substrate and arranged along a first direction, each bit line comprises a conductive part, and the bit line comprises four sidewalls, and a spacer surrounds the four sidewalls of the bit line, the spacer comprises two short spacers covering two ends of the conductive part, two long spacers covering the two long sides of the conductive part, and a plurality of storage node contact isolations located between any two adjacent bit lines, at least a part of the storage node contact isolations cover directly above the spacers. The structure of the invention can improve the electrical isolation effect, preferably avoid leakage current and improve the quality of components.

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: A method for manufacturing a semiconductor device includes forming a gate trench over a semiconductor fin, the gate trench including an upper portion and a lower portion. The method includes sequentially forming one or more work function layers, a capping layer, and a glue layer over the gate trench. The glue layer includes a first sub-layer and a second sub-layer that have respective different etching rates with respect to an etching solution. The method includes removing the second sub-layer while leaving a first portion of the first sub-layer filled in the lower portion of the gate trench.

Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.

Abstract: A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.

Abstract: In an embodiment, a structure includes: a gate stack over a channel region of a substrate; a source/drain region adjacent the channel region; a first inter-layer dielectric (ILD) layer over the source/drain region; a silicide between the first ILD layer and the source/drain region, the silicide contacting a top surface of the source/drain region and a bottom surface of the source/drain region; and a first source/drain contact having a first portion and a second portion, the first portion of the first source/drain contact disposed between the silicide and the first ILD layer, the second portion of the first source/drain contact extending through the first ILD layer and contacting the silicide.

Abstract: A semiconductor structure manufacturing method includes that a substrate is provided, in which the substrate includes a substrate layer and a plurality of bit line structures arranged on the substrate layer in a first direction, the substrate layer includes shallow trench isolation structures, active areas, and a plurality of word line structures arranged in a second direction, and two adjacent bit line structures and two adjacent word line structures define a conductive contact region, and the conductive contact region exposing part of a corresponding active area; a conducting layer is formed between the bit line structures, the conducting layer covering the substrate layer, and the conducting layer extending along the first direction; part of the conducting layer is removed with the conducting layer corresponding to the conductive contact region retained to form first capacitor wires; and an isolation layer is formed, which fills gaps between the first capacitor wires.

Abstract: A semiconductor device includes first and second gate structures over a substrate, the first gate structure has a first width that is smaller than a second width of the second gate structure, in which a lower portion of the first gate structure having a first work-function material (WFM) layer, the first WFM layer having a top surface, a lower portion of the second gate structure having a second WFM layer, the second WFM layer having a top surface. A first gate electrode is disposed over the first WFM layer and a second gate electrode has a lower portion disposed in the second WFM layer, in which the first gate electrode has a first width that is smaller than a second width of the second gate electrode, and wherein the top surface of the second WFM layer is at a level below a top surface of the second gate electrode.

Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.

Abstract: Provided is a memory device including a substrate, a plurality of contacts, and a plurality of air gaps. The substrate has a plurality of active areas. The contacts are respectively disposed on ends of the active areas. The air gaps respectively surround the sidewalls of the contacts.

Abstract: A method is presented for reducing parasitic capacitance. The method includes forming a p-type epitaxial region and an n-type epitaxial region over a substrate, depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region, depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween, and selectively removing the epitaxial growth to expose top surfaces of the p-type and n-type epitaxial regions. The method further includes depositing a second dielectric in direct contact with the exposed top surfaces of the p-type and n-type epitaxial regions, selectively etching the first and second dielectrics to form a strapped contact, and applying a metallization layer over the strapped contact.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate; an insulating layer provided on the substrate; a conductive layer provided on the insulating layer; a stacked body provided on the conductive layer and including a plurality of electrode layers and a plurality of insulating layers respectively provided among the plurality of electrode layers; a columnar section piercing through the stacked body to reach the conductive layer and extending in a first direction in which the stacked body is stacked; and a source layer. The columnar section includes a channel body and a charge storage film provided between the channel body and the respective electrode layers. The conductive layer includes a first film having electric conductivity and in contact with the lower end portion of the channel body; and an air gap provided to be covered by the first film.

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a first inter-layer dielectric (ILD) layer formed over the fin structure. The FinFET device structure includes a gate structure formed in the first ILD layer, and a first S/D contact structure formed in the first ILD layer and adjacent to the gate structure. The FinFET device structure also includes a first air gap formed on a sidewall of the first S/D contact structure, and the first air gap is in direct contact with the first ILD layer.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a first electrode layer disposed on the substrate, a gate electrode layer disposed on the first electrode layer, a second electrode layer disposed on the gate electrode layer, an oxide semiconductor layer penetrating through the gate electrode layer, a gate dielectric layer disposed between the gate electrode layer and the oxide semiconductor layer, a first insulating layer disposed between the gate electrode layer and the first electrode layer, and a second insulating layer disposed between the gate electrode layer and the second electrode layer. The oxide semiconductor layer is in direct contact with the first electrode layer and the second electrode layer, respectively.

Abstract: Semiconductor devices fabrication method is provided. The method for fabricating the semiconductor device includes: providing a semiconductor substrate; forming a gate structure on a surface of the semiconductor substrate; forming protective sidewall spacers on sidewall surfaces of the gate structure and to cover sidewall surfaces of the gate dielectric layer; forming sacrificial sidewall spacers on sidewall surfaces of the protective sidewall spacers and between the protective sidewall spacers and the gate structure; forming a first dielectric layer on the surface of the semiconductor substrate around the gate structure, the protective sidewall spacers and the sacrificial sidewall spacers; forming conductive plugs in the first dielectric layer at opposite sides of the gate structure, the protective sidewall spacers and the sacrificial sidewall spacers; and removing the sacrificial sidewall spacers to form air gap spacers between the protective sidewall spacers and the conductive plugs.

Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.

Abstract: The present disclosure relates to a method for preparing a semiconductor device with air gaps between conductive lines (e.g., bit lines). The method includes forming a first dielectric structure and a second dielectric structure over a semiconductor substrate, and forming a conductive material over the first dielectric structure and the second dielectric structure. The conductive material extends into a first opening between the first dielectric structure and the second dielectric structure. The method also includes partially removing the conductive material to form a first bit line and a second bit line in the first opening and forming a sealing dielectric layer over the first bit line and the second bit line such that an air gap is formed between the sealing dielectric layer and the semiconductor substrate.

Abstract: A method used in forming integrated circuitry comprises forming conductive line structures having conductive vias laterally between and spaced longitudinally along immediately-adjacent of the conductive line structures. First insulating material is formed laterally between immediately-adjacent of the conductive vias. Second insulating material is formed directly above the first insulating material and directly above the conductive vias. The second insulating material comprises silicon, carbon, nitrogen, and hydrogen. A third material is formed directly above the second insulating material. The third material and the second insulating material comprise different compositions relative one another. The third material is removed from being directly above the second insulating material and the thickness of the second insulating material is reduced thereafter. A fourth insulating material is formed directly above the second insulating material of reduced thickness.

Abstract: The present disclosure provides a method for preparing a semiconductor device with a T-shaped buried gate electrode. The method includes forming an isolation structure in a semiconductor substrate to define an active region, and forming a doped region in the active region. The method also includes etching the semiconductor substrate to form a first trench and a second trench. The first trench has a first portion extending across the doped region and a second portion extending away from the first portion, and the second trench has a third portion extending across the doped region and a fourth portion extending away from the third portion. The method further includes forming a first gate electrode in the first trench and a second gate electrode in the second trench.

Abstract: A semiconductor device comprises a first gate electrode on a substrate, a first conductive contact on the first gate electrode, an etch stop layer (ESL) on the first conductive contact, and a second conductive contact extending through the ESL. The first conductive contact has a first width. The second conductive contact has a second width, the second width being smaller than the first width. The ESL overhangs a portion of the second conductive contact. A convex bottom surface of the second conductive contact physically contacts a concave top surface of the first conductive contact.

Abstract: A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.

Abstract: In an embodiment, a method includes: forming a differential contact etch stop layer (CESL) having a first portion over a source/drain region and a second portion along a gate stack, the source/drain region being in a substrate, the gate stack being over the substrate proximate the source/drain region, a first thickness of the first portion being greater than a second thickness of the second portion; depositing a first interlayer dielectric (ILD) over the differential CESL; forming a source/drain contact opening in the first ILD; forming a contact spacer along sidewalls of the source/drain contact opening; after forming the contact spacer, extending the source/drain contact opening through the differential CESL; and forming a first source/drain contact in the extended source/drain contact opening, the first source/drain contact physically and electrically coupling the source/drain region, the contact spacer physically separating the first source/drain contact from the first ILD.

Abstract: A method includes following steps. First and second gate electrodes are formed over a substrate, with an ILD layer between the first and second gate electrodes. A first etch operation is performed to etch the first and second gate electrodes. A sacrificial layer is formed across the etched first and second gate electrodes and the ILD layer. A second etch operation is performed to etch the sacrificial layer and the etched the first and second gate electrodes.

Abstract: Methods and systems for depositing vanadium and/or indium layers onto a surface of a substrate and structures and devices formed using the methods are disclosed. An exemplary method includes using a cyclical deposition process, depositing a vanadium and/or indium layer onto the surface of the substrate. The cyclical deposition process can include providing a vanadium and/or indium precursor to the reaction chamber and separately providing a reactant to the reaction chamber. The cyclical deposition process may desirably be a thermal cyclical deposition process. Exemplary structures can include field effect transistor structures, such as gate all around structures. The vanadium and/or indium layers can be used, for example, as barrier layers or liners, as work function layers, as dipole shifter layers, or the like.

Abstract: In an embodiment, a structure includes: a contact etch stop layer (CESL) over a substrate; a fin extending through the CESL; an epitaxial source/drain region in the fin, the epitaxial source/drain region extending through the CESL; a silicide contacting upper facets of the epitaxial source/drain region; a source/drain contact contacting the silicide, lower facets of the epitaxial source/drain region, and a first surface of the CESL; and an inter-layer dielectric (ILD) layer surrounding the source/drain contact, the ILD layer contacting the first surface of the CESL.

Abstract: In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.

Abstract: A semiconductor device, and a manufacturing method thereof. The method includes: providing a semiconductor substrate provided with a body region, a gate dielectric layer, and a field oxide layer, formed on the semiconductor substrate; forming a gate polycrystalline, the gate polycrystalline covering the gate dielectric layer and the field oxide layer and exposing at least one portion of the field oxide layer; forming a drift region in the semiconductor substrate by ion implantation using a drift region masking layer as a mask, removing the exposed portion of the field oxide layer by further using the drift region masking layer as the mask to form a first field oxide self-aligned with the gate polycrystalline; forming a source region in the body region, and forming a drain region in the drift region; forming a second field oxide on the semiconductor substrate; and forming a second field plate on the second field oxide.

Abstract: One illustrative IC product disclosed herein includes a transistor device formed on a semiconductor substrate, the transistor device comprising a gate structure comprising an upper surface, a polish-stop sidewall spacer positioned adjacent the gate structure, wherein, at a location above an upper surface of the semiconductor substrate, when viewed in a cross-section taken through the first polish-stop sidewall spacer in a direction corresponding to a gate length direction of the transistor, an upper surface of the gate structure is substantially coplanar with an upper surface of the polish-stop sidewall spacer.

Abstract: A terminal of a flexible organic EL display device is formed using a third conductive member being a second metal layer exposed through an opening of a second resin layer. In the opening of the second resin layer, a protruding portion being formed using a third resin layer being a layer lower than the second resin layer and the third conductive member being the second metal layer overlap each other.

Abstract: The present invention provides a display panel and a manufacturing method of the display panel. By etching a certain amount of a protective layer in a first contact region and in a second contact region, a first via hole and a second via hole expose a surface of an active layer, and a source/drain metal layer is connected to the active layer through the first via hole and the second via hole. The present invention does not use a hydrofluoric acid cleaning machine (HFC) to rinse the protective layer, so a first capacitor electrode and a second capacitor electrode are effectively prevented from being etched by hydrofluoric acid (HF). Accordingly, stable thin-film-transistor (TFT) electrical parameters are obtained.

Abstract: A semiconductor memory device includes; a first impurity region and a second impurity region spaced apart in a substrate, a device isolation pattern between the first impurity region and the second impurity region, a bit-line contact on the first impurity region, a storage node contact on the second impurity region and a dielectric pattern between the bit-line contact and the storage node contact. An upper part of a sidewall of the device isolation pattern has a first slope and a lower part of the sidewall of the device isolation pattern has a second slope different from the first slope.

Abstract: Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface.

Abstract: A display panel includes a base layer, a first thin film transistor disposed on the base layer and including a silicon semiconductor pattern, a first control electrode is spaced apart from the silicon semiconductor pattern. A first input electrode is connected to a first side of the silicon semiconductor pattern. A first output electrode is connected to a second side of the silicon semiconductor pattern. The display panel includes a second thin film transistor. An organic light emitting diode includes a first electrode connected to the first thin film transistor, a second electrode, and an emission layer. A first insulating layer includes openings exposing the first side and the second side of the silicon semiconductor pattern, respectively. The first input electrode and the first output electrode are positioned in the openings, respectively.

Abstract: A method is presented for employing contact over active gate to reduce parasitic capacitance. The method includes forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion, forming a first dielectric over the HKMGs, forming first contacts to source/drain of a transistor between the HKMGs, and forming a second dielectric over the first contacts. The method further includes selectively removing the first dielectric to form second contacts to the HKMGs, selectively removing the second dielectric to form third contacts on top of the first contacts, removing the sacrificial upper portion of the stacked spacers, and depositing a third dielectric that pinches off the remaining first and second dielectrics to form air-gaps between the first contacts and the HKMGs.

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.

Abstract: An electronic device and a method for manufacturing the same are disclosed. The method for manufacturing the electronic device includes the following steps: providing a substrate; forming a metal layer on the substrate, wherein the metal layer has a first surface; forming a first insulating layer on the first surface of the metal layer; forming a second insulating layer on the first insulating layer; etching the first insulating layer and the second insulating layer to form a contact hole, wherein the contact hole exposes a portion of the first surface; cleaning the portion of the first surface exposed by the contact hole with a solution; and forming a transparent conductive layer on the second insulating layer, wherein the transparent conductive layer electrically connects with the metal layer.

Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer.