Combined With Formation Of Ohmic Contact To Semiconductor Region Patents (Class 438/586)
  • Patent number: 11309397
    Abstract: A method is presented for employing contact over active gate to reduce parasitic capacitance. The method includes forming high-k metal gates (HKMGs) between stacked spacers, the stacked spacers including a low-k dielectric lower portion and a sacrificial upper portion, forming a first dielectric over the HKMGs, forming first contacts to source/drain of a transistor between the HKMGs, and forming a second dielectric over the first contacts. The method further includes selectively removing the first dielectric to form second contacts to the HKMGs, selectively removing the second dielectric to form third contacts on top of the first contacts, removing the sacrificial upper portion of the stacked spacers, and depositing a third dielectric that pinches off the remaining first and second dielectrics to form air-gaps between the first contacts and the HKMGs.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: April 19, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kangguo Cheng
  • Patent number: 11282787
    Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: March 22, 2022
    Inventors: Taejin Park, Keunnam Kim, Sohyun Park, Jin-Hwan Chun, Wooyoung Choi, Sunghee Han, Inkyoung Heo, Yoosang Hwang
  • Patent number: 11239340
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
  • Patent number: 11234330
    Abstract: An electronic device and a method for manufacturing the same are disclosed. The method for manufacturing the electronic device includes the following steps: providing a substrate; forming a metal layer on the substrate, wherein the metal layer has a first surface; forming a first insulating layer on the first surface of the metal layer; forming a second insulating layer on the first insulating layer; etching the first insulating layer and the second insulating layer to form a contact hole, wherein the contact hole exposes a portion of the first surface; cleaning the portion of the first surface exposed by the contact hole with a solution; and forming a transparent conductive layer on the second insulating layer, wherein the transparent conductive layer electrically connects with the metal layer.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: January 25, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Po-Yun Hsu, Ker-Yih Kao, Chia-Ping Tseng
  • Patent number: 11227796
    Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: January 18, 2022
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Lawrence A. Clevenger, Baozhen Li, Xiao H. Liu, Kirk D. Peterson
  • Patent number: 11211471
    Abstract: The present invention discloses a metal gate process. A sacrificial nitride layer is introduced during the fabrication of metal gates. The gate height can be well controlled by introducing the sacrificial nitride layer. Further, the particle fall-on problem can be effectively solved.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: December 28, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Fu-Shou Tsai, Yong-Yi Lin, Yang-Ju Lu, Yu-Lung Shih, Ji-Min Lin, Ching-Yang Chuang, Kun-Ju Li
  • Patent number: 11164782
    Abstract: A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins upon a substrate, forming a plurality of epitaxially grown source-drain regions upon the fins, forming a plurality of device gates upon the fins, the device gates disposed between the epitaxially grown source-drain regions, forming a trench exposing at least one epitaxially grown source-drain region, masking at least a portion of the exposed epitaxially grown source-drain region, forming a gate trench exposing at least a portion of a device gate and gate spacer, forming a metallization layer between the epitaxially grown source-drain region and the device gate, selectively recessing the metallization layer, forming a conductive layer upon the metallization layer, and forming a dielectric cap above the conductive layer.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Balasubramanian S Pranatharthi Haran, Dechao Guo, Nicolas Loubet, Alexander Reznicek
  • Patent number: 11127752
    Abstract: A semiconductor device includes a substrate, having cell region and high-voltage region. A memory cell is on the substrate within the cell region. The memory cell includes a memory gate structure and a selection gate structure on the substrate. A first spacer is sandwiched between or respectively on sidewalls of the memory cell structure and the selection gate structure. First high-voltage transistor is on the substrate within the high-voltage region. A first composite gate structure of the first high-voltage transistor includes a first gate structure on the substrate, an insulating layer with a predetermined thickness on the substrate in a -like structure or an L-like structure at cross-section, and a second gate structure on the insulating layer along the -like structure or the L-like structure. The selection gate structure and the second gate structure are originated from a same preliminary conductive layer.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: September 21, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ching Hsu, Wang Xiang, Shen-De Wang, Chun-Sung Huang
  • Patent number: 11087990
    Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: August 10, 2021
    Inventors: Chang Sun Hwang, Han Sol Seok, Hyun Ku Kang, Byoung Ho Kwon, Chung Ki Min
  • Patent number: 11069694
    Abstract: A semiconductor structure and a method for forming same are provided. In one form a method includes: providing a substrate with a discrete first gate laminated structure formed on the substrate; forming, on a portion of the substrate exposed from the first gate laminated structure, a unit dielectric layer covering a portion of a side wall of the first gate laminated structure, where the first gate laminated structure and the unit dielectric layer enclose a unit groove; forming an isolation spacer layer on a side wall of the unit groove, where the isolation spacer layer is in contact with the unit dielectric layer; forming a metal layer conformally covering the isolation spacer layer, the first gate laminated structure, and the unit dielectric layer; and annealing the metal layer to form a metal silicide layer.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: July 20, 2021
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Han Liang, Wang Hai Ying
  • Patent number: 11069814
    Abstract: An electronic device can include a panel; a driver circuit configured to drive the panel; and a transistor disposed in the panel, the transistor including: a gate electrode disposed on a substrate, a first insulating film disposed on the gate electrode, an active layer disposed on the first insulating film, the active layer including: a first portion of the active layer overlapping with an upper surface of the gate electrode, a second portion of the active layer extending from the first portion, being disposed along a side surface of the gate electrode and including a channel area, and a third portion of the active layer extending from the second portion of the active layer, the third portion of the active layer being disposed on a portion of the first insulating film that does not overlap with the gate electrode, a second insulating film disposed on the active layer, a first electrode disposed on the second insulating film, the first electrode being electrically connected to the first portion of the active l
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: July 20, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: SangYun Sung, SeHee Park, Jiyong Noh, InTak Cho, PilSang Yun
  • Patent number: 10998187
    Abstract: Methods are provided for conducting a deposition on a semiconductor substrate by selectively depositing a material on the substrate. The substrate has a plurality of substrate materials, each with a different nucleation delay corresponding to the material deposited thereon. Specifically, the nucleation delay associated with a first substrate material on which deposition is intended is less than the nucleation delay associated with a second substrate material on which deposition is not intended according to a nucleation delay differential, which degrades as deposition proceeds. A portion of the deposited material is etched to reestablish the nucleation delay differential between the first and the second substrate materials. The material is further selectively deposited on the substrate.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: May 4, 2021
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Kapu Sirish Reddy, Meliha Gozde Rainville, Nagraj Shankar, Dennis M. Hausmann, David Charles Smith, Karthik Sivaramakrishnan, David W. Porter
  • Patent number: 10998322
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: May 4, 2021
    Inventors: Daeik Kim, Bong-Soo Kim, Jemin Park, Taejin Park, Yoosang Hwang
  • Patent number: 10998335
    Abstract: A semiconductor device according to an embodiment includes a semiconductor substrate, a plurality of conductive layers extending in a first direction on the semiconductor substrate, and laminated in a third direction perpendicular to the first direction and a second direction at intervals in the second direction perpendicular to the first direction, and a passivation film which has several layers provided above the plurality of conductive layers. The passivation film has a first nitride film provided above the plurality of conductive layers, and a second nitride film provided on the first nitride film, and the second nitride film has the concave and convex shape which is repeated along the second direction.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: May 4, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Noguchi
  • Patent number: 10943909
    Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: March 9, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
  • Patent number: 10872811
    Abstract: Provided is a memory device including a substrate, a plurality of contacts, and a plurality of air gaps. The substrate has a plurality of active areas. The contacts are respectively disposed on ends of the active areas. The air gaps respectively surround the sidewalls of the contacts.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: December 22, 2020
    Assignee: Winbond Electronics Corp.
    Inventor: Huang-Nan Chen
  • Patent number: 10861923
    Abstract: A display device includes a substrate in which a first area, a second area and a bending area between the first and second areas are defined, a plurality of pixels disposed above the substrate in the first area, a plurality of conductive layers extending to and intersecting the bending area, a protective film covering the conductive layers and disposed in the bending area, a first portion of the first area adjacent to the bending area, and a second portion of the second area adjacent to the bending area. The display device further includes a plurality of tag layers disposed in the first and second portions and connected to both ends of the conductive layers, wherein the bending area is interposed between the plurality of tag layers. The tag layers are exposed to an outside of the display device by exposure holes defined in the protective film.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: December 8, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Horyun Chung, Sejoong Shin, Hyojin Kim, Taehyun Sung, Changhan Lee
  • Patent number: 10832962
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of gate structures on a semiconductor fin, and forming a plurality of source/drain regions adjacent the gate structures. A sacrificial spacer layer is deposited on the source/drain regions, and part of the sacrificial spacer layer is removed to expose portions of the source/drain regions. A plurality of source/drain contacts are formed on the source/drain regions, wherein remaining portions of the sacrificial spacer layer are positioned between the source/drain contacts and adjacent ones of the gate structures. The method also includes removing the remaining portions of the sacrificial spacer layer to form a plurality of spaces between the source/drain contacts and the adjacent ones of the gate structures. The removal of the remaining portions of the sacrificial spacer layer is performed using a water-based etch. A dielectric material including a plurality of air gaps is deposited in the spaces.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu, ChoongHyun Lee
  • Patent number: 10825818
    Abstract: A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: November 3, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen
  • Patent number: 10699951
    Abstract: According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: June 30, 2020
    Assignee: ELPIS TECHNOLOGIES INC.
    Inventors: Balasubramanian Pranatharthiharan, Injo Ok, Charan V. V. S. Surisetty
  • Patent number: 10680078
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
  • Patent number: 10651091
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 10644025
    Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 5, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
  • Patent number: 10629602
    Abstract: Structures for a static random access memory (SRAM) bitcell and methods for forming a SRAM bitcell. The SRAM includes a storage element with a first pull-up (PU) vertical-transport field-effect transistor (VTFET) having a first bottom source/drain region and a fin projecting from the first bottom source/drain region, and a second pull-up (PU) VTFET with a second bottom source/drain region and a fin projecting from the second bottom source/drain region. The fin of the first PU VTFET is arranged over a first active region in which the first bottom source/drain region is centrally arranged, and the fin of the second PU VTFET is arranged over a second active region in which the second bottom source/drain region is centrally arranged. The second source/drain region is aligned with the first bottom source/drain region. A read port may be connected with the storage element, and may also be formed using VTFETs.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Randy W. Mann, Bipul C. Paul
  • Patent number: 10622375
    Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 14, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Seung Ju Chun, Yong Min Yoo, Jong Wan Choi, Young Jae Kim, Sun Ja Kim, Wan Gyu Lim, Yoon Ki Min, Hae Jin Lee, Tae Hee Yoo
  • Patent number: 10600791
    Abstract: A semiconductor memory device includes a word line buried in an upper portion of a substrate and extending in a first direction, and a word line contact plug connected to the word line. An end portion of the word line includes a contact surface exposed in the first direction, and the word line contact plug is connected to the contact surface.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Wan Kim, Keunnam Kim, Juik Lee
  • Patent number: 10586769
    Abstract: A technique relates to fabricating a semiconductor device. A contact trench is formed in an inter-level dielectric layer. The contact trench creates an exposed portion of a semiconductor substrate through the inter-level dielectric layer. A gate stack is on the semiconductor substrate, and the inter-level dielectric layer is adjacent to the gate stack and the semiconductor substrate. A source/drain region is formed in the contact trench such that the source/drain region is on the exposed portion of the semiconductor substrate. Tin is introduced in the source/drain region to form an alloyed layer on top of the source/drain region, and the alloyed layer includes the tin and a source/drain material of the source/drain region. A trench layer is formed in the contact trench such that the trench layer is on top of the alloyed layer. A metallic liner layer is formed on the trench layer and the inter-level dielectric layer.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Oleg Gluschenkov, Jiseok Kim, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi
  • Patent number: 10580733
    Abstract: Provided is an integrated circuit which includes: a plurality of conductive lines extending in a first horizontal direction on a plane separate from a gate line, and including first and second conductive lines; a source/drain contact having a bottom surface connected to a source/drain region, and including a lower source/drain contact and an upper source/drain contact which are connected to each other in a vertical direction; and a gate contact having a bottom surface connected to the gate line, and extending in the vertical direction, in which the upper source/drain contact is placed below the first conductive line, and the gate contact is placed below the second conductive line. A top surface of the lower source/drain contact may be larger than a bottom surface of the upper source/drain contact.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-hyung Kim, Jung-ho Do, Dae-young Moon, Sang-yeop Baeck, Jae-hyun Lim, Jae-seung Choi, Sang-shin Han
  • Patent number: 10559461
    Abstract: Methods are provided for conducting a deposition on a semiconductor substrate by selectively depositing a material on the substrate. The substrate has a plurality of substrate materials, each with a different nucleation delay corresponding to the material deposited thereon. Specifically, the nucleation delay associated with a first substrate material on which deposition is intended is less than the nucleation delay associated with a second substrate material on which deposition is not intended according to a nucleation delay differential, which degrades as deposition proceeds. A portion of the deposited material is etched to reestablish the nucleation delay differential between the first and the second substrate materials. The material is further selectively deposited on the substrate.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: February 11, 2020
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Kapu Sirish Reddy, Meliha Gozde Rainville, Nagraj Shankar, Dennis M. Hausmann, David Charles Smith, Karthik Sivaramakrishnan, David W. Porter
  • Patent number: 10546854
    Abstract: One illustrative method disclosed herein includes, among other things, forming a source/drain contact structure between two spaced-apart transistor gate structures, forming a non-uniform thickness layer of material on the upper surface of the gate cap layers and on the upper surface of the source/drain contact structure, wherein the non-uniform thickness layer of material is thicker above the gate cap layers than it is above the source/drain contact structure, forming an opening in the non-uniform thickness layer of material so as to expose at least a portion of the source/drain contact structure, and forming a V0 via that is conductively coupled to the exposed portion of the source/drain contact structure, the V0 via being at least partially positioned in the opening in the non-uniform thickness layer of material.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: January 28, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Xunyuan Zhang
  • Patent number: 10535603
    Abstract: A method includes depositing a dielectric structure on a first conductive structure, etching the dielectric structure to form a via opening, etching the dielectric structure to form a trench over the via opening, depositing a first protective layer on a bottom surface of the trench, filling the trench and the via opening with a second conductive structure, and removing the first protective layer to form an air gap between the second conductive structure and the dielectric structure.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10497793
    Abstract: A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 3, 2019
    Assignee: Taiwan Seminconductor Manufacturing Company Limited
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 10490566
    Abstract: A memory device includes a cell region and a peripheral circuit region adjacent the cell region. A plurality of gate electrode layers and insulating layers are stacked on the substrate in the cell region, and a plurality of circuit devices are in the peripheral circuit region. A first interlayer insulating layer is on the substrate in the peripheral circuit region and covers the plurality of circuit devices, and a second interlayer insulating layer is on the substrate in the cell region and the peripheral circuit region. A blocking layer is on the plurality of circuit devices between the first and second interlayer insulating layers. The blocking layer is on an upper surface, of the first interlayer insulating layer, and a side surface of the blocking layer is covered by the second interlayer insulating layer.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: November 26, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Seok Jung, Brad H. Lee, Sang Woo Jin
  • Patent number: 10396084
    Abstract: Active regions for planar transistor architectures may be patterned in one lateral direction, i.e., the width direction, on the basis of a single lithography process, followed by deposition and etch processes, thereby providing multiple width dimensions and multiple spaces or pitches with reduced process variability due to the avoidance of overlay errors typically associated with conventional approaches when patterning the width dimensions and spaces on the basis of a sequence of sophisticated lithography processes. Consequently, increased packing density, enhanced performance and reduced manufacturing costs may be achieved on the basis of process techniques as disclosed herein.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: August 27, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Nigel Chan, Nilesh Kenkare, Hongsik Yoon
  • Patent number: 10325995
    Abstract: Provided herewith are embodiments related to a semiconductor structure and a method for forming the semiconductor structure. A first spacer layer and a second spacer layer are formed opposite a major surface of a substrate. The second spacer layer is removed using the first spacer layer as a stop layer. The removal of the second spacer layer forms an air-gap spacer in an area previously occupied by the second spacer layer.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10283408
    Abstract: Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the methods, different, selectively etchable, dielectric materials are used above the gate level for: a dielectric cap above a gate; a dielectric spacer above a gate sidewall spacer and laterally surrounding the dielectric cap; and a stack of dielectric layer(s) that covers the dielectric cap, the dielectric spacer, and metal plugs positioned laterally adjacent to the dielectric spacer and above source/drain regions. Due to the different dielectric materials, subsequently formed gate and source/drain contacts are self-aligned in two dimensions to provide protection against the occurrence of opens between wires and/or vias in the first BEOL metal level and the contacts and to further provide protection against the occurrence of shorts between the gate contact and any metal plugs and between the source/drain contacts and the gate.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chanro Park, Andre Labonte, Lars Liebmann
  • Patent number: 10269808
    Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes a stack structure on the substrate. The stack structure includes a first insulating material and a second insulating material that is on the first insulating material. The semiconductor device includes a spacer that extends from a sidewall of the first insulating material of the stack structure to a portion of a sidewall of the second insulating material of the stack structure. Moreover, the semiconductor device includes a conductive line that is on the spacer. Methods of forming semiconductor devices are also provided.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: April 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Daeik Kim, Bong-Soo Kim, Jemin Park, Taejin Park, Yoosang Hwang
  • Patent number: 10269564
    Abstract: A method of fabricating a semiconductor device includes plasma etching a portion of a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate by applying a plasma to the plurality of metal dichalcogenide films. After plasma etching, a chalcogen is applied to remaining portions of the plurality of metal dichalcogenide films to repair damage to the remaining portions of the plurality of metal dichalcogenide films from the plasma etching. The chalcogen is S, Se, or Te.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: April 23, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Shih-Yen Lin, Kuan-Chao Chen, Si-Chen Lee, Samuel C. Pan
  • Patent number: 10242983
    Abstract: A semiconductor device includes a semiconductor fin arranged on a substrate, a gate stack arranged over a channel region of the fin, and a spacer arranged adjacent to the gate stack. A source/drain region is arranged in the fin the source/drain region having a cavity that exposes a portion of the semiconductor fin. An insulator layer is arranged over a portion of the fin, and a conductive contact material is arranged in the cavity and over portions of the source/drain region.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Chi-Chun Liu, Peng Xu, Jie Yang
  • Patent number: 10229918
    Abstract: Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first, a second, and a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a third set of lines in a direction perpendicular to the first and second set of lines; etching to define the third set of lines, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: March 12, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Atsushi Ogino
  • Patent number: 10217749
    Abstract: A manufacturing method of a semiconductor memory device includes the following steps. A semiconductor substrate having a memory cell region and a peripheral region defined thereon is provided. Bit line structures are formed on the memory cell region. At least one gate structure is formed on the peripheral region. A spacer layer is formed covering the semiconductor substrate, the gate structure, and the bit line structures. The spacer layer is partly disposed on the memory cell region and partly disposed on the peripheral region. A first etching process is performed to the spacer layer for removing a part of the spacer layer on the memory cell region. At least a part of the spacer layer remains on the memory cell region after the first etching process. A second etching process is performed after the first etching process for removing the spacer layer remaining on the memory cell region.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: February 26, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yu-Ching Chen, Shih-Fang Tzou, Kuei-Hsuan Yu, Hui-Ling Chuang
  • Patent number: 10211102
    Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a core region and a peripheral region, and prior to forming a metal silicide in the core region, forming a sidewall layer on opposite sides of a gate structure of a core region device. The sidewall layer includes sequentially, from the inside out, a silicon oxide layer, a first silicon nitride layer, a first silicon nitride layer, a second silicon oxide layer, and a second silicon nitride layer, or the sidewall layer includes, from inside out, a first silicon nitride layer and a second silicon nitride layer. The sidewall layer having such structure ensures that the formed metal silicide has a good morphology in the core region to achieve good device performance.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: February 19, 2019
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Jinshuang Zhang, Shengfen Chiu
  • Patent number: 10177242
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
  • Patent number: 10164034
    Abstract: A semiconductor device includes a fin structure, first and second gate structures, a source/drain region, a source/drain contact, a separator, a plug contacting the source/drain contact and a wiring contacting the plug. The fin structure protrudes from an isolation insulating layer and extends in a first direction. The first and second gate structures are formed over the fin structure and extend in a second direction crossing the first direction. The source/drain region is disposed between the first and second gate structures. The interlayer insulating layer is disposed over the fin structure, the first and second gate structures and the source/drain region. The first source/drain contact is disposed on the first source/drain region. The separator is disposed adjacent to the first source/drain contact layer. Ends of the first and second gate structures and an end of the source drain contact are in contact with a same face of the separator.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yi-Jyun Huang, Tung-Heng Hsieh, Bao-Ru Young
  • Patent number: 10083862
    Abstract: A method of forming a protective liner between a gate dielectric and a gate contact. The method may include; forming a finFET having a replacement metal gate (RMG) on one or more fins, the RMG includes a gate dielectric wrapped around a metal gate, an outer liner is on the sidewalls of the gate dielectric and on the fins; forming a gate contact trench by recessing the gate dielectric and the outer liner below a top surface of the metal gate in a gate contact region; forming a protective trench by further recessing the gate dielectric below a top surface of the outer liner; filling the protective trench with a protective liner; and forming a gate contact in the gate contact trench, where the protective liner is between the gate dielectric and the gate contact.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: September 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk D. Peterson, Junli Wang
  • Patent number: 10011920
    Abstract: An epitaxy method includes providing an exposed crystalline region of a substrate material. Silicon is epitaxially deposited on the substrate material in a low temperature process wherein a deposition temperature is less than 500 degrees Celsius. A source gas is diluted with a dilution gas with a gas ratio of dilution gas to source gas of less than 1000.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: July 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Alexander Reznicek, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 9960117
    Abstract: A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A dielectric cap layer is formed over the semiconductor substrate and air gaps are etched into the dielectric layer. The result is a bilayer cap air gap structure with effective electrical performance.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: May 1, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stephen M. Gates, Elbert E. Huang, Dimitri R. Kioussis, Christopher J. Penny, Deepika Priyadarshini
  • Patent number: 9934976
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer dielectric (ILD) disposed on a substrate, wherein a source/drain contact area is exposed, forming a rare earth metal layer on the source/drain contact area, forming a transition metal layer on the rare earth metal layer; and annealing the rare earth metal layer and the transition metal layer to form a metal silicide stack structure.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Matt Metz, Gilbert Dewey, Jack Kavalieros, Robert S Chau
  • Patent number: 9887159
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; forming an active device on the substrate; forming an interlayer dielectric (ILD) layer on the substrate and the active device; forming a mask layer on the ILD layer; removing part of the mask layer, part of the ILD layer, and part of the insulating layer to form a first contact hole; forming a patterned mask on the mask layer and into the first contact hole; and removing part of the mask layer and part of the ILD layer to form a second contact hole exposing part of the active device.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: February 6, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Mengkai Zhu
  • Patent number: 9859393
    Abstract: A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: January 2, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-suk Tak, Tae-jong Lee, Hyun-seung Kim, Bon-young Koo, Ki-yeon Park, Gi-gwan Park, Mi-seon Park