Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.

Abstract: A micro-electromechanical structure for modulating light beams includes multiple asymmetric deformable diffractive elements, each having an L-shaped cross section, split pedestal and flexible reflective member. The reflective member has an elongated shape, and a supported part and unsupported part. The split pedestal extends along the long dimension of the supported part of the reflective member and is anchored to a substrate which supports one or more electrodes or serves as an electrode. The diffractive element is movable between a non-energized position wherein the diffractive element acts to reflect a beam of light as a planar mirror, to an energized position wherein upon application of an electrostatic force, the diffractive element flexes independently about an axis parallel to the long dimension of each reflective member to vary a curvature of the reflective member to form a blazed grating.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first polysilicon structure over the substrate, wherein the first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure, wherein the first barrier layer has a non-uniform thickness. The semiconductor device further includes a second polysilicon structure over the first barrier layer, wherein the second polysilicon structure has a second grain size smaller than the first grain size.

Abstract: A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure comprises a channel element. The channel element comprises a substrate portion and a vertical channel portion. The vertical channel portion is adjoined on the substrate portion. The substrate portion and the vertical channel portion both comprise single crystal silicon.

Abstract: Plasma-assisted methods and apparatus are disclosed. The methods and apparatus can be used to provide activated species formed in a remote plasma unit to a reaction chamber to assist ignition of a plasma within a reaction chamber coupled to the remote plasma unit.

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

Abstract: A semiconductor device includes a semiconductor substrate, a field-effect transistor arranged at least partially on the semiconductor substrate and used in an analog circuit, and having a P-type gate electrode, an interlayer insulating film arranged on the field-effect transistor, and a hydrogen shielding metal or metallic film arranged on the interlayer insulting film and covering the P-type gate electrode and configured to shield hydrogen.

Abstract: A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.

Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.

Abstract: A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.

Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a substrate; forming a dummy gate structure including a dummy gate dielectric layer, an initial dummy gate electrode layer, and a first sidewall spacer; forming an isolation layer having a surface lower than or coplanar with the dummy gate structure; forming a dummy gate electrode layer having a surface lower than the isolation layer, and forming a first opening to expose a portion of the first sidewall spacer; forming a modified sidewall spacer from the exposed first sidewall spacer; forming a second opening by removing the dummy gate electrode layer; forming a third opening by removing the dummy gate dielectric layer and the modified sidewall spacer, where top of the third opening has a size larger than bottom of the third opening; and forming a gate structure in the third opening.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a first dielectric layer, a work function layer, and a gate electrode sequentially stacked over the substrate, the first dielectric layer is between the work function layer and the substrate, the work function layer is between the first dielectric layer and the gate electrode, the first dielectric layer has a thin portion and a thick portion, the thin portion is thinner than the thick portion and surrounds the thick portion. The semiconductor device structure includes. The semiconductor device structure includes an insulating layer over the substrate and wrapping around the gate stack. The thin portion is between the thick portion and the insulating layer.

Abstract: Embodiments of 3D memory devices having a pocket structure in memory strings and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a selective epitaxial layer on the substrate, a memory stack including interleaved conductive layers and dielectric layers on the selective epitaxial layer, and a memory string including a channel structure extending vertically in the memory stack and a pocket structure extending vertically in the selective epitaxial layer. The memory string includes a semiconductor channel extending vertically in the channel structure, and extending vertically and laterally in the pocket structure and in contact with the selective epitaxial layer.

Abstract: An image device includes a first active region and a second active region disposed on a substrate. Each of the first active region and the second active region includes a gate insulating layer disposed on the substrate and a gate electrode disposed on the gate insulating layer. At least one of the first active region and the second active region further includes a first passivation layer containing fluorine (F) disposed between the gate insulating layer and the gate electrode. A concentration of fluorine in the gate insulating layer is higher than a concentration of fluorine in the gate electrode.

Abstract: A buried channel MOSFET includes a dielectric layer, a gate and a buried channel region. The dielectric layer having a recess is disposed on a substrate. The gate is disposed in the recess, wherein the gate includes a first work function metal layer having a “-” shaped cross-sectional profile, and a minimum distance between each sidewalls of the first work function metal layer and the nearest sidewall of the recess is larger than zero. The buried channel region is located in the substrate right below the gate. The present invention provides a method of forming said buried channel MOSFET.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A method for forming a semiconductor structure is provided. The method includes: forming first and second hard mask layers and a target layer on a substrate; patterning the second hard mask layer to form patterned second hard masks including a second wide mask and second narrow masks; and forming spacers on sidewalls of the second wide mask and the second narrow masks. Then, a photoresist layer is formed to cover the second wide mask and the spacers on the sidewalls of the second wide mask. The second narrow masks and the photoresist layer are removed. And, the first hard mask layer is etched with the spacers and the second wide mask together as a mask to form patterned first hard masks on the target layer, wherein the spacers define a first line width, and the second wide mask and the pair of spacers define a second line width.

Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

Abstract: Methods for depositing a molybdenum nitride film on a surface of a substrate are disclosed. The methods may include: providing a substrate into a reaction chamber; and depositing a molybdenum nitride film directly on the surface of the substrate by performing one or more unit deposition cycles of cyclical deposition process, wherein a unit deposition cycle may include, contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, and contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor. Semiconductor device structures including a molybdenum nitride film are also disclosed.

Abstract: A semiconductor device includes a power switch circuit and a logic circuit. The semiconductor device includes a first dielectric layer and a thin film transistor (TFT) formed on the first dielectric layer. The TFT includes a semiconductor nano-sheet, a gate dielectric layer wrapping around a channel region of the semiconductor nano-sheet, and a gate electrode layer formed on the gate dielectric layer. The semiconductor nano-sheet is made of an oxide semiconductor material.

Abstract: In thickness/depth measurement of a wafer in etching, variation occurs in detected light quantity due to fluctuation of light quantity of a light source or fluctuation of air in a region through which light passes, and measurement accuracy of thickness/depth is reduced, and thus the total light quantity or average light quantity of an arbitrary wavelength is calculated from an optical spectrum measured at each time instant during etching, estimated total light quantity or estimated average light quantity at the present time, which is estimated using total light quantity or average light quantity measured prior to the present time, is calculated, a change rate, as a ratio of the total light quantity at the present time to the estimated total light quantity or a ratio of the average light quantity to the estimated average light quantity, is calculated, the calculated change rate is used to correct light quantity of each wavelength at the present time, and the corrected light quantity of each wavelength is used

Abstract: A method of forming a semiconductor device includes providing a structure that includes a substrate, a first fin and a second fin, a first gate structure engaging the first fin, and a second gate structure engaging the second fin; depositing a dielectric layer over the first and second gate structures; etching the dielectric layer, thereby forming a first gate contact opening exposing the first gate structure and a second gate contact opening exposing the second gate structure, wherein the first gate contact opening has a first length that is larger than a second length of the second gate contact opening; and filling the first and second gate contact openings with conductive material, thereby forming a first gate contact engaging the first gate structure and a second gate contact engaging the second gate structure.

Abstract: A semiconductor device of an embodiment includes: a semiconductor substrate; a first insulating layer provided on or above the semiconductor substrate; an aluminum layer provided on the first insulating layer; a second insulating layer provided on the first insulating layer, the second insulating layer covering a first region of a surface of the aluminum layer; and an aluminum oxide film provided on a second region other than the first region of the surface of the aluminum layer, the aluminum oxide film including ?-alumina as a main component, and a film thickness of the aluminum oxide film being equal to or larger than 0.5 nm and equal to or smaller than 3 nm.

Abstract: A device includes a first conductive via plug, a first electrode, a storage element, a second electrode, a spacer, a barrier structure, a first dielectric layer. The first electrode is over the first conductive via plug. The storage element is over the first electrode. The second electrode is over the storage element. The spacer has a bottom portion extending along a top surface of the first electrode and a standing portion extending from the bottom portion and along a sidewall of the second electrode. The barrier structure extends from the bottom portion of the spacer and along a sidewall of the standing portion of the spacer. The first dielectric layer is substantially conformally over the spacer and the barrier structure.

Abstract: A method of forming a semiconductor structure includes patterning a hard mask layer over a top surface of a substrate. The method also includes forming a first portion of one or more vertical fins below the patterned hard mask layer. The method further includes forming a top spacer on sidewalls of the hard mask layer and the first portion of the one or more vertical fins. The method further includes forming a second portion of the one or more vertical fins in the substrate below the top spacer and trimming sidewalls of the second portion of the one or more vertical fins. The method further includes forming an interfacial layer on the trimmed sidewalls of the second portion of the one or more vertical fins. The one or more vertical fins provide one or more vertical transport channels for one or more vertical transport field-effect transistors.

Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided at a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration higher than that of the semiconductor substrate, a trench penetrating the first semiconductor region and the second semiconductor layer, to reach the first semiconductor layer, and a gate electrode provided in the trench, via a gate insulating film. The trench has a sidewall that includes a terrace portion, surface roughness of the terrace portion being at most 0.1 nm.

Abstract: An integrated circuit device includes a conductive line formed on a substrate, an insulating spacer covering side walls of the conductive line and extending parallel with the conductive line, and a conductive plug that is spaced apart from the conductive line with the insulating spacer therebetween. The insulating spacer includes an insulating liner contacting the conductive line, an outer spacer contacting the conductive plug, and a barrier layer between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.

Abstract: Production of a transistor, the channel structure of which comprises at least one finned channel structure, the method comprising: forming, from a substrate (1), a molding block (3), forming, on the molding block, a thin layer (7) made from a given semiconductor or semi-metallic material, and consisting of one to ten atomic or molecular monolayers of two-dimensional crystal, withdrawing the molding block while retaining a portion (7a) of the thin layer extending against a lateral face of the molding block, said retained portion (7a) forming a fin that is capable of forming a channel structure of the transistor, producing a coating gate electrode against said fin.

Abstract: A radio frequency (RF) switch includes a phase-change material (PCM), a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM, a capacitive RF terminal, and an ohmic RF terminal. The capacitive RF terminal can include a first trench metal liner situated on a first passive segment of the PCM, and a dielectric liner separating the first trench metal liner from a first trench metal plug. The ohmic RF terminal can include a second trench metal liner situated on a second passive segment of the PCM, and a second trench metal plug ohmically connected to the second trench metal liner. Alternatively, the capacitive RF terminal and the ohmic RF terminal can include lower metal portions and upper metal portions. A MIM capacitor can be formed by the upper metal portion of the capacitive RF terminal, an insulator, and a patterned top plate.

Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening.

Abstract: Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.

Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.

Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.

Abstract: A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET).

Abstract: A radio frequency (RF) switch includes a phase-change material (PCM), a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM, a capacitive RF terminal, and an ohmic RF terminal. The capacitive RF terminal can include a first trench metal liner situated on a first passive segment of the PCM, and a dielectric liner separating the first trench metal liner from a first trench metal plug. The ohmic RF terminal can include a second trench metal liner situated on a second passive segment of the PCM, and a second trench metal plug ohmically connected to the second trench metal liner. Alternatively, the capacitive RF terminal and the ohmic RF terminal can include lower metal portions and upper metal portions. A MIM capacitor can be formed by the upper metal portion of the capacitive RF terminal, an insulator, and a patterned top plate.

Abstract: A method of forming tensilely strained n-type fin field effect transistors and compressively strained p-type fin field effect transistors on the same substrate is provided. The method includes forming a pair of adjacent semiconductor mandrels on a semiconductor etch-stop layer, and forming a fill layer on the adjacent semiconductor mandrels and semiconductor etch-stop layer. The method further includes removing a portion of the fill layer to expose one of the adjacent mandrels, and forming a fin on each of the sidewalls of the pair of adjacent semiconductor mandrels. The method further includes forming an occlusion layer on the fins and one of the pair of semiconductor mandrels, and removing another portion of the fill layer to expose the other of the pair of adjacent semiconductor mandrels. The method further includes forming another fin on each of the sidewalls of the other of the pair of adjacent semiconductor mandrels.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.

Abstract: An semiconductor device capable of suppressing an increase in layout area can be provided. According to one embodiment, the semiconductor device comprises a transistor including a drain formed in a main surface portion of the semiconductor substrate, a source formed in a main surface portion, and a gate for controlling the current between the drain and the source, a drain wiring connected to the drain through the contact, and a passing wire disposed between the source wiring connected to the source through the contact and insulated from the drain, the source, and the gate.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extending above an isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and the top surface of the capping layer is higher than the top surface of the first fin structure and the top surface of the second fin structure. The semiconductor device structure includes a first gate structure formed over first fin structure, and a second gate structure formed over the second fin structure. The first gate structure and the second gate structure are separated by the dummy fin structure and the capping layer.

Abstract: A semiconductor device includes a vertical transistor on a substrate. The vertical transistor includes at least one fin. A bottom source/drain is disposed on the substrate and around the at least one fin. A spacer layer is disposed on the bottom source/drain and around the at least one fin. A gate structure is disposed on the spacer layer and around the at least one fin. The gate length is the same or substantially the same on each side of the at least one fin.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.

Abstract: Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.

Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

Abstract: A process of forming a field effect transistor is disclosed. The process includes steps of depositing a first silicon nitride (SiN) film on a semiconductor layer by a low pressure chemical vapor deposition (LPCVD) technique; depositing a second SiN film on the first SiN film by plasma assisted chemical vapor deposition (p-CVD) technique; preparing a photoresist mask on the second SiN film, the photoresist mask having an opening in a position corresponding to the gate electrode; dry-etching the second SiN film and the first SiN film continuously in a portion of the opening in the photoresist mask to form an opening in the first SiN film and an opening in the second SiN film, the openings in the first and second SiN films exposing the semiconductor layer; and filling at least the opening in the first SiN film by the gate electrode. A feature of the process is that the opening in the first SiN film has an inclined side against the semiconductor layer and gradually widens from the semiconductor layer.

Abstract: A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.

Abstract: A method for manufacturing an electrode including the following steps is provided. A conductive layer is formed on a base material. A radio frequency physical vapor deposition (RF PVD) transition metal compound layer is formed on the conductive layer by using a RF PVD. A sacrificial layer is formed on the RF PVD transition metal compound layer. A planarization process is performed to remove the sacrificial layer and a portion of the RF PVD transition metal compound layer.