Insulated Gate Formation Patents (Class 438/585)
  • Patent number: 12218062
    Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.
    Type: Grant
    Filed: November 20, 2023
    Date of Patent: February 4, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun Hyoung Kim, Young-Jin Kwon, Geun Won Lim
  • Patent number: 12218283
    Abstract: An array substrate and a display panel are provided, the array substrate is disposed on the base substrate, and a passivation layer is formed on a side of the array substrate layer away from the base substrate. The passivation layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked in sequence, the first dielectric layer is disposed close to the array layer and the third dielectric layer is disposed away from the array layer, a refractive index of the first dielectric layer is different from a refractive index of the second dielectric layer, and the refractive index of the second dielectric layer is different from a refractive index of the third dielectric layer.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: February 4, 2025
    Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Tsunglung Chang, Aoqi Song, Ting Zhang
  • Patent number: 12218193
    Abstract: An integrated circuit (IC) device includes a first region and a second region adjacent to each other along a first direction on a substrate, fin patterns in each of the first and second regions extending along a second direction perpendicular to the first direction; gate electrodes extending along the first direction and intersecting the fin patterns; and an isolation region between the first and second regions, a bottom of the isolation region having a non-uniform height relative to a bottom of the substrate.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: February 4, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-hyun Park, Kye-hyun Baek, Yong-ho Jeon, Cheol Kim, Sung-il Park, Yun-il Lee, Hyung-suk Lee
  • Patent number: 12211750
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.
    Type: Grant
    Filed: June 24, 2022
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung-Jung Chang
  • Patent number: 12183580
    Abstract: The present invention is related to a method for fabricating a semiconductor device capable of forming fine patterns. The method for fabricating the semiconductor device according to the present invention may comprise forming an etch mask layer on an etch target layer; forming a spacer structure in which first spacers and second spacers are alternately disposed and spaced apart from each other on the etch mask layer; forming first spacer lines through selective etching of the first spacers; forming second spacer lines through selective etching of the second spacers; and etching the etch target layer to form a plurality of fine line patterns using the first and second spacer lines.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: December 31, 2024
    Assignee: SK hynix Inc.
    Inventors: Ji Hoon Kim, Jae Han Park, Chang Hun Lee
  • Patent number: 12183833
    Abstract: A flash memory device is provided. The flash memory device includes a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, a first polycrystalline silicon layer and a second polycrystalline silicon layer. The first dielectric layer is formed on the substrate located in a first region of a peripheral region, the second dielectric layer is formed on the substrate located in a second region of the peripheral region, and the third dielectric layer is formed on the substrate located in an array region. A bottom surface of the third dielectric layer is lower than a bottom surface of the second dielectric layer. The first polycrystalline silicon layer is formed on the first and the second dielectric layers. The second polycrystalline silicon layer is formed on the third dielectric layer.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: December 31, 2024
    Assignee: Winbond Electronics Corp.
    Inventors: Cheng-Ta Yang, Lu-Ping Chiang
  • Patent number: 12167596
    Abstract: A three-dimensional semiconductor device includes a first substrate; a plurality of first transistors on the first substrate; a second substrate on the plurality of first transistors; a plurality of second transistors on the second substrate; and an interconnection portion electrically connecting the plurality of first transistors and the plurality of second transistors. Each of the plurality of first transistors includes a first gate insulating film on the first substrate and having a first hydrogen content. Each of the plurality of second transistors includes a second gate insulating film on the second substrate and having a second hydrogen content. The second hydrogen content is greater than the first hydrogen content.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: December 10, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seungha Oh, Weonhong Kim, Hoonjoo Na
  • Patent number: 12166105
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a first conductive material and a second conductive material disposed over the semiconductor substrate and the first dielectric layer. The semiconductor device structure further includes a second dielectric layer surrounding the first conductive material and the second conductive material and an insulating structure over the semiconductor substrate. The insulating structure is disposed between the first conductive material and the second conductive material. The insulating structure comprises a material different from the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: October 19, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsuan Hsiao, Shu-Yuan Ku, Chih-Chang Hung, I-Wei Yang, Chih-Ming Sun
  • Patent number: 12142310
    Abstract: A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: November 12, 2024
    Assignee: Kepler Computing Inc.
    Inventors: Noriyuki Sato, Tanay Gosavi, Niloy Mukherjee, Amrita Mathuriya, Rajeev Kumar Dokania, Sasikanth Manipatruni
  • Patent number: 12142671
    Abstract: A method for manufacturing a semiconductor device and a semiconductor device, the method including forming an active pattern on a substrate such that the active pattern includes sacrificial patterns and semiconductor patterns alternately and repeatedly stacked on the substrate; and forming first spacer patterns at both sides of each of the sacrificial patterns by performing an oxidation process, wherein the first spacer patterns correspond to oxidized portions of each of the sacrificial patterns, wherein the sacrificial patterns include a first semiconductor material containing impurities, wherein the semiconductor patterns include a second semiconductor material different from the first semiconductor material, and wherein the impurities include an element different from semiconductor elements of the first semiconductor material and the second semiconductor material.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: November 12, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong Chan Suh, Sangmoon Lee, Yihwan Kim, Woo Bin Song, Dongsuk Shin, Seung Ryul Lee
  • Patent number: 12132054
    Abstract: Provided is a manufacturing method of an electronic device, including forming a circuit layer on a base layer, disposing a light emitting element for attachment over the circuit layer, disposing an insulating layer between the light emitting element and the circuit layer, and drying the insulation layer to attach the light emitting element with the insulating layer and the circuit layer.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: October 29, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jangyeol Yoon, JaeMin Shin, Jongho Hong
  • Patent number: 12125851
    Abstract: The embodiments of the disclosure provide a FinFET. The FinFET includes a substrate, a first gate stack and a second gate stack. The substrate has a first fin and a second fin. The first gate stack is across the first fin and extends along a widthwise direction of the first fin. The second gate stack is across the second fin and extends along a widthwise direction of the second fin. A bottommost surface of the first gate stack is lower than a bottommost surface of the second gate stack, and a first gate height of the first gate stack directly on the first fin is substantially equal to a second gate height of the second gate stack directly on the second fin.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: October 22, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Wei Tseng, Jiun-Ming Kuo, Yuan-Ching Peng, Kuo-Yi Chao
  • Patent number: 12125710
    Abstract: A substrate processing method includes: (a) providing a substrate including an etching target film, a first mask formed on the etching target film, and a second mask formed on the first mask, the second mask being different in film type from the first mask and having an opening; (b) selectively etching the first mask with respect to the second mask, thereby forming an opening in the first mask such that an opening dimension of at least a portion of the first mask is larger than an opening dimension of a bottom of the second mask; and (c) etching the etching target film.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: October 22, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Sho Kumakura, Yusuke Takino
  • Patent number: 12112940
    Abstract: In exemplary embodiment, a method of top-selective deposition using a flowable carbon-based film on a substrate having a recess defined by a top surface, sidewall, and a bottom, includes steps of: (i) depositing a flowable carbon-based film in the recess of the substrate in a reaction space until a thickness of the flowable carbon-based film in the recess reaches a predetermined thickness, and then stopping the deposition step; and (ii) exposing the carbon-based film to a nitrogen plasma in an atmosphere substantially devoid of hydrogen and oxygen so as to redeposit a carbon-based film selectively on the top surface.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: October 8, 2024
    Assignee: ASM IP Holding B.V.
    Inventor: Timothee Julien Vincent Blanquart
  • Patent number: 12112953
    Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: October 8, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
  • Patent number: 12104108
    Abstract: The present disclosure is directed to etching compositions that are useful, e.g., for selectively removing tungsten (W) and/or titanium nitride (TiN) from a semiconductor substrate as an intermediate step in a multistep semiconductor manufacturing process.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: October 1, 2024
    Assignee: Fujifilm Electronic Materials U.S.A., Inc.
    Inventors: Tomonori Takahashi, Frank Gonzalez
  • Patent number: 12100627
    Abstract: A method of manufacturing a semiconductor device having metal gates and the semiconductor device are disclosed. The method comprises providing a first sacrificial gate associated with a first conductive type transistor and a second sacrificial gate associated with a second conductive type transistor disposed over the substrate, wherein the first conductive type and the second conductive type are complementary; replacing the first sacrificial gate with a first metal gate structure; forming a patterned dielectric layer and/or a patterned photoresist layer to cover the first metal gate structure; and replacing the second sacrificial gate with a second metal gate structure. The method can improve gate height uniformity during twice metal gate chemical mechanical polish processes.
    Type: Grant
    Filed: March 8, 2023
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Huang Chen, Yen-Yu Chen, Po-An Chen, Soon-Kang Huang
  • Patent number: 12080712
    Abstract: A semiconductor device includes a plurality of semiconductor patterns that are sequentially stacked and spaced apart from each other on a substrate, and a gate electrode on the plurality of semiconductor patterns. The gate electrode includes a capping pattern and a work function pattern that are sequentially stacked on the plurality of semiconductor patterns. The capping pattern includes a first metal nitride layer including a first metal element, and a second metal nitride layer including a second metal element whose work function is greater than a work function of the first metal element. The first metal nitride layer is disposed between the second metal nitride layer and the plurality of semiconductor patterns. The first metal nitride layer is thinner than the second metal nitride layer.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: September 3, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byounghoon Lee, Jongho Park, Wandon Kim, Sangjin Hyun
  • Patent number: 12062537
    Abstract: A method for depositing a carbon ashable hard mask layer on a substrate includes a) arranging a substrate in a processing chamber; b) setting chamber pressure in a predetermined pressure range; c) setting a substrate temperature in a predetermined temperature range from ?20° C. to 200° C.; d) supplying a gas mixture including hydrocarbon precursor and one or more other gases; and e) striking plasma by supplying RF plasma power for a first predetermined period to deposit a carbon ashable hard mask layer on the substrate.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: August 13, 2024
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Jun Xue, Mary Anne Manumpil, Shih-Ked Lee, Samantha SiamHwa Tan
  • Patent number: 12051746
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a first dielectric layer, a work function layer, and a gate electrode sequentially stacked over the substrate, the first dielectric layer has a thin portion and a thick portion, the thin portion is thinner than the thick portion and surrounds the thick portion, and the first dielectric layer is a single-layer structure. The semiconductor device structure includes an insulating layer over the substrate and wrapping around the gate stack. The thin portion is between the thick portion and the insulating layer.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: July 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Liang Cheng, Ziwei Fang
  • Patent number: 12051693
    Abstract: A method for manufacturing a semiconductor structure is provided. The method includes forming a plurality of fin structures extending along a first direction over a substrate, forming a low-k isolation strip over the substrate, the low-k isolation strip extending along the first direction and between the plurality of fin structures; and forming a high-k isolation strip on top of the low-k isolation strip.
    Type: Grant
    Filed: November 1, 2021
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shi Ning Ju, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang, Kuan-Ting Pan, Zhi-Chang Lin
  • Patent number: 12046657
    Abstract: A method of making a semiconductor device includes forming first and second dummy gates over a substrate. The method includes removing the first and second dummy gates to define first and second openings. The method includes depositing a continuous gate dielectric layer in the first opening and the second opening. The method includes depositing a continuous capping layer on the gate dielectric layer, wherein the capping layer includes TaC. The method further includes depositing a continuous barrier layer on the capping layer, wherein the barrier layer includes TaC and a second material. The method includes depositing a first work function layer over the barrier layer in the first opening. The method includes depositing a second work function layer over the barrier layer in the second opening. The method includes depositing a continuous metal layer over each of the first work function layer and the second work function layer.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: July 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hsueh Wen Tsau
  • Patent number: 12027595
    Abstract: Embodiments relate to a method for fabricating a semiconductor structure, a semiconductor structure, and a peripheral circuit. The method for fabricating a semiconductor structure includes: providing a substrate; forming a gate initial structure and a residue on the substrate; and removing the residue by means of a first cleaning liquid. The first cleaning liquid is capable of inhibiting the residue from undergoing a hydrolysis reaction.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: July 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jie Bai, Kang You
  • Patent number: 12020990
    Abstract: A method for microfabrication of a three dimensional transistor stack having gate-all-around field-effect transistor devices. The channels hang between source/drain regions. Each channel is selectively deposited with layers of materials designed for adjusting the threshold voltage of the channel. The layers may be oxides, high-k materials, work function materials and metallization. The three dimensional transistor stack forms an array of high threshold voltage devices and low threshold voltage devices in a single package.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: June 25, 2024
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Kandabara Tapily, Lars Liebmann, Daniel Chanemougame, Mark Gardner, H. Jim Fulford, Anton J. Devilliers
  • Patent number: 12015070
    Abstract: A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: June 18, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
  • Patent number: 12004381
    Abstract: A display apparatus includes a base substrate, an active pattern disposed on the base substrate, a gate insulation layer disposed on the active pattern, a gate electrode disposed on the gate insulation layer and overlapping the active pattern, a first insulation layer disposed on the gate electrode and having a total amount of hydrogen of about 5 atomic percent (at. %) to about 30 at. %, and a source electrode and a drain electrode which are disposed on the first insulation layer and are electrically connected to the active pattern.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: June 4, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yung Bin Chung, Yeoungkeol Woo, Kwanghyun Kim, Sangwoo Sohn, Dokeun Song, Sangwook Lee, Heon Sik Ha
  • Patent number: 12002871
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first fin structure and a second fin structure over a substrate. The method includes forming a dielectric layer over the substrate, the first fin structure, and the second fin structure. The method includes forming a first work function layer in the first trench and the second trench. The method includes forming a first mask layer over the first work function layer in the first trench. The method includes removing the first work function layer exposed by the first mask layer. The method includes removing the first mask layer. The method includes forming a first gate electrode in the first trench and a second gate electrode in the second trench. The method includes forming a first hard mask layer in the first trench and a second hard mask layer in the second trench.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wen-Han Fang, Chang-Yin Chen, Ming-Chia Tai, Po-Chi Wu
  • Patent number: 11972950
    Abstract: There is provided a semiconductor device, a hydrogen concentration distribution has a hydrogen concentration peak, a helium concentration distribution has a helium concentration peak, and a donor concentration distribution has a first donor concentration peak and a second donor concentration peak; the hydrogen concentration peak and the first donor concentration peak are located at a first depth, and the helium concentration peak and the second donor concentration peak are located at a second depth; each concentration peak has an upward slope; and a value which is obtained by normalizing a gradient of the upward slope of the second donor concentration peak by a gradient of the upward slope of the helium concentration peak is smaller than a value which is obtained by normalizing a gradient of the upward slope of the first donor concentration peak by a gradient of the upward slope of the hydrogen concentration peak.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: April 30, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Misaki Meguro, Takashi Yoshimura, Hiroshi Takishita, Naoko Kodama, Yasunori Agata
  • Patent number: 11955547
    Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Jen Pan, Yu-Hsien Lin, Hsiang-Ku Shen, Wei-Han Fan, Yun Jing Lin, Yimin Huang, Tzu-Chung Wang
  • Patent number: 11923437
    Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsu-Hui Su, Chun-Hsiang Fan, Yu-Wen Wang, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11916134
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, a drift layer of the first conductivity type coupled to the semiconductor substrate, a fin array having a first row of fins and a second row of fins on the drift layer, and a space between the first row of fins and the second row of fins. The first row of fins includes a plurality of first elongated fins arranged in parallel to each other along a first row direction and separated by a first distance, and the second row of fins includes a plurality of second elongated fins arranged in parallel to each other along a second row direction and separated by a second distance.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: February 27, 2024
    Assignee: NEXGEN POWER SYSTEMS, INC.
    Inventors: Clifford Drowley, Ray Milano, Subhash Srinivas Pidaparthi, Andrew P. Edwards
  • Patent number: 11854814
    Abstract: An embodiment method includes: forming a gate stack over a channel region; growing a source/drain region adjacent the channel region; depositing a first ILD layer over the source/drain region and the gate stack; forming a source/drain contact through the first ILD layer to physically contact the source/drain region; forming a gate contact through the first ILD layer to physically contact the gate stack; performing an etching process to partially expose a first sidewall and a second sidewall, the first sidewall being at a first interface of the source/drain contact and the first ILD layer, the second sidewall being at a second interface of the gate contact and the first ILD layer; forming a first conductive feature physically contacting the first sidewall and a first top surface of the source/drain contact; and forming a second conductive feature physically contacting the second sidewall and a second top surface of the gate contact.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Guan-Ren Wang, Ching-Feng Fu
  • Patent number: 11830889
    Abstract: A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate, wherein the isolation feature is adjacent to the channel. The low noise device further includes a spacer surrounding a portion of the gate stack, wherein an edge of the gate stack is spaced from an edge of the isolation feature adjacent to the spacer by a distance ranging from a minimum spacing distance to about 0.3 microns (?m).
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Victor Chiang Liang, Fu-Huan Tsai, Chi-Feng Huang, Yu-Lin Wei, Fang-Ting Kuo, Meng-Chang Ho
  • Patent number: 11756798
    Abstract: The present application provides a method for improving the metal work function boundary effect in FinFET process, the method comprises steps of: depositing a first TiN layer on four fin structures. The first TiN layer has no gap between the second and the third fin structures; removing the first TiN layer up to a first distance from the midline between the second and third fin structures at the second fin structure side; depositing a second TiN layer; removing the second and first TiN layers from second fin structure. The thickness of the TiN layer at the bottom edge of the fin structure at the later structure of the ultra-low threshold voltage P-type transistor will be smaller from this process. Thus formed TiN layer is less prone to a bottom undercut during etching, thereby reducing the metal boundary effect and increasing of the threshold voltage of the device.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: September 12, 2023
    Assignee: Shanghai Huali Integrated Circuit Corporation
    Inventor: Wenyin Weng
  • Patent number: 11758724
    Abstract: A memory device includes a substrate, a laminated structure and a memory string. The laminated structure is disposed on the substrate. The laminated structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked along a first direction. The memory string is accommodated in the laminated structure along the first direction. The memory string includes a memory layer and a channel layer, and the memory layer is disposed between the laminated structure and the channel layer. At least a portion of the memory layer and the insulating layers are overlapped along the first direction.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: September 12, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Guan-Wei Wu, Yao-Wen Chang, I-Chen Yang
  • Patent number: 11749739
    Abstract: A field-effect transistor (FET) device having a modulated threshold voltage (Vt) includes a source electrode, a drain electrode, a channel region extending between the source electrode and the drain electrode, and a gate stack on the channel region. The gate stack includes an ultrathin dielectric dipole layer on the channel region configured to shift the modulated Vt in a first direction, a high-k (HK) insulating layer on the ultrathin dielectric dipole layer, and a doped gate metal layer on the HK insulating layer configured to shift the modulated Vt in a second direction.
    Type: Grant
    Filed: August 6, 2021
    Date of Patent: September 5, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wei-E Wang, Mark S. Rodder
  • Patent number: 11739432
    Abstract: A radiation-assisted (typically solar-assisted) electrolyzer cell and panel for high-efficiency hydrogen production comprises a photoelectrode and electrode pair, with said photoelectrode comprising either a photoanode electrically coupled to a cathode shared with an anode, or a photocathode electrically coupled to an anode shared with a cathode; electrolyte; gas separators; all within a container divided into two chambers by said shared cathode or shared anode, and at least a portion of which is transparent to the electromagnetic radiation required by said photoanode (or photocathode) to apply photovoltage to a shared cathode (or anode) that increases the electrolysis current and hydrogen production.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: August 29, 2023
    Assignee: Nanoptek Corporation
    Inventor: John M. Guerra
  • Patent number: 11735658
    Abstract: A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: August 22, 2023
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Wenyu Xu
  • Patent number: 11721702
    Abstract: A fin transistor structure is provided. The fin transistor structure includes a first substrate. An insulation layer is disposed on the first substrate. A plurality of fin structures are disposed on the insulation layer. A supporting dielectric layer fixes the fin structures at the fin structures at waist parts thereof. A gate structure layer is disposed on the supporting dielectric layer and covers a portion of the fin structures.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: August 8, 2023
    Assignee: United Microelectronics Corp.
    Inventors: Sheng-Yao Huang, Yu-Ruei Chen, Chung-Liang Chu, Zen-Jay Tsai, Yu-Hsiang Lin
  • Patent number: 11690213
    Abstract: A semiconductor device includes a gate structure on a substrate, first and second spacer structures on first and second sidewalls, respectively, opposite to each other of the gate structure, and first and second source/drain layers at upper portions of the substrate adjacent to the first and second sidewalls, respectively, of the gate structure. An upper surface of the gate structure has a height with reference to an upper surface of the substrate being a base level decreasing from a central portion to the first sidewall and substantially constant from the central portion to the second sidewall.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: June 27, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongkyun Lim, Youngsin Kim, Kijin Park, Hoju Song, Dongkwan Yang, Sangho Yun, Gyuhyun Lee, Jieun Lee, Seunguk Han, Yoongi Hong
  • Patent number: 11681155
    Abstract: A micro-electromechanical structure for modulating light beams includes multiple asymmetric deformable diffractive elements, each having an L-shaped cross section, split pedestal and flexible reflective member. The reflective member has an elongated shape, and a supported part and unsupported part. The split pedestal extends along the long dimension of the supported part of the reflective member and is anchored to a substrate which supports one or more electrodes or serves as an electrode. The diffractive element is movable between a non-energized position wherein the diffractive element acts to reflect a beam of light as a planar mirror, to an energized position wherein upon application of an electrostatic force, the diffractive element flexes independently about an axis parallel to the long dimension of each reflective member to vary a curvature of the reflective member to form a blazed grating.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: June 20, 2023
    Assignee: Teledyne Micralyne Inc.
    Inventors: Glen Fitzpatrick, John Harley
  • Patent number: 11676856
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first polysilicon structure over the substrate, wherein the first polysilicon structure has a first grain size. The semiconductor device further includes a first barrier layer over the first polysilicon structure, wherein the first barrier layer has a non-uniform thickness. The semiconductor device further includes a second polysilicon structure over the first barrier layer, wherein the second polysilicon structure has a second grain size smaller than the first grain size.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: J. J. Lee, Chun-Tse Tsai, M. C. Hang
  • Patent number: 11626517
    Abstract: A semiconductor structure and a manufacturing method for the same are provided. The semiconductor structure comprises a channel element. The channel element comprises a substrate portion and a vertical channel portion. The vertical channel portion is adjoined on the substrate portion. The substrate portion and the vertical channel portion both comprise single crystal silicon.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: April 11, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Erh-Kun Lai
  • Patent number: 11615970
    Abstract: Plasma-assisted methods and apparatus are disclosed. The methods and apparatus can be used to provide activated species formed in a remote plasma unit to a reaction chamber to assist ignition of a plasma within a reaction chamber coupled to the remote plasma unit.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: March 28, 2023
    Assignee: ASM IP Holding B.V.
    Inventor: Hiroo Sekiguchi
  • Patent number: 11600524
    Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: March 7, 2023
    Assignee: Intel Corporation
    Inventors: Mark T. Bohr, Tahir Ghani, Nadia M. Rahhal-Orabi, Subhash M. Joshi, Joseph M. Steigerwald, Jason W. Klaus, Jack Hwang, Ryan Mackiewicz
  • Patent number: 11587869
    Abstract: A semiconductor device includes a semiconductor substrate, a field-effect transistor arranged at least partially on the semiconductor substrate and used in an analog circuit, and having a P-type gate electrode, an interlayer insulating film arranged on the field-effect transistor, and a hydrogen shielding metal or metallic film arranged on the interlayer insulting film and covering the P-type gate electrode and configured to shield hydrogen.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: February 21, 2023
    Assignee: ABLIC INC.
    Inventors: Hisashi Hasegawa, Takeshi Koyama, Shinjiro Kato, Kohei Kawabata
  • Patent number: 11575008
    Abstract: A method of forming a semiconductor arrangement includes forming a gate dielectric layer over a semiconductor layer. A gate electrode layer is formed over the gate dielectric layer. A first gate mask is formed over the gate electrode layer. The gate electrode layer is etched using the first gate mask as an etch template to form a first gate electrode. A first dopant is implanted into the semiconductor layer using the first gate mask and the first gate electrode as an implantation template to form a first doped region in the semiconductor layer.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: February 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yun-Chi Wu, Tsung-Yu Yang, Cheng-Bo Shu, Chien Hung Liu
  • Patent number: 11575042
    Abstract: A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: February 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Xin Miao, Chen Zhang, Kangguo Cheng, Wenyu Xu
  • Patent number: 11532718
    Abstract: A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T1 of the cap portion is greater than a thickness T2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hsuan Liao, Chih-Chung Chang, Chun-Heng Chen, Jiun-Ming Kuo
  • Patent number: 11515400
    Abstract: A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a substrate; forming a dummy gate structure including a dummy gate dielectric layer, an initial dummy gate electrode layer, and a first sidewall spacer; forming an isolation layer having a surface lower than or coplanar with the dummy gate structure; forming a dummy gate electrode layer having a surface lower than the isolation layer, and forming a first opening to expose a portion of the first sidewall spacer; forming a modified sidewall spacer from the exposed first sidewall spacer; forming a second opening by removing the dummy gate electrode layer; forming a third opening by removing the dummy gate dielectric layer and the modified sidewall spacer, where top of the third opening has a size larger than bottom of the third opening; and forming a gate structure in the third opening.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: November 29, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Ruizhi Tang, Jinyu Fu, Lin Liu, Bo Li, Peng Yang, Haojun Huang, Jialei Liu