Insulated Gate Formation Patents (Class 438/585)
  • Patent number: 11056395
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su
  • Patent number: 11004953
    Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Rinus Tek Po Lee, Hui Zang, Jiehui Shu, Hong Yu, Wei Hong
  • Patent number: 10998423
    Abstract: Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Van H. Le, Scott B. Clendenning, Martin M. Mitan, Szuya S. Liao
  • Patent number: 10971370
    Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
  • Patent number: 10971594
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Patent number: 10957696
    Abstract: A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET).
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • Patent number: 10937960
    Abstract: A radio frequency (RF) switch includes a phase-change material (PCM), a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM, a capacitive RF terminal, and an ohmic RF terminal. The capacitive RF terminal can include a first trench metal liner situated on a first passive segment of the PCM, and a dielectric liner separating the first trench metal liner from a first trench metal plug. The ohmic RF terminal can include a second trench metal liner situated on a second passive segment of the PCM, and a second trench metal plug ohmically connected to the second trench metal liner. Alternatively, the capacitive RF terminal and the ohmic RF terminal can include lower metal portions and upper metal portions. A MIM capacitor can be formed by the upper metal portion of the capacitive RF terminal, an insulator, and a patterned top plate.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: March 2, 2021
    Assignee: Newport Fab, LLC
    Inventors: Gregory P. Slovin, Nabil El-Hinnawy, Jefferson E. Rose, David J. Howard
  • Patent number: 10879132
    Abstract: A method of forming tensilely strained n-type fin field effect transistors and compressively strained p-type fin field effect transistors on the same substrate is provided. The method includes forming a pair of adjacent semiconductor mandrels on a semiconductor etch-stop layer, and forming a fill layer on the adjacent semiconductor mandrels and semiconductor etch-stop layer. The method further includes removing a portion of the fill layer to expose one of the adjacent mandrels, and forming a fin on each of the sidewalls of the pair of adjacent semiconductor mandrels. The method further includes forming an occlusion layer on the fins and one of the pair of semiconductor mandrels, and removing another portion of the fill layer to expose the other of the pair of adjacent semiconductor mandrels. The method further includes forming another fin on each of the sidewalls of the other of the pair of adjacent semiconductor mandrels.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: December 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kangguo Cheng
  • Patent number: 10868133
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ruei Yeh, Chih-Lin Wang, Kang-Min Kuo
  • Patent number: 10833011
    Abstract: An semiconductor device capable of suppressing an increase in layout area can be provided. According to one embodiment, the semiconductor device comprises a transistor including a drain formed in a main surface portion of the semiconductor substrate, a source formed in a main surface portion, and a gate for controlling the current between the drain and the source, a drain wiring connected to the drain through the contact, and a passing wire disposed between the source wiring connected to the source through the contact and insulated from the drain, the source, and the gate.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: November 10, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Mitsuhiro Hotta
  • Patent number: 10825918
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extending above an isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and the top surface of the capping layer is higher than the top surface of the first fin structure and the top surface of the second fin structure. The semiconductor device structure includes a first gate structure formed over first fin structure, and a second gate structure formed over the second fin structure. The first gate structure and the second gate structure are separated by the dummy fin structure and the capping layer.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: November 3, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Kuan-Ting Pan, Chih-Hao Wang, Shi-Ning Ju
  • Patent number: 10796967
    Abstract: A semiconductor device includes a vertical transistor on a substrate. The vertical transistor includes at least one fin. A bottom source/drain is disposed on the substrate and around the at least one fin. A spacer layer is disposed on the bottom source/drain and around the at least one fin. A gate structure is disposed on the spacer layer and around the at least one fin. The gate length is the same or substantially the same on each side of the at least one fin.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10741569
    Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
  • Patent number: 10734287
    Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10714537
    Abstract: Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 14, 2020
    Assignee: Nantero, Inc.
    Inventor: Claude L. Bertin
  • Patent number: 10672778
    Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
  • Patent number: 10665464
    Abstract: A process of forming a field effect transistor is disclosed. The process includes steps of depositing a first silicon nitride (SiN) film on a semiconductor layer by a low pressure chemical vapor deposition (LPCVD) technique; depositing a second SiN film on the first SiN film by plasma assisted chemical vapor deposition (p-CVD) technique; preparing a photoresist mask on the second SiN film, the photoresist mask having an opening in a position corresponding to the gate electrode; dry-etching the second SiN film and the first SiN film continuously in a portion of the opening in the photoresist mask to form an opening in the first SiN film and an opening in the second SiN film, the openings in the first and second SiN films exposing the semiconductor layer; and filling at least the opening in the first SiN film by the gate electrode. A feature of the process is that the opening in the first SiN film has an inclined side against the semiconductor layer and gradually widens from the semiconductor layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: May 26, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Tomohiro Yoshida
  • Patent number: 10658173
    Abstract: A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 19, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Ching-Pin Hsu
  • Patent number: 10636967
    Abstract: A method for manufacturing an electrode including the following steps is provided. A conductive layer is formed on a base material. A radio frequency physical vapor deposition (RF PVD) transition metal compound layer is formed on the conductive layer by using a RF PVD. A sacrificial layer is formed on the RF PVD transition metal compound layer. A planarization process is performed to remove the sacrificial layer and a portion of the RF PVD transition metal compound layer.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: April 28, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Yi-Chung Chen, Cheng-An Peng, Shuo-Che Chang, Sung-Ying Wen
  • Patent number: 10629695
    Abstract: A semiconductor device includes a metal gate on a substrate, a polysilicon layer on the metal gate, a hard mask on the polysilicon layer, and a source/drain region adjacent to two sides of the metal gate. Preferably, the metal gate includes a ferroelectric (FE) layer on the substrate, a work function metal layer on the FE layer, and a low resistance metal layer on the work function metal layer.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Cheng-Ping Kuo, Kuan-Hao Tseng
  • Patent number: 10608112
    Abstract: A semiconductor device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure includes a semiconductor layer, recesses in the semiconductor substrate on both sides of the fin structure and extending partially to underneath the bottom of the fin structure, and an isolation structure filling the recesses.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 31, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 10573753
    Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 25, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Jiehui Shu, Ruilong Xie
  • Patent number: 10515977
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a logic region having a plurality of transistor devices disposed within a substrate, an embedded memory region having a plurality of memory devices disposed within the substrate, and a boundary region separating the logic region from the embedded memory region. The boundary region includes a first isolation structure having a first upper surface and a second upper surface below the first upper surface. The first and second upper surfaces are coupled by an interior sidewall overlying the first isolation structure. The boundary region further includes a memory wall arranged on the second upper surface and surrounding the embedded memory region, and a logic wall arranged on the first upper surface and surrounding the memory wall. The logic wall has an upper surface that is above the plurality of memory devices and the memory wall.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Cheng Wu, Chien-Hung Chang
  • Patent number: 10483116
    Abstract: Processing methods comprising exposing a substrate to an optional nucleation promoter followed by sequential exposure of a first reactive gas comprising a metal oxyhalide compound and a second reactive gas to form a metal film on the substrate.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: November 19, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Xinyu Fu, David Knapp, David Thompson, Jeffrey W. Anthis, Mei Chang
  • Patent number: 10388492
    Abstract: A semiconductor processing member is provided, including a body and a plasma spray coating provided on the body. The coating is an ABO or ABCO complex oxide solid solution composition, where A, B and C are selected from the group consisting of La, Zr, Ce, Gd, Y, Yb and Si, and O is an oxide. The coating imparts both chlorine and fluorine plasma erosion resistance, reduces particle generation during plasma etching, and prevents spalling of the coating during wet cleaning of the semiconductor processing member.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: August 20, 2019
    Assignee: FM Industries, Inc.
    Inventors: Mahmood Naim, David Hammerich
  • Patent number: 10319859
    Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sujin Jung, JinBum Kim, Kang Hun Moon, Kwan Heum Lee, Byeongchan Lee, Choeun Lee, Yang Xu
  • Patent number: 10312366
    Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ren Sun, Shiu-Ko Jangjian, Kun-Ei Chen, Chun-Che Lin
  • Patent number: 10276367
    Abstract: A method for improving wafer surface uniformity is disclosed. A wafer including a first region and a second region is provided. The first region and the second region have different pattern densities. A conductive layer is formed on the wafer. A buffer layer is then formed on the conductive layer. The buffer layer is polished until the conductive layer is exposed. A portion of the conductive layer and the remaining buffer layer are etched away.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: April 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Jen-Chieh Lin, Wen-Chin Lin, Yu-Ting Li
  • Patent number: 10276444
    Abstract: A method for forming a fin-based transistor includes forming a fin on a substrate; overlaying at least an upper portion of the fin with nitrogen-based radicals, wherein the nitrogen-based radicals are distributed along a sidewall and over a top surface of the upper portion of the fin with respective different concentrations; and forming an oxide layer over the upper portion of the fin using a thermal oxidation process.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Hua Lee, Jung-Wei Lee, Wen-Chieh Huang
  • Patent number: 10211313
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; removing the gate structure to form a first recess; forming ferroelectric (FE) layer in the first recess; forming a compressive layer on the FE layer; performing a thermal treatment process; removing the compressive layer; and forming a work function metal layer in the recess.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: February 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Cheng-Ping Kuo, Kuan-Hao Tseng
  • Patent number: 10211311
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a metal gate on a substrate and a spacer around the metal gate, in which the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer. Next, part of the high-k dielectric layer is removed to form an air gap between the work function metal layer and the spacer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: February 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao-Ming Lee, Sheng-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • Patent number: 10192866
    Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: January 29, 2019
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazushi Fujita, Taiji Ema, Mitsuaki Hori, Yasunobu Torii
  • Patent number: 10186460
    Abstract: A semiconductor device including a semiconductor substrate including first regions and second regions, at least one of the first regions being disposed between adjacent second regions; a plurality of first gate structures on the first regions of the semiconductor substrate; and a plurality of second gate structures on the second regions of the semiconductor substrate, wherein each of the first and second gate structures includes a lower gate structure including a recess region defined by sidewalls and a bottom connecting the sidewalls; and an upper gate structure including a gap-fill metal pattern that fills the recess region of the lower gate structure, wherein the bottom of the lower gate structure included in the first gate structure has a thickness different from a thickness of the bottom of the lower gate structure included in the second gate structure, and wherein the gap-fill metal patterns of the first and second gate structures have top surfaces at substantially a same level.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangsu Kim, Yunsang Shin
  • Patent number: 10164040
    Abstract: A method comprises doping a lower portion of a nanowire to form a first drain/source region, wherein the nanowire is formed over a substrate, doping an upper portion of the nanowire to form a second drain/source region, doping a middle portion of the nanowire to form a channel region, wherein the channel region is between the first drain/source region and the second drain/source region, forming a ring-shaped gate structure surrounding a lower portion of the channel region, wherein the ring-shaped gate structure comprises a vertical portion of a first work-function metal layer and depositing a low-resistivity gate metal layer over a horizontal portion of the first work-function metal layer, wherein the low-resistivity gate metal layer is electrically coupled to the vertical portion of the first work-function metal layer through the horizontal portion of the first work-function metal layer.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Ta-Pen Guo, Carlos H. Diaz
  • Patent number: 10163899
    Abstract: The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Amit Kundu, Chia-Hsin Hu, Jaw-Juinn Horng
  • Patent number: 10153326
    Abstract: According to one embodiment, a memory device includes a first conductive layer, a second conductive layer, a first insulating layer and a first layer. The first conductive layer includes a first metal capable of forming a compound with silicon. The second conductive layer includes at least one selected from a group consisting of tungsten, molybdenum, platinum, tungsten nitride, molybdenum nitride, and titanium nitride. The first insulating layer is provided between the first conductive layer and the second conductive layer. The first layer is provided between the first insulating layer and the second conductive layer. The first layer includes silicon.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: December 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masato Koyama, Harumi Seki, Shosuke Fujii, Hidenori Miyagawa
  • Patent number: 10134643
    Abstract: An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: November 20, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Younsung Choi, Steven Lee Prins
  • Patent number: 10121671
    Abstract: Processing methods comprising exposing a substrate to an optional nucleation promoter followed by sequential exposure of a first reactive gas comprising a metal oxyhalide compound and a second reactive gas to form a metal film on the substrate.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: November 6, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Fu, David Knapp, David Thompson, Jeffrey W. Anthis, Mei Chang
  • Patent number: 10109722
    Abstract: The disclosure relates to methods of forming etch-resistant spacers in an integrated circuit (IC) structure. Methods according to the disclosure can include: forming a mask on an upper surface of a gate structure positioned over a substrate; forming a spacer material on the substrate, the mask, and exposed sidewalls of the gate structure; forming a separation layer over the substrate and laterally abutting the spacer material to a predetermined height, such that an exposed portion of the spacer material is positioned above an upper surface of the separation layer and at least partially in contact with the mask; and implanting a dopant into the exposed portion of the spacer material to yield a dopant-implanted region within the spacer material, wherein the dopant-implanted region of the spacer material has a greater etch resistivity than a remainder of the spacer material.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Zhenxing Bi, Pietro Montanini, Eric R. Miller, Balasubramanian Pranatharthiharan, Oleg Gluschenkov, Ruqiang Bao, Kangguo Cheng
  • Patent number: 10083882
    Abstract: A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a <110> orientation wherein the hard mask is oriented in the <112> direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: September 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Sanghoon Lee
  • Patent number: 10068767
    Abstract: A method for fabricating a semiconductor device includes forming a first mask pattern on a first film to extend in a first direction, forming a first spacer on either side wall of the first mask pattern, forming a second film to cover the first spacer and the first film, and forming a second mask pattern on the second film. The second mask pattern extends in a second direction different from the first direction. The method further includes forming a second spacer on either side wall of the second mask pattern, etching the first film using the first spacer and the second spacer as etch masks to form a contact pattern, and removing the first and second spacers to expose the contact pattern.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: September 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Sik Seo, Seung-Heon Lee, Hyun-Woo Lee
  • Patent number: 10043802
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The gate structure includes a gate dielectric layer formed over the substrate and a capping layer formed over the gate dielectric layer. The gate structure further includes a capping oxide layer formed over the capping layer and a work function metal layer formed over the capping oxide layer. The gate structure further includes a gate electrode layer formed over the work function metal layer.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: August 7, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Lin, Chih-Lin Wang, Kang-Min Kuo, Cheng-Wei Lian
  • Patent number: 10026845
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 10008578
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a metal gate on a substrate and a spacer around the metal gate, in which the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer. Next, part of the high-k dielectric layer is removed to form an air gap between the work function metal layer and the spacer.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: June 26, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao-Ming Lee, Sheng-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • Patent number: 10002775
    Abstract: In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: June 19, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yuhei Sato, Keiji Sato, Tetsunori Maruyama, Junichi Koezuka
  • Patent number: 9960175
    Abstract: A method for generating a non-volatile memory device may comprise: applying plasma for a preset time period to an exposed surface of a channel of a field effect transistor such that a plurality of charge-trapping sites are formed at the channel. The channel is comprised of a multi-layer structure of atomically thin two-dimensional sheets.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: May 1, 2018
    Assignee: The Regents of The University of Michigan
    Inventors: Xiaogan Liang, Hongsuk Nam, Sungjin Wi, Mikai Chen
  • Patent number: 9954176
    Abstract: Dielectric treatments for carbon nanotube devices are provided. In one aspect, a method for forming a carbon nanotube-based device is provided. The method includes: providing at least one carbon nanotube disposed on a first dielectric; removing contaminants from surfaces of the first dielectric; and depositing a second dielectric onto the first dielectric and at least partially surrounding the at least one carbon nanotube. A carbon nanotube-based device is also provided.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Damon B. Farmer, Martin M. Frank, Shu-Jen Han
  • Patent number: 9923097
    Abstract: A semiconductor device includes an oxide semiconductor film, a gate electrode overlapping the oxide semiconductor film with a gate insulating film therebetween, a nitride insulating film in contact with the oxide semiconductor film, and a conductive film in contact with the oxide semiconductor film. The oxide semiconductor film includes a first region in contact with the gate insulating film and a second region in contact with the conductive film. The second region contains an impurity element. The impurity element concentration of the second region is different from that of the first region.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: March 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Masami Jintyou, Yukinori Shima
  • Patent number: 9911851
    Abstract: Integrated circuit devices having a cavity and methods of manufacturing the integrated circuit devices are provided. The integrated circuit devices may include a pair of spacers, which define a recess. The integrated circuit device may also include a lower conductive pattern in the recess and an upper conductive pattern on the lower conductive pattern. The upper conductive pattern may have an etch selectivity with respect to the lower conductive pattern and may expose an upper surface of the lower conductive pattern adjacent a sidewall of the upper conductive pattern. An inner sidewall of one of the pair of spacers, the upper surface of the lower conductive pattern and the sidewall of the upper conductive pattern may define a space and a capping pattern may be formed on the upper conductive pattern to seal a top portion of the space, such that a cavity is disposed under the capping pattern.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: March 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kang-Ill Seo, Jin-Wook Lee
  • Patent number: 9899221
    Abstract: The present disclosure discloses a method for preparing electrode including: providing a substrate; forming a buffer layer on the substrate; forming a patterned photoresist on the surface of the buffer layer away from the substrate, the photoresist has a bottom surface and a top surface disposed opposite and a side connected between the bottom surface and the top surface, the bottom surface is bonded to the buffer layer; by dry etching, the portions of the photoresist not covered by the buffer layer is removed to form a receiving area; depositing a conductive film, the conductive film layer includes a waste material forming on the top surface and an electrode filling in the receiving area; and stripping the waste material and the photoresist. The yields of the method for preparing electrode of the present disclosure is high.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: February 20, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventors: Zhichao Zhou, Hui Xia