Insulated Gate Formation Patents (Class 438/585)
  • Patent number: 11462577
    Abstract: An image device includes a first active region and a second active region disposed on a substrate. Each of the first active region and the second active region includes a gate insulating layer disposed on the substrate and a gate electrode disposed on the gate insulating layer. At least one of the first active region and the second active region further includes a first passivation layer containing fluorine (F) disposed between the gate insulating layer and the gate electrode. A concentration of fluorine in the gate insulating layer is higher than a concentration of fluorine in the gate electrode.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: October 4, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu Min Lee, Ju-Eun Kim, Soo Jin Hong
  • Patent number: 11437512
    Abstract: A buried channel MOSFET includes a dielectric layer, a gate and a buried channel region. The dielectric layer having a recess is disposed on a substrate. The gate is disposed in the recess, wherein the gate includes a first work function metal layer having a “-” shaped cross-sectional profile, and a minimum distance between each sidewalls of the first work function metal layer and the nearest sidewall of the recess is larger than zero. The buried channel region is located in the substrate right below the gate. The present invention provides a method of forming said buried channel MOSFET.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: September 6, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Chang-Po Hsiung
  • Patent number: 11430799
    Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
  • Patent number: 11335568
    Abstract: A method for forming a semiconductor structure is provided. The method includes: forming first and second hard mask layers and a target layer on a substrate; patterning the second hard mask layer to form patterned second hard masks including a second wide mask and second narrow masks; and forming spacers on sidewalls of the second wide mask and the second narrow masks. Then, a photoresist layer is formed to cover the second wide mask and the spacers on the sidewalls of the second wide mask. The second narrow masks and the photoresist layer are removed. And, the first hard mask layer is etched with the spacers and the second wide mask together as a mask to form patterned first hard masks on the target layer, wherein the spacers define a first line width, and the second wide mask and the pair of spacers define a second line width.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: May 17, 2022
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Ting-Wei Wu, Cheng-Ta Yang, Hsin-Hung Chou
  • Patent number: 11295786
    Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 5, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu
  • Patent number: 11286558
    Abstract: Methods for depositing a molybdenum nitride film on a surface of a substrate are disclosed. The methods may include: providing a substrate into a reaction chamber; and depositing a molybdenum nitride film directly on the surface of the substrate by performing one or more unit deposition cycles of cyclical deposition process, wherein a unit deposition cycle may include, contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor, and contacting the substrate with a second vapor phase reactant comprising a nitrogen precursor. Semiconductor device structures including a molybdenum nitride film are also disclosed.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: March 29, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Eric Christopher Stevens, Bhushan Zope, Shankar Swaminathan, Charles Dezelah, Qi Xie, Giuseppe Alessio Verni
  • Patent number: 11264506
    Abstract: A semiconductor device includes a power switch circuit and a logic circuit. The semiconductor device includes a first dielectric layer and a thin film transistor (TFT) formed on the first dielectric layer. The TFT includes a semiconductor nano-sheet, a gate dielectric layer wrapping around a channel region of the semiconductor nano-sheet, and a gate electrode layer formed on the gate dielectric layer. The semiconductor nano-sheet is made of an oxide semiconductor material.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Marcus Johannes Henricus Van Dal, Gerben Doornbos
  • Patent number: 11239121
    Abstract: A method of forming a semiconductor device includes providing a structure that includes a substrate, a first fin and a second fin, a first gate structure engaging the first fin, and a second gate structure engaging the second fin; depositing a dielectric layer over the first and second gate structures; etching the dielectric layer, thereby forming a first gate contact opening exposing the first gate structure and a second gate contact opening exposing the second gate structure, wherein the first gate contact opening has a first length that is larger than a second length of the second gate contact opening; and filling the first and second gate contact openings with conductive material, thereby forming a first gate contact engaging the first gate structure and a second gate contact engaging the second gate structure.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan Chen, Jui-Lin Chen, Yu-Kuan Lin
  • Patent number: 11239097
    Abstract: In thickness/depth measurement of a wafer in etching, variation occurs in detected light quantity due to fluctuation of light quantity of a light source or fluctuation of air in a region through which light passes, and measurement accuracy of thickness/depth is reduced, and thus the total light quantity or average light quantity of an arbitrary wavelength is calculated from an optical spectrum measured at each time instant during etching, estimated total light quantity or estimated average light quantity at the present time, which is estimated using total light quantity or average light quantity measured prior to the present time, is calculated, a change rate, as a ratio of the total light quantity at the present time to the estimated total light quantity or a ratio of the average light quantity to the estimated average light quantity, is calculated, the calculated change rate is used to correct light quantity of each wavelength at the present time, and the corrected light quantity of each wavelength is used
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: February 1, 2022
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Soichiro Eto, Hiroyuki Minemura, Tatehito Usui
  • Patent number: 11233023
    Abstract: A semiconductor device of an embodiment includes: a semiconductor substrate; a first insulating layer provided on or above the semiconductor substrate; an aluminum layer provided on the first insulating layer; a second insulating layer provided on the first insulating layer, the second insulating layer covering a first region of a surface of the aluminum layer; and an aluminum oxide film provided on a second region other than the first region of the surface of the aluminum layer, the aluminum oxide film including ?-alumina as a main component, and a film thickness of the aluminum oxide film being equal to or larger than 0.5 nm and equal to or smaller than 3 nm.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: January 25, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hiroaki Takahashi
  • Patent number: 11227937
    Abstract: A method of forming a semiconductor structure includes patterning a hard mask layer over a top surface of a substrate. The method also includes forming a first portion of one or more vertical fins below the patterned hard mask layer. The method further includes forming a top spacer on sidewalls of the hard mask layer and the first portion of the one or more vertical fins. The method further includes forming a second portion of the one or more vertical fins in the substrate below the top spacer and trimming sidewalls of the second portion of the one or more vertical fins. The method further includes forming an interfacial layer on the trimmed sidewalls of the second portion of the one or more vertical fins. The one or more vertical fins provide one or more vertical transport channels for one or more vertical transport field-effect transistors.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: January 18, 2022
    Assignee: International Business Machines Corporation
    Inventors: Shogo Mochizuki, ChoongHyun Lee, Kangguo Cheng, Juntao Li
  • Patent number: 11227993
    Abstract: A device includes a first conductive via plug, a first electrode, a storage element, a second electrode, a spacer, a barrier structure, a first dielectric layer. The first electrode is over the first conductive via plug. The storage element is over the first electrode. The second electrode is over the storage element. The spacer has a bottom portion extending along a top surface of the first electrode and a standing portion extending from the bottom portion and along a sidewall of the second electrode. The barrier structure extends from the bottom portion of the spacer and along a sidewall of the standing portion of the spacer. The first dielectric layer is substantially conformally over the spacer and the barrier structure.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: January 18, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu
  • Patent number: 11183590
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, provided at a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate, a second semiconductor layer of a second conductivity type, selectively provided on the first semiconductor layer, a first semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration higher than that of the semiconductor substrate, a trench penetrating the first semiconductor region and the second semiconductor layer, to reach the first semiconductor layer, and a gate electrode provided in the trench, via a gate insulating film. The trench has a sidewall that includes a terrace portion, surface roughness of the terrace portion being at most 0.1 nm.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: November 23, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tae Tawara, Shinji Fujikake, Aki Takigawa, Hidekazu Tsuchida, Koichi Murata
  • Patent number: 11177215
    Abstract: An integrated circuit device includes a conductive line formed on a substrate, an insulating spacer covering side walls of the conductive line and extending parallel with the conductive line, and a conductive plug that is spaced apart from the conductive line with the insulating spacer therebetween. The insulating spacer includes an insulating liner contacting the conductive line, an outer spacer contacting the conductive plug, and a barrier layer between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungwook Park, Yoongoo Kang, Wonseok Yoo, Dain Lee
  • Patent number: 11171137
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first fin-shaped structure on a substrate; forming a first single diffusion break (SDB) structure in the first fin-shaped structure; forming a first gate structure on the first SDB structure and a second gate structure on the first fin-shaped structure; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned mask on the first gate structure; and performing a replacement metal gate (RMG) process to transform the second gate structure into a metal gate.
    Type: Grant
    Filed: October 6, 2019
    Date of Patent: November 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yen-Wei Tung, Jen-Yu Wang, Cheng-Tung Huang, Yan-Jou Chen
  • Patent number: 11145549
    Abstract: Production of a transistor, the channel structure of which comprises at least one finned channel structure, the method comprising: forming, from a substrate (1), a molding block (3), forming, on the molding block, a thin layer (7) made from a given semiconductor or semi-metallic material, and consisting of one to ten atomic or molecular monolayers of two-dimensional crystal, withdrawing the molding block while retaining a portion (7a) of the thin layer extending against a lateral face of the molding block, said retained portion (7a) forming a fin that is capable of forming a channel structure of the transistor, producing a coating gate electrode against said fin.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: October 12, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Thomas Alava, Thomas Ernst, Zheng Han
  • Patent number: 11088322
    Abstract: A radio frequency (RF) switch includes a phase-change material (PCM), a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM, a capacitive RF terminal, and an ohmic RF terminal. The capacitive RF terminal can include a first trench metal liner situated on a first passive segment of the PCM, and a dielectric liner separating the first trench metal liner from a first trench metal plug. The ohmic RF terminal can include a second trench metal liner situated on a second passive segment of the PCM, and a second trench metal plug ohmically connected to the second trench metal liner. Alternatively, the capacitive RF terminal and the ohmic RF terminal can include lower metal portions and upper metal portions. A MIM capacitor can be formed by the upper metal portion of the capacitive RF terminal, an insulator, and a patterned top plate.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: August 10, 2021
    Assignee: Newport Fab, LLC
    Inventors: Gregory P. Slovin, Nabil El-Hinnawy, Jefferson E. Rose, David J. Howard
  • Patent number: 11081402
    Abstract: Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate, wherein each of the gate stacks includes an electrode layer, a first hard mask (HM) layer over the electrode layer, and a second HM layer over the first HM layer. The method further includes depositing a dielectric layer over the substrate and the gate stacks and filling spaces between the gate stacks; and performing a first chemical mechanical planarization (CMP) process to partially remove the dielectric layer. The method further includes performing an etching process to remove the second HM layer and to partially remove the dielectric layer, thereby exposing the first HM layer. The method further includes performing a second CMP process to at least partially remove the first HM layer.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 3, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Shen, Ying-Ho Chen, Yung-Cheng Lu
  • Patent number: 11056395
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su
  • Patent number: 11004953
    Abstract: A method is provided for fabricating a semiconductor device structure with a short channel and long channel component having different gate dielectric layers without using lithography processes or masks. The method includes forming first and second openings having sidewalls and bottom surfaces in a dielectric layer, the first opening being narrower than the second opening. A first material layer is formed in the first and second openings. A protective layer is formed over the first material layer, wherein the protective layer covers the sidewalls and the bottom surface of the second opening. A block layer is formed to fill the second opening and cover the protective layer therein. The method further includes removing side portions of the protective layer to expose upper portions of the first material layer in the second opening. The block layer is removed from the second opening to expose the protective layer remaining in the second opening.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 11, 2021
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Rinus Tek Po Lee, Hui Zang, Jiehui Shu, Hong Yu, Wei Hong
  • Patent number: 10998423
    Abstract: Methods of selectively nitriding surfaces of semiconductor devices are disclosed. For example, a hardmask is formed on the top portion of the fins to create SOI structure. The hardmask may be formed by nitriding the top portion of the fin. In other embodiments, silicon nitride is grown on the top portion of the fin to form the hard masks. In another example, internal spacers are formed between adjacent nanowires in a gate-all-around structure. The internal spacers may be formed by nitriding the remaining interlayer material between the channel region and source and drain regions.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: Van H. Le, Scott B. Clendenning, Martin M. Mitan, Szuya S. Liao
  • Patent number: 10971594
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Patent number: 10971370
    Abstract: A method of removing a hard mask is provided. Gate stacks are patterned on a substrate, where the gate stacks include a polysilicon layer and the hard mask deposited over the polysilicon layer. A dielectric layer is deposited on the substrate and on the patterned gate stacks. A first portion of the dielectric layer is planarized by chemical mechanical polishing (CMP) to remove a topography of the dielectric layer. The hard mask and a second portion of the dielectric layer are removed by the CMP.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Che-Hao Tu, William Weilun Hong, Ying-Tsung Chen
  • Patent number: 10957696
    Abstract: A method of forming a semiconductor structure includes forming an interfacial layer surrounding at least one channel stack, forming a high-k dielectric layer surrounding the interfacial layer, and forming a metal gate layer surrounding the high-k dielectric layer. The method also includes forming a silicon layer over the metal gate layer and forming at least one additional metal layer over the silicon layer. The method further includes performing silicidation to transform at least a portion of the at least one additional metal layer and at least a portion of the silicon layer into a silicide layer. The metal gate layer, the silicon layer and the silicide layer form at least one gate electrode for a vertical transport field-effect transistor (VTFET).
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Ruqiang Bao, Dechao Guo, Vijay Narayanan
  • Patent number: 10937960
    Abstract: A radio frequency (RF) switch includes a phase-change material (PCM), a heating element underlying an active segment of the PCM and extending outward and transverse to the PCM, a capacitive RF terminal, and an ohmic RF terminal. The capacitive RF terminal can include a first trench metal liner situated on a first passive segment of the PCM, and a dielectric liner separating the first trench metal liner from a first trench metal plug. The ohmic RF terminal can include a second trench metal liner situated on a second passive segment of the PCM, and a second trench metal plug ohmically connected to the second trench metal liner. Alternatively, the capacitive RF terminal and the ohmic RF terminal can include lower metal portions and upper metal portions. A MIM capacitor can be formed by the upper metal portion of the capacitive RF terminal, an insulator, and a patterned top plate.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: March 2, 2021
    Assignee: Newport Fab, LLC
    Inventors: Gregory P. Slovin, Nabil El-Hinnawy, Jefferson E. Rose, David J. Howard
  • Patent number: 10879132
    Abstract: A method of forming tensilely strained n-type fin field effect transistors and compressively strained p-type fin field effect transistors on the same substrate is provided. The method includes forming a pair of adjacent semiconductor mandrels on a semiconductor etch-stop layer, and forming a fill layer on the adjacent semiconductor mandrels and semiconductor etch-stop layer. The method further includes removing a portion of the fill layer to expose one of the adjacent mandrels, and forming a fin on each of the sidewalls of the pair of adjacent semiconductor mandrels. The method further includes forming an occlusion layer on the fins and one of the pair of semiconductor mandrels, and removing another portion of the fill layer to expose the other of the pair of adjacent semiconductor mandrels. The method further includes forming another fin on each of the sidewalls of the other of the pair of adjacent semiconductor mandrels.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: December 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kangguo Cheng
  • Patent number: 10868133
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate electrode structure and an insulating layer over the semiconductor substrate. The insulating layer surrounds the metal gate electrode structure. The method includes nitrifying a first top portion of the metal gate electrode structure to form a metal nitride layer over the metal gate electrode structure.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ruei Yeh, Chih-Lin Wang, Kang-Min Kuo
  • Patent number: 10833011
    Abstract: An semiconductor device capable of suppressing an increase in layout area can be provided. According to one embodiment, the semiconductor device comprises a transistor including a drain formed in a main surface portion of the semiconductor substrate, a source formed in a main surface portion, and a gate for controlling the current between the drain and the source, a drain wiring connected to the drain through the contact, and a passing wire disposed between the source wiring connected to the source through the contact and insulated from the drain, the source, and the gate.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: November 10, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Mitsuhiro Hotta
  • Patent number: 10825918
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure extending above an isolation structure. The semiconductor device structure includes a dummy fin structure formed over the isolation structure, and the dummy fin structure is between the first fin structure and the second fin structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and the top surface of the capping layer is higher than the top surface of the first fin structure and the top surface of the second fin structure. The semiconductor device structure includes a first gate structure formed over first fin structure, and a second gate structure formed over the second fin structure. The first gate structure and the second gate structure are separated by the dummy fin structure and the capping layer.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: November 3, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Kuan-Ting Pan, Chih-Hao Wang, Shi-Ning Ju
  • Patent number: 10796967
    Abstract: A semiconductor device includes a vertical transistor on a substrate. The vertical transistor includes at least one fin. A bottom source/drain is disposed on the substrate and around the at least one fin. A spacer layer is disposed on the bottom source/drain and around the at least one fin. A gate structure is disposed on the spacer layer and around the at least one fin. The gate length is the same or substantially the same on each side of the at least one fin.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10741569
    Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
  • Patent number: 10734287
    Abstract: A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: August 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10714537
    Abstract: Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 14, 2020
    Assignee: Nantero, Inc.
    Inventor: Claude L. Bertin
  • Patent number: 10672778
    Abstract: In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Chin Liu, Wei Cheng Wu, Yi Hsien Lu, Yu-Hsiung Wang, Juo-Li Yang
  • Patent number: 10665464
    Abstract: A process of forming a field effect transistor is disclosed. The process includes steps of depositing a first silicon nitride (SiN) film on a semiconductor layer by a low pressure chemical vapor deposition (LPCVD) technique; depositing a second SiN film on the first SiN film by plasma assisted chemical vapor deposition (p-CVD) technique; preparing a photoresist mask on the second SiN film, the photoresist mask having an opening in a position corresponding to the gate electrode; dry-etching the second SiN film and the first SiN film continuously in a portion of the opening in the photoresist mask to form an opening in the first SiN film and an opening in the second SiN film, the openings in the first and second SiN films exposing the semiconductor layer; and filling at least the opening in the first SiN film by the gate electrode. A feature of the process is that the opening in the first SiN film has an inclined side against the semiconductor layer and gradually widens from the semiconductor layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: May 26, 2020
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Tomohiro Yoshida
  • Patent number: 10658173
    Abstract: A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 19, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Fu-Che Lee, Chieh-Te Chen, Ching-Pin Hsu
  • Patent number: 10636967
    Abstract: A method for manufacturing an electrode including the following steps is provided. A conductive layer is formed on a base material. A radio frequency physical vapor deposition (RF PVD) transition metal compound layer is formed on the conductive layer by using a RF PVD. A sacrificial layer is formed on the RF PVD transition metal compound layer. A planarization process is performed to remove the sacrificial layer and a portion of the RF PVD transition metal compound layer.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: April 28, 2020
    Assignee: Winbond Electronics Corp.
    Inventors: Yi-Chung Chen, Cheng-An Peng, Shuo-Che Chang, Sung-Ying Wen
  • Patent number: 10629695
    Abstract: A semiconductor device includes a metal gate on a substrate, a polysilicon layer on the metal gate, a hard mask on the polysilicon layer, and a source/drain region adjacent to two sides of the metal gate. Preferably, the metal gate includes a ferroelectric (FE) layer on the substrate, a work function metal layer on the FE layer, and a low resistance metal layer on the work function metal layer.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: April 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Cheng-Ping Kuo, Kuan-Hao Tseng
  • Patent number: 10608112
    Abstract: A semiconductor device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure includes a semiconductor layer, recesses in the semiconductor substrate on both sides of the fin structure and extending partially to underneath the bottom of the fin structure, and an isolation structure filling the recesses.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 31, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 10573753
    Abstract: A device including oxide spacer in a contact over active gates (COAG) and method of production thereof. Embodiments include first gate structures over a fin of a substrate and second gate structures, each over an outer portion of the fin and a shallow trench isolation (STI) layer adjacent to the fin; a first raised source/drain (RSD) in a portion of the fin between the first gate structures and a second RSD in the portion of the fin between the first and second gate structures; a metal liner over the first and second RSD and on sidewall portions of the first and second gate structures; a metal layer over the metal liner; and an interlayer dielectric (ILD) over the metal liner and portions of the first and second gate structures.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 25, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Laertis Economikos, Jiehui Shu, Ruilong Xie
  • Patent number: 10515977
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a logic region having a plurality of transistor devices disposed within a substrate, an embedded memory region having a plurality of memory devices disposed within the substrate, and a boundary region separating the logic region from the embedded memory region. The boundary region includes a first isolation structure having a first upper surface and a second upper surface below the first upper surface. The first and second upper surfaces are coupled by an interior sidewall overlying the first isolation structure. The boundary region further includes a memory wall arranged on the second upper surface and surrounding the embedded memory region, and a logic wall arranged on the first upper surface and surrounding the memory wall. The logic wall has an upper surface that is above the plurality of memory devices and the memory wall.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei Cheng Wu, Chien-Hung Chang
  • Patent number: 10483116
    Abstract: Processing methods comprising exposing a substrate to an optional nucleation promoter followed by sequential exposure of a first reactive gas comprising a metal oxyhalide compound and a second reactive gas to form a metal film on the substrate.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: November 19, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Xinyu Fu, David Knapp, David Thompson, Jeffrey W. Anthis, Mei Chang
  • Patent number: 10388492
    Abstract: A semiconductor processing member is provided, including a body and a plasma spray coating provided on the body. The coating is an ABO or ABCO complex oxide solid solution composition, where A, B and C are selected from the group consisting of La, Zr, Ce, Gd, Y, Yb and Si, and O is an oxide. The coating imparts both chlorine and fluorine plasma erosion resistance, reduces particle generation during plasma etching, and prevents spalling of the coating during wet cleaning of the semiconductor processing member.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: August 20, 2019
    Assignee: FM Industries, Inc.
    Inventors: Mahmood Naim, David Hammerich
  • Patent number: 10319859
    Abstract: A semiconductor device is disclosed. The device includes a substrate including an active region defined by a device isolation layer, a fin pattern protruding from the substrate and extending in a first direction, the fin pattern including a gate fin region and a source/drain fin region, a gate pattern disposed on the gate fin region to extend in a second direction crossing the first direction, and a source/drain portion provided on a sidewall of the source/drain fin region. When measured in the second direction, a width of the source/drain fin region is different from a width in the second direction of the gate fin region.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sujin Jung, JinBum Kim, Kang Hun Moon, Kwan Heum Lee, Byeongchan Lee, Choeun Lee, Yang Xu
  • Patent number: 10312366
    Abstract: A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device regions separated by at least one isolation structure disposed in the substrate. Each device region includes two doped regions in the substrate. The gate structures are respectively disposed on the device regions. In each device region, the doped regions are respectively disposed at two opposite sides of the gate structure. The interlayer dielectric layer is disposed over the substrate and peripherally surrounds the gate structures. A top of the interlayer dielectric layer has at least one concave. The material layer fills the concave and has a top surface elevated at the same level with top surfaces of the gate structures. A ratio of a thickness of a thickest portion of the material layer to a pitch of the gate structures ranges from 1/30 to 1/80.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ren Sun, Shiu-Ko Jangjian, Kun-Ei Chen, Chun-Che Lin
  • Patent number: 10276444
    Abstract: A method for forming a fin-based transistor includes forming a fin on a substrate; overlaying at least an upper portion of the fin with nitrogen-based radicals, wherein the nitrogen-based radicals are distributed along a sidewall and over a top surface of the upper portion of the fin with respective different concentrations; and forming an oxide layer over the upper portion of the fin using a thermal oxidation process.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Hua Lee, Jung-Wei Lee, Wen-Chieh Huang
  • Patent number: 10276367
    Abstract: A method for improving wafer surface uniformity is disclosed. A wafer including a first region and a second region is provided. The first region and the second region have different pattern densities. A conductive layer is formed on the wafer. A buffer layer is then formed on the conductive layer. The buffer layer is polished until the conductive layer is exposed. A portion of the conductive layer and the remaining buffer layer are etched away.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: April 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Jen-Chieh Lin, Wen-Chin Lin, Yu-Ting Li
  • Patent number: 10211311
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a metal gate on a substrate and a spacer around the metal gate, in which the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer. Next, part of the high-k dielectric layer is removed to form an air gap between the work function metal layer and the spacer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: February 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao-Ming Lee, Sheng-Hao Lin, Hsin-Yu Chen, Shou-Wei Hsieh
  • Patent number: 10211313
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming an interlayer dielectric (ILD) layer around the gate structure; removing the gate structure to form a first recess; forming ferroelectric (FE) layer in the first recess; forming a compressive layer on the FE layer; performing a thermal treatment process; removing the compressive layer; and forming a work function metal layer in the recess.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: February 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Hung Tsai, Po-Kuang Hsieh, Yu-Ting Tseng, Cheng-Ping Kuo, Kuan-Hao Tseng
  • Patent number: 10192866
    Abstract: A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: January 29, 2019
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kazushi Fujita, Taiji Ema, Mitsuaki Hori, Yasunobu Torii