Abstract: An optical device and method of forming the optical device include a substrate having an integrated metal pattern proximate a detector or top absorber layer to minimize diffraction effects. The integrated metal pattern is aligned with selective regions of the pixel array structure of the detector layer for masking pixels of the pixel array structure. The pattern of the integrated metal pattern may be used for alignment with modulation transfer function (MTF) structures of the detector layer for MTF testing, for alignment with reference pixels of the detector layer for spatial reference used during calibration of the optical device, or for forming a polarizer grid.

Abstract: There is provided a technique that includes: (a) forming an inhibitor layer on a surface of a first material of a concave portion provided on a surface of a substrate, by supplying a precursor to the substrate to adsorb at least a portion of a molecular structure of molecules constituting the precursor on the surface of the first material of the concave portion, the concave portion being composed of the first material containing a first element and a second material containing a second element different from the first element; (b) growing a film on a surface of the second material of the concave portion by supplying a film-forming material to the substrate having the inhibitor layer formed on the surface of the first material; and (c) forming a hydroxyl group termination on the surface of the first material before performing (a).

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Abstract: Semiconductor devices and methods of manufacture are provided whereby fences are formed over a substrate and III-V materials are grown over the substrate, wherein the fences block growth of the III-V materials. As such, smaller areas of the III-V materials are grown, thereby preventing stresses that occur with the growth of larger sheets.

Abstract: Aspects of the disclosure provide methods for fabricating semiconductor devices. In some examples, a method for fabricating a semiconductor device includes forming a stack of layers having a first region and a second region. The stack of layers includes at least a first layer. The method then forms a hard mask layer on the stack of layers in the first region. Then, the method includes patterning the stack of layers in the second region of the semiconductor device. The patterning of the stack of layers in the second region removes a portion of the stack of layers in the second region, and exposes a side of the stack of layers. The method further includes covering at least the side of the stack of layers with a second layer that has a lower remove rate than the first layer, and then the method includes removing the hard mask layer.

Abstract: A method includes forming a metal-containing hard mask layer over a dielectric layer, wherein the metal-containing hard mask layer has a Young's modulus greater than about 400 MPa and a tensile stress greater than about 600 MPa, patterning the metal-containing hard mask layer to form an opening in the metal-containing hard mask layer, and etching the dielectric layer using the metal-containing hard mask layer as an etching mask. The opening extends into the dielectric layer. The opening is filled with a conductive material to form a conductive feature. The metal-containing hard mask layer is then removed.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first dielectric layer and a first conductive feature and a second conductive feature surrounded by the first dielectric layer. The semiconductor device structure also includes a second dielectric layer over the first dielectric layer and a resistive element electrically connected to the first conductive feature. The second dielectric layer surrounds a portion of the resistive element. The semiconductor device structure further includes a conductive via electrically connected to the second conductive feature. The second dielectric layer surrounds a portion of the conductive via, and a contact area between the resistive element and the first conductive feature is wider than a contact area between the conductive via and the second conductive feature.

Abstract: A film forming method includes forming a thin film by executing a plurality of cycles each including supplying a raw material gas to a substrate, supplying a reaction gas capable of reacting with the raw material gas to the substrate, and processing the substrate with deuterium plasma.

Abstract: It is an object to manufacture and provide a highly reliable display device including a thin film transistor with a high aperture ratio which has stable electric characteristics. In a manufacturing method of a semiconductor device having a thin film transistor in which a semiconductor layer including a channel formation region is formed using an oxide semiconductor film, a heat treatment for reducing moisture and the like which are impurities and for improving the purity of the oxide semiconductor film (a heat treatment for dehydration or dehydrogenation) is performed. Further, an aperture ratio is improved by forming a gate electrode layer, a source electrode layer, and a drain electrode layer using conductive films having light transmitting properties.

Abstract: An aluminum-scandium (Al—Sc) etch stop that is both CMOS compatible and highly conductive, and a method for forming the same are disclosed. The low volatility of Sc in Cl and strong covalent bond between Al—Sc leads to an increase in resistance to NaCl corrosion and makes it difficult to dry etch in Cl-based chemistries, resulting in an excellent etch stop material, especially when used in conjunction with an overlying aluminum nitride (AlN) or aluminum scandium nitride (AlScN) piezoelectric layer. When deposited at high deposition temperatures or when subsequently annealed at >600° C., the Al—Sc has a low resistivity, enabling corresponding device operation at temperatures up to at least 500° C. While Al3Sc is the preferred composition, Al1-xScx with x between 5 and 100 atomic percent provides many of these same benefits but comes at the cost of increased electrical resistivity and etch resistance with increasing Sc content due to Sc oxidation.

Abstract: There is provided a technique that includes: performing a set a plurality of times, the set including: (a) loading at least one substrate into a process container; (b) performing a process of forming a nitride film on the at least one substrate by supplying a film-forming gas to the at least one substrate supported by a support in the process container; (c) unloading the processed at least one substrate from an interior of the process container; and (d) supplying an oxidizing gas into the process container from which the processed at least one substrate has been unloaded so as to oxidize one part of the nitride film formed inside the process container in (b) into an oxide film and maintain another part of the nitride film, which is different from the one part of the nitride film, as it is without oxidizing the another part.

Abstract: An IC die includes a temperature control element suitable for three-dimensional IC package with enhanced thermal control and management. The temperature control element may be formed as an integral part of an IC die that may assist temperature control of the IC die when in operation. The temperature control element may include a heat dissipation material disposed therein to assist dissipating thermal energy generated by the plurality of devices in the IC die during operation.

Abstract: [Object] It is an object of the present invention to provide an aluminum alloy film having excellent bending resistance and heat resistance, and a thin film transistor including the aluminum alloy film. [Solving Means] In order to achieve the above-mentioned object, an aluminum alloy film according to an embodiment of the present invention includes: an Al pure metal that includes at least one type of a first additive element selected from the group consisting of Zr, Sc, Mo, Y, Nb, and Ti. A content of the first additive element is 0.01 atomic % or more and 1.0 atomic % or less. Such an aluminum alloy film has excellent bending resistance and excellent heat resistance. Further, also etching can be performed on the aluminum alloy film.

Abstract: The disclosure relates to structures of, and methods for forming electromagnetic band gap (EBG) element. Specifically, the disclosure is directed to methods for additively manufacturing electronic mushroom-type EBG elements having a periodic cell structure enabling a reduced footprint and increased band gap range for a very wide range of frequencies, for example between 500 MHz to about 30 GHz, by altering both the EBG structure's superstrate as well as the ground plane.

Abstract: A method for manufacturing an electronic device includes providing a substrate with a first major surface having a microchannel, wherein the microchannel has a first end and a second end; dispensing a conductive liquid in the microchannel to cause the conductive liquid to move, primarily by capillary pressure, in a first direction toward the first end of the microchannel and in a second direction toward the second end of the microchannel; and solidifying the conductive liquid to form an electrically conductive trace electrically connecting a first electronic device at the first end of the microchannel to a second electronic device at the second end of the microchannel.

Abstract: Methods of forming thin-film structures including metal carbide material, and structures and devices including the metal carbide material are disclosed. Exemplary structures include metal carbide material formed using two or more different processes (e.g., two or more different precursors), which enables tuning of various metal carbide material properties, including resistivity, current leakage, and work function.

Abstract: An object is to coat a target position on a substrate with a dense film. In order to achieve the object, while a substrate on which a base containing a coating material is formed is transported, an auxiliary agent is applied to the substrate, and then a main agent containing a coating material is applied to the substrate to react the main agent with the auxiliary agent, so that a portion on the substrate where the base is formed is coated with the coating material.

Abstract: A method for fabricating a semiconductor device includes providing a substrate; sequentially forming a layer of first conductive material, a layer of second conductive material, a layer of third conductive material, and an anti-reflective coating layer over the substrate; performing a plug etch process to turn the layer of first conductive material into a bottom conductive layer on the substrate, turn the layer of second conductive material into a middle conductive layer on the bottom conductive layer, and turn the layer of third conductive material into a top conductive layer on the middle conductive layer; selectively forming an insulating covering layer on a sidewall of the middle conductive layer, wherein the bottom conductive layer, the middle conductive layer, the top conductive layer, and the insulating covering layer together configure a plug structure; and forming a first dielectric layer on the substrate and surrounding the plug structure.

Abstract: In the semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure also includes a first conductive feature and a second conductive feature surrounded by the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element having a first portion over the second dielectric layer and a second portion penetrating through the second dielectric layer to be electrically connected to the first conductive feature. In addition, the semiconductor device structure includes a conductive via penetrating through the second dielectric layer to be electrically connected to the second conductive feature. The second portion of the resistive element is wider than the conductive via.

Abstract: A substrate processing apparatus includes: a heat processing unit configured to perform a heat process on a substrate having a film formed on the substrate; and a control unit configured to control the heat processing unit, wherein the heat processing unit comprises: a heater configured to support and heat the substrate; a chamber configured to cover the substrate supported on the heater; a gas ejector having a head in which ejection holes are formed, and configured to eject a gas from the ejection holes toward a surface of the substrate; an outer peripheral exhauster configured to evacuate a processing space inside the chamber from an outer peripheral region located further outward than a peripheral edge of the substrate supported on the heater; and a central exhauster configured to evacuate the processing space from a central region located further inward than the peripheral edge of the substrate supported on the heater.

Abstract: Embodiments of the invention relate to a method for fabricating a semiconductor structure comprising a semiconductor material, and a semiconductor substrate fabricated from the method. The method can include a step of providing a template structure. The template structure can comprise an opening, a cavity and a seed structure. The seed structure can comprise a seed material and a seed surface. An inner surface of the template structure can comprise at least one metallic surface area comprising a metallic material. The embodied method further comprises a step of growing the semiconductor structure within the cavity of the template structure from the seed surface along the metallic surface area.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

Abstract: Disclosed is a composition for removing polymers. The composition contains a fluorinated alkyl compound, a polar aprotic solvent, and an acyclic secondary or tertiary amine compound.

Abstract: Disclosed is a semiconductor package comprising first and second semiconductor structures spaced apart on a first substrate, a heat sink covering the first and second semiconductor structure and the first substrate, and a thermal interface material layer between the heat sink and the first and second semiconductor structures. The first semiconductor structure includes a first sidewall adjacent to the second semiconductor structure and a second sidewall opposite the first sidewall. The thermal interface material layer includes a first segment between the first and second semiconductor structures and a second segment protruding beyond the second sidewall. A first distance from a top surface of the first substrate to a lowest point of a bottom surface of the first segment is less than a second distance from the top surface of the first substrate to a lowest point of a bottom surface of the second segment.

Abstract: A package includes a first semiconductor substrate; an integrated circuit die bonded to the first semiconductor substrate with a dielectric-to-dielectric bond; a molding compound over the first semiconductor substrate and around the integrated circuit die; and a redistribution structure over the first semiconductor substrate and the integrated circuit die, wherein the redistribution structure is electrically connected to the integrated circuit die. The integrated circuit die includes a second semiconductor substrate, and wherein the second semiconductor substrate comprises a first sidewall, a second sidewall, and a third sidewall opposite the first sidewall and the second sidewall, and the second sidewall is offset from the first sidewall.

Abstract: Manufacturing a handle substrate includes: providing a support substrate having a receiving face; depositing an anti-adherent formulation including a first solvent over the receiving face of the support substrate so as to form a film; depositing a liquid formulation over a face of the film, before the complete evaporation of the first solvent, the liquid formulation being intended to form an adhesive layer; and evaporating the first solvent so as to obtain an anti-adherent film from the film in order to obtain the handle substrate and to obtain a bonding energy between the anti-adherent film and the adhesive layer lower than about 1.2 J/m2. The step of depositing of a liquid formulation is carried out when the face of the film has a water drop angle smaller than 65 degrees, so as to avoid any risk of dewetting of the liquid formulation.

Abstract: A transparent display device includes a first pixel electrode, a second pixel electrode, a first transparent region and at least two metal lines. The second pixel electrode is disposed adjacent to the first pixel electrode. The first transparent region is disposed adjacent to the first pixel electrode. The at least two metal lines are disposed between the first pixel electrode and the second pixel electrode.

Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.

Abstract: A bulk-acoustic wave resonator may include: a substrate; a resonator unit including a first electrode disposed on the substrate, a piezoelectric layer disposed on the first electrode, and a second electrode disposed on the piezoelectric layer; and a protective layer disposed on a surface of the resonator unit. The protective layer is formed of a diamond film, and a grain size of the diamond film is 50 nm or more.

Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.

Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.

Abstract: A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.

Abstract: A method of fabricating an integrated circuit (IC) includes depositing a photoresist on a semiconductor substrate and patterning the photoresist to expose one or more deposition target areas. The method further includes performing a dual-deposition process that deposits a plurality of layers on the photoresists and on the target areas. A conductive layer among the plurality of conductive layers inhibits X-ray energy so as to prevent damage to the underlying semiconductor substrate.

Abstract: A formable transparent conductive film are described that comprise a sparse metal conductive layer, a thermoplastic polymer substrate supporting the sparse metal conductive layer, a viscoelastic polymer with a thickness from about 15 microns to about 150 microns over the sparse metal conductive layer. A layered film structure can be formed that is suitable for contouring on the surface of a three dimensional object without unacceptable increases in sheet resistance and with good optical transparency and low haze. The formable films can be placed into a frozen configuration bent 90 degrees with a radius of curvature of no more than about 5 centimeters while exhibiting a surface resistance of no more than about 500 ohms/sq. with a total transmittance with respect to visible light of at least about 80%.

Abstract: There is provided a mask forming method, including: forming a photosensitive organic film on a workpiece; generating a first region and a second region in the photosensitive organic film by performing a selective exposure and a post-exposure baking on the photosensitive organic film, the first region having an acidic functional group in the photosensitive organic film, and the second region having a protective group in which the acidic functional group is protected; forming a salt in the first region by causing a basic substance to permeate into the first region using a substance staying in a gaseous state or a solid state; and removing the first region by dissolving the salt in a developer.

Abstract: Polyarylene resins and compositions containing them are useful as underlayers in semiconductor manufacturing processes.

Abstract: Integrated circuit (IC) dies and method for manufacturing the same are described herein that mitigate pattern loading effects during manufacture. In one example, the IC includes a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone. The first and second circuit blocks have first and second transistors that are at least partially fabricated from a gate metal layer and disposed immediately adjacent the buffer zone. A dummy structure is formed in the buffer zone and is also at least partially fabricated from the gate metal layer. An amount of gate metal layer material in the dummy structure is selected to mitigate differences in the amount of gate metal layer material in regions of first and second circuit blocks that neighbor each other across the buffer zone.

Abstract: In various aspects, the present disclosure is directed to methods and compositions for the simultaneous production of carbon nanotubes and hydrogen gas from lower hydrocarbon comprises methane, ethane, propane, butane, or a combination thereof utilizing the disclosed catalysts. In various aspects, the disclosure relates to methods for COx-free production of hydrogen with concomitant production of carbon nanotubes. Also disclosed are methods and compostions for selective base grown carbon nanotubes over a disclosed catalyst composition. In a further aspect, the disclosure relates to mono, bimetallic, and trimetallic catalysts comprising a 3d transition metal (e.g., Ni, Fe, Co, Mn, Cr, Mo, and combinations thereof) over a support material selected from a silica, an alumina, a zeolite, titatnium dioxide, and combinations thereof. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present disclosure.

Abstract: A semiconductor device having high reliability is obtained. A semiconductor device includes a semiconductor substrate, a first gate interconnection, a second gate interconnection, a first metal portion, an insulating member, and a second metal portion. The first gate interconnection and the second gate interconnection are disposed on a main surface of the semiconductor substrate with an interval therebetween. The first metal portion is formed on the first gate interconnection and the second gate interconnection. The first metal portion has a top surface located opposite to the semiconductor substrate at a region between the first gate interconnection and the second gate interconnection. A recess is formed in the top surface. The insulating member fills at least a portion of the recess. The second metal portion extends from an upper surface of the insulating member onto the top surface of the first metal portion.

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

Abstract: A flattening method, by utilizing the advantages of the CARE method and making up for the disadvantages, can perform removal processing of a surface of a workpiece at a sufficient processing rate and can provide a processed surface having enhanced flatness without leaving damage in the processed surface. A flattening method comprises at least two surface removal steps and at least two cleaning steps, the final surface removal step being a catalyst-referred etching step comprising immersing a workpiece in a processing solution containing at least one of hydrohalic acid, hydrogen peroxide water and ozone water, and bringing a surface of a catalyst platen into contact with or close proximity to a surface to be processed of the workpiece to process the surface, said catalyst platen having in a surface a catalyst selected from the group consisting of platinum, gold, a ceramic solid catalyst, a transition metal, glass, and an acidic or basic solid catalyst.

Abstract: The present invention provides a nanometer wire grid structure fabrication method.

Abstract: Techniques regarding a vertical nanofluidic channel array are provided. For example, one or more embodiments described herein can regard an apparatus that can comprise a semiconductor substrate and a dielectric layer adjacent to the semiconductor substrate. The dielectric layer can comprise a first nanofluidic channel and a second nanofluidic channel. The second nanofluidic channel can be located between the first nanofluidic channel and the semiconductor substrate.

Abstract: A photoelectric conversion element includes a composite passivation film disposed on a second surface of a semiconductor substrate that is opposite to a first surface on which light is incident. The composite passivation film includes a first passivation film having negative fixed charges and a protection film that protects the first passivation film. This allows the carrier collection efficiency of the photoelectric conversion element to be improved.

Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.

Abstract: There is provided a technique that includes: (a) supplying a hydrogen gas to a substrate set to a first temperature, without supplying any oxygen-containing gas; (b) changing a temperature of the substrate from the first temperature to a second temperature, which is higher than the first temperature, while the hydrogen gas is supplied to the substrate, without supplying any oxygen-containing gas; and (c) forming an oxide film on the substrate, on which (a) and (b) have been performed, by alternately repeating, while the temperature of the substrate is maintained at the second temperature: supplying a precursor gas to the substrate; and supplying an oxygen-containing gas to the substrate, without supplying any hydrogen-containing gas.

Abstract: To provide a manufacturing method capable of manufacturing a high density semiconductor device excellent in transmission between chips at a favorable yield and at low cost. A method for manufacturing a semiconductor device includes an insulating layer forming step of forming an insulating layer 3 having a trench 4 above a substrate 1, a copper layer forming step of forming a copper layer 5a on the insulating layer 3 so as to fill the trench 4, and a removing step of removing the copper layer 5a on the insulating layer 3 by a fly cutting method so as to retain a copper layer part in the trench 4.

Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.