Coating With Electrically Or Thermally Conductive Material Patents (Class 438/584)
  • Patent number: 11905598
    Abstract: An object is to coat a target position on a substrate with a dense film. In order to achieve the object, while a substrate on which a base containing a coating material is formed is transported, an auxiliary agent is applied to the substrate, and then a main agent containing a coating material is applied to the substrate to react the main agent with the auxiliary agent, so that a portion on the substrate where the base is formed is coated with the coating material.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: February 20, 2024
    Assignee: FUJIFILM Corporation
    Inventors: Eijiro Iwase, Keio Okano, Katsuyuki Nukui
  • Patent number: 11823984
    Abstract: A method for fabricating a semiconductor device includes providing a substrate; sequentially forming a layer of first conductive material, a layer of second conductive material, a layer of third conductive material, and an anti-reflective coating layer over the substrate; performing a plug etch process to turn the layer of first conductive material into a bottom conductive layer on the substrate, turn the layer of second conductive material into a middle conductive layer on the bottom conductive layer, and turn the layer of third conductive material into a top conductive layer on the middle conductive layer; selectively forming an insulating covering layer on a sidewall of the middle conductive layer, wherein the bottom conductive layer, the middle conductive layer, the top conductive layer, and the insulating covering layer together configure a plug structure; and forming a first dielectric layer on the substrate and surrounding the plug structure.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: November 21, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Tse-Yao Huang
  • Patent number: 11817427
    Abstract: In the semiconductor device, a semiconductor substrate has first and second surfaces. A circuitry layer is formed over the first surface and a first insulating layer is further formed over the circuitry layer. A second insulating layer including a first insulating element is formed over the second surface. A third insulating layer including a second insulating element different from the first insulating element of the second insulating layer is formed over the second surface with an intervention of the second insulating layer therebetween. A penetration electrode penetrates through the semiconductor substrate, the circuitry layer, the first insulating layer, the second insulating layer and the third insulating layer.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: November 14, 2023
    Assignee: Longitude Licensing Limited
    Inventors: Ryohei Kitada, Masahiro Yamaguchi
  • Patent number: 11798821
    Abstract: A substrate processing apparatus includes: a heat processing unit configured to perform a heat process on a substrate having a film formed on the substrate; and a control unit configured to control the heat processing unit, wherein the heat processing unit comprises: a heater configured to support and heat the substrate; a chamber configured to cover the substrate supported on the heater; a gas ejector having a head in which ejection holes are formed, and configured to eject a gas from the ejection holes toward a surface of the substrate; an outer peripheral exhauster configured to evacuate a processing space inside the chamber from an outer peripheral region located further outward than a peripheral edge of the substrate supported on the heater; and a central exhauster configured to evacuate the processing space from a central region located further inward than the peripheral edge of the substrate supported on the heater.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: October 24, 2023
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yukinobu Otsuka, Shinsuke Takaki, Yasuhiro Kuga, Koji Ushimaru, Ryohei Fujise
  • Patent number: 11798848
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first dielectric layer over the substrate. The semiconductor device structure also includes a first conductive feature and a second conductive feature surrounded by the first dielectric layer and a second dielectric layer over the first dielectric layer. The semiconductor device structure further includes a resistive element having a first portion over the second dielectric layer and a second portion penetrating through the second dielectric layer to be electrically connected to the first conductive feature. In addition, the semiconductor device structure includes a conductive via penetrating through the second dielectric layer to be electrically connected to the second conductive feature. The second portion of the resistive element is wider than the conductive via.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: October 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Sheh Huang, Hsiu-Wen Hsueh, Yu-Hsiang Chen, Chii-Ping Chen
  • Patent number: 11776809
    Abstract: Embodiments of the invention relate to a method for fabricating a semiconductor structure comprising a semiconductor material, and a semiconductor substrate fabricated from the method. The method can include a step of providing a template structure. The template structure can comprise an opening, a cavity and a seed structure. The seed structure can comprise a seed material and a seed surface. An inner surface of the template structure can comprise at least one metallic surface area comprising a metallic material. The embodied method further comprises a step of growing the semiconductor structure within the cavity of the template structure from the seed surface along the metallic surface area.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: October 3, 2023
    Assignee: International Business Machines Corporation
    Inventors: Markus Fabian Ritter, Fabrizio Nichele, Heinz Schmid, Heike Erika Riel
  • Patent number: 11757016
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: September 12, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Patent number: 11739048
    Abstract: Disclosed is a composition for removing polymers. The composition contains a fluorinated alkyl compound, a polar aprotic solvent, and an acyclic secondary or tertiary amine compound.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: August 29, 2023
    Assignee: DONGWOO FINE-CHEM CO., LTD.
    Inventors: Soon-Hong Pang, Kyeong-Muk Choi, Han-Byeol Kang
  • Patent number: 11735494
    Abstract: Disclosed is a semiconductor package comprising first and second semiconductor structures spaced apart on a first substrate, a heat sink covering the first and second semiconductor structure and the first substrate, and a thermal interface material layer between the heat sink and the first and second semiconductor structures. The first semiconductor structure includes a first sidewall adjacent to the second semiconductor structure and a second sidewall opposite the first sidewall. The thermal interface material layer includes a first segment between the first and second semiconductor structures and a second segment protruding beyond the second sidewall. A first distance from a top surface of the first substrate to a lowest point of a bottom surface of the first segment is less than a second distance from the top surface of the first substrate to a lowest point of a bottom surface of the second segment.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: August 22, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hee-Jeong Kim, Juhyun Lyu, Un-Byoung Kang, Jongho Lee
  • Patent number: 11728312
    Abstract: A package includes a first semiconductor substrate; an integrated circuit die bonded to the first semiconductor substrate with a dielectric-to-dielectric bond; a molding compound over the first semiconductor substrate and around the integrated circuit die; and a redistribution structure over the first semiconductor substrate and the integrated circuit die, wherein the redistribution structure is electrically connected to the integrated circuit die. The integrated circuit die includes a second semiconductor substrate, and wherein the second semiconductor substrate comprises a first sidewall, a second sidewall, and a third sidewall opposite the first sidewall and the second sidewall, and the second sidewall is offset from the first sidewall.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen
  • Patent number: 11710653
    Abstract: Manufacturing a handle substrate includes: providing a support substrate having a receiving face; depositing an anti-adherent formulation including a first solvent over the receiving face of the support substrate so as to form a film; depositing a liquid formulation over a face of the film, before the complete evaporation of the first solvent, the liquid formulation being intended to form an adhesive layer; and evaporating the first solvent so as to obtain an anti-adherent film from the film in order to obtain the handle substrate and to obtain a bonding energy between the anti-adherent film and the adhesive layer lower than about 1.2 J/m2. The step of depositing of a liquid formulation is carried out when the face of the film has a water drop angle smaller than 65 degrees, so as to avoid any risk of dewetting of the liquid formulation.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: July 25, 2023
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Pierre Montmeat, Frank Fournel, Paul Stewart
  • Patent number: 11681325
    Abstract: A transparent display device includes a first pixel electrode, a second pixel electrode, a first transparent region and at least two metal lines. The second pixel electrode is disposed adjacent to the first pixel electrode. The first transparent region is disposed adjacent to the first pixel electrode. The at least two metal lines are disposed between the first pixel electrode and the second pixel electrode.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: June 20, 2023
    Assignee: Innolux Corporation
    Inventors: Toshiya Inada, Masahiro Yoshiga, Yoshitada Ozaki, Satoru Takahashi
  • Patent number: 11631745
    Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.
    Type: Grant
    Filed: April 2, 2021
    Date of Patent: April 18, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Sheng Lai, Yu-Fan Peng, Li-Ting Chen, Yu-Shan Lu, Yu-Bey Wu, Wei-Chung Sun, Yuan-Ching Peng, Kuei-Yu Kao, Shih-Yao Lin, Chih-Han Lin, Pei-Yi Liu, Jing Yi Yan
  • Patent number: 11558026
    Abstract: A bulk-acoustic wave resonator may include: a substrate; a resonator unit including a first electrode disposed on the substrate, a piezoelectric layer disposed on the first electrode, and a second electrode disposed on the piezoelectric layer; and a protective layer disposed on a surface of the resonator unit. The protective layer is formed of a diamond film, and a grain size of the diamond film is 50 nm or more.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 17, 2023
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Kyung Lee, Sang Heon Han, Ran Hee Shin, Jin Suk Son
  • Patent number: 11495464
    Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ya-Lan Chang, Ting-Gang Chen, Tai-Chun Huang, Chi On Chui, Yung-Cheng Lu
  • Patent number: 11495684
    Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Han Chu, Nai-Chia Chen, Ping-Jung Huang, Tsung-Min Chuo, Jui-Ming Shih, Bi-Ming Yen
  • Patent number: 11450558
    Abstract: A method for fabricating metal interconnect structure includes the steps of: forming a first metal interconnection in a first inter-metal dielectric (IMD) layer on a substrate; forming a cap layer on the first metal interconnection; forming a second IMD layer on the cap layer; performing a first etching process to remove part of the second IMD layer for forming an opening; performing a plasma treatment process; and performing a second etching process to remove polymers from bottom of the opening.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: September 20, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Patent number: 11380645
    Abstract: A structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The first bonding structure includes a first dielectric layer and first conductors embedded in the first dielectric layer. The second semiconductor die includes a second bonding structure. The second bonding structure includes a second dielectric layer and second conductors embedded in the second dielectric layer. The first dielectric layer is in contact with the second dielectric layer, and the first conductors are in contact with the second conductors. Thermal conductivity of the first dielectric layer and the second dielectric layer is greater than thermal conductivity of silicon dioxide.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: July 5, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chun-Hui Yu, Jeng-Nan Hung, Kuo-Chung Yee, Po-Fan Lin
  • Patent number: 11348804
    Abstract: A method of fabricating an integrated circuit (IC) includes depositing a photoresist on a semiconductor substrate and patterning the photoresist to expose one or more deposition target areas. The method further includes performing a dual-deposition process that deposits a plurality of layers on the photoresists and on the target areas. A conductive layer among the plurality of conductive layers inhibits X-ray energy so as to prevent damage to the underlying semiconductor substrate.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: May 31, 2022
    Assignee: RAYTHEON COMPANY
    Inventor: Jonathan Getty
  • Patent number: 11343911
    Abstract: A formable transparent conductive film are described that comprise a sparse metal conductive layer, a thermoplastic polymer substrate supporting the sparse metal conductive layer, a viscoelastic polymer with a thickness from about 15 microns to about 150 microns over the sparse metal conductive layer. A layered film structure can be formed that is suitable for contouring on the surface of a three dimensional object without unacceptable increases in sheet resistance and with good optical transparency and low haze. The formable films can be placed into a frozen configuration bent 90 degrees with a radius of curvature of no more than about 5 centimeters while exhibiting a surface resistance of no more than about 500 ohms/sq. with a total transmittance with respect to visible light of at least about 80%.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: May 24, 2022
    Assignee: C3 Nano, Inc.
    Inventors: Yu Kambe, Yung-Yu Huang, Christopher S. Scully, Xiqiang Yang, Ajay Virkar
  • Patent number: 11205571
    Abstract: There is provided a mask forming method, including: forming a photosensitive organic film on a workpiece; generating a first region and a second region in the photosensitive organic film by performing a selective exposure and a post-exposure baking on the photosensitive organic film, the first region having an acidic functional group in the photosensitive organic film, and the second region having a protective group in which the acidic functional group is protected; forming a salt in the first region by causing a basic substance to permeate into the first region using a substance staying in a gaseous state or a solid state; and removing the first region by dissolving the salt in a developer.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: December 21, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hidetami Yaegashi, Soichiro Okada
  • Patent number: 11175581
    Abstract: Polyarylene resins and compositions containing them are useful as underlayers in semiconductor manufacturing processes.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: November 16, 2021
    Assignee: ROHM AND HAAS ELECTRONIC MATERIALS LLC
    Inventors: Sheng Liu, Shintaro Yamada, James F. Cameron, Li Cui, Suzanne M. Coley, Joshua A. Kaitz, Keren Zhang
  • Patent number: 11114344
    Abstract: Integrated circuit (IC) dies and method for manufacturing the same are described herein that mitigate pattern loading effects during manufacture. In one example, the IC includes a die body having a first circuit block separated from an adjacent second circuit block by a buffer zone. The first and second circuit blocks have first and second transistors that are at least partially fabricated from a gate metal layer and disposed immediately adjacent the buffer zone. A dummy structure is formed in the buffer zone and is also at least partially fabricated from the gate metal layer. An amount of gate metal layer material in the dummy structure is selected to mitigate differences in the amount of gate metal layer material in regions of first and second circuit blocks that neighbor each other across the buffer zone.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: September 7, 2021
    Assignee: XILINX, INC.
    Inventors: Hui-Wen Lin, Nui Chong, Myongseob Kim, Henley Liu, Ping-Chin Yeh, Cheang-whang Chang
  • Patent number: 11040876
    Abstract: In various aspects, the present disclosure is directed to methods and compositions for the simultaneous production of carbon nanotubes and hydrogen gas from lower hydrocarbon comprises methane, ethane, propane, butane, or a combination thereof utilizing the disclosed catalysts. In various aspects, the disclosure relates to methods for COx-free production of hydrogen with concomitant production of carbon nanotubes. Also disclosed are methods and compostions for selective base grown carbon nanotubes over a disclosed catalyst composition. In a further aspect, the disclosure relates to mono, bimetallic, and trimetallic catalysts comprising a 3d transition metal (e.g., Ni, Fe, Co, Mn, Cr, Mo, and combinations thereof) over a support material selected from a silica, an alumina, a zeolite, titatnium dioxide, and combinations thereof. This abstract is intended as a scanning tool for purposes of searching in the particular art and is not intended to be limiting of the present disclosure.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 22, 2021
    Assignee: WEST VIRGINIA UNIVERSITY
    Inventors: Jianli Hu, Deepa Ayillath Kutteri, I-Wen Wang
  • Patent number: 10998436
    Abstract: A semiconductor device having high reliability is obtained. A semiconductor device includes a semiconductor substrate, a first gate interconnection, a second gate interconnection, a first metal portion, an insulating member, and a second metal portion. The first gate interconnection and the second gate interconnection are disposed on a main surface of the semiconductor substrate with an interval therebetween. The first metal portion is formed on the first gate interconnection and the second gate interconnection. The first metal portion has a top surface located opposite to the semiconductor substrate at a region between the first gate interconnection and the second gate interconnection. A recess is formed in the top surface. The insulating member fills at least a portion of the recess. The second metal portion extends from an upper surface of the insulating member onto the top surface of the first metal portion.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: May 4, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Jun Fujita, Naoto Kaguchi, Fumio Wada
  • Patent number: 10985028
    Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: April 20, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wan Hsuan Hsu, Jao Sheng Huang, Yen-Chiu Kuo, Yu-Li Cheng, Ya Tzu Chen, Neng-Jye Yang, Chun-Li Chou
  • Patent number: 10916455
    Abstract: A flattening method, by utilizing the advantages of the CARE method and making up for the disadvantages, can perform removal processing of a surface of a workpiece at a sufficient processing rate and can provide a processed surface having enhanced flatness without leaving damage in the processed surface. A flattening method comprises at least two surface removal steps and at least two cleaning steps, the final surface removal step being a catalyst-referred etching step comprising immersing a workpiece in a processing solution containing at least one of hydrohalic acid, hydrogen peroxide water and ozone water, and bringing a surface of a catalyst platen into contact with or close proximity to a surface to be processed of the workpiece to process the surface, said catalyst platen having in a surface a catalyst selected from the group consisting of platinum, gold, a ceramic solid catalyst, a transition metal, glass, and an acidic or basic solid catalyst.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: February 9, 2021
    Assignee: EBARA CORPORATION
    Inventors: Kazuto Yamauchi, Yasuhisa Sano, Hideyuki Hara, Junji Murata, Keita Yagi
  • Patent number: 10710350
    Abstract: The present invention provides a nanometer wire grid structure fabrication method.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: July 14, 2020
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Minghui Li
  • Patent number: 10689245
    Abstract: Techniques regarding a vertical nanofluidic channel array are provided. For example, one or more embodiments described herein can regard an apparatus that can comprise a semiconductor substrate and a dielectric layer adjacent to the semiconductor substrate. The dielectric layer can comprise a first nanofluidic channel and a second nanofluidic channel. The second nanofluidic channel can be located between the first nanofluidic channel and the semiconductor substrate.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Choonghyun Lee, Peng Xu
  • Patent number: 10665731
    Abstract: A photoelectric conversion element includes a composite passivation film disposed on a second surface of a semiconductor substrate that is opposite to a first surface on which light is incident. The composite passivation film includes a first passivation film having negative fixed charges and a protection film that protects the first passivation film. This allows the carrier collection efficiency of the photoelectric conversion element to be improved.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: May 26, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yasushi Yoshikawa, Takayuki Isaka, Chikao Okamoto
  • Patent number: 10636908
    Abstract: An embodiment method includes forming a patterned etch mask over a target layer and patterning the target layer using the patterned etch mask as a mask to form a patterned target layer. The method further includes performing a first cleaning process on the patterned etch mask and the patterned target layer, the first cleaning process including a first solution. The method additionally includes performing a second cleaning process to remove the patterned etch mask and form an exposed patterned target layer, the second cleaning process including a second solution. The method also includes performing a third cleaning process on the exposed patterned target layer, and performing a fourth cleaning process on the exposed patterned target layer, the fourth cleaning process comprising the first solution.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Han Chu, Nai-Chia Chen, Ping-Jung Huang, Tsung-Min Chuo, Jui-Ming Shih, Bi-Ming Yen
  • Patent number: 10604842
    Abstract: There is provided a technique that includes: (a) supplying a hydrogen gas to a substrate set to a first temperature, without supplying any oxygen-containing gas; (b) changing a temperature of the substrate from the first temperature to a second temperature, which is higher than the first temperature, while the hydrogen gas is supplied to the substrate, without supplying any oxygen-containing gas; and (c) forming an oxide film on the substrate, on which (a) and (b) have been performed, by alternately repeating, while the temperature of the substrate is maintained at the second temperature: supplying a precursor gas to the substrate; and supplying an oxygen-containing gas to the substrate, without supplying any hydrogen-containing gas.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: March 31, 2020
    Assignee: Kokusai Electric Corporation
    Inventors: Katsuyoshi Harada, Yushin Takasawa, Satoshi Shimamoto, Shin Sone
  • Patent number: 10388608
    Abstract: To provide a manufacturing method capable of manufacturing a high density semiconductor device excellent in transmission between chips at a favorable yield and at low cost. A method for manufacturing a semiconductor device includes an insulating layer forming step of forming an insulating layer 3 having a trench 4 above a substrate 1, a copper layer forming step of forming a copper layer 5a on the insulating layer 3 so as to fill the trench 4, and a removing step of removing the copper layer 5a on the insulating layer 3 by a fly cutting method so as to retain a copper layer part in the trench 4.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: August 20, 2019
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Kazuyuki Mitsukura, Masaya Toba, Kenichi Iwashita, Kohsuke Urashima, Kazuhiko Kurafuchi
  • Patent number: 10373822
    Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: August 6, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prashant Kumar Kulshreshtha, Sudha Rathi, Praket P. Jha, Saptarshi Basu, Kwangduk Douglas Lee, Martin J. Seamons, Bok Hoen Kim, Ganesh Balasubramanian, Ziqing Duan, Lei Jing, Mandar B. Pandit
  • Patent number: 10254614
    Abstract: A process of making an electrochromic or an electrolytic film by Ultrasonic Spray Pyrolysis (USP) deposition on a substrate comprising: mixing a surfactant to an aqueous precursor solution comprising an electrochromic component or an electrolytic component to provide a spray solution; introducing the spray solution into an ultrasonic spray deposition nozzle at a constant flow rate between 0.1 mL/min and 2 mL/min and applying an ultrasonic frequency between 80 and 120 kHz to generate atomized droplets of the precursor solution; entraining the atomized droplets with a controlled jet of air as gas carrier at a pressure between 0.50 to 2.0 psi, onto a pre-heated substrate at a temperature of 200 to 450° C.; thermally converting the atomized droplets when depositing onto the pre-heated substrate to generate an electrochromic or an electrolytic film.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: April 9, 2019
    Assignees: UNIVERSITE DE LIEGE, INISMA
    Inventors: Rudi Cloots, Catherine Henrist, Jessica Denayer, Anthony Maho, Francis Cambier, Véronique Lardot, Geoffroy Bister, Philippe Aubry
  • Patent number: 10236328
    Abstract: A method of manufacturing an organic light-emitting display device includes forming pixel electrodes on a substrate, forming a first protective layer with a first exposure portion that exposes a first pixel electrode of the pixel electrodes, forming on the first pixel electrode a first intermediate layer and a first blocking layer covering the first intermediate layer, removing the first protective layer, forming a second protective with a second exposure portion that exposes a second pixel electrode of the pixel electrodes, forming on the first pixel electrode a second intermediate layer and a second blocking layer covering the second intermediate layer, removing the second protective layer, forming a third protective with a third exposure portion that exposes a third pixel electrode of the pixel electrodes, and forming a third intermediate layer on the third pixel electrode, wherein each of the first and second blocking layers includes a self-assembled monolayer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 19, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaesik Kim, Yeonhwa Lee, Joongu Lee, Sehoon Jeong
  • Patent number: 10174423
    Abstract: Disclosed are Niobium-containing film forming compositions, methods of synthesizing the same, and methods of forming Niobium-containing films on one or more substrates via atomic layer deposition processes using the Niobium-containing film forming compositions.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 8, 2019
    Assignee: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventors: Clément Lansalot-Matras, Jooho Lee, Wontae Noh
  • Patent number: 10134896
    Abstract: A semiconductor substructure with an improved source/drain structure is described. The semiconductor substructure can include an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structure is disposed over or on a recess surface of a recess that extends below said upper surface. The source/drain structure includes a first epitaxial layer, having a first composition, over or on the interface surface, and a subsequent epitaxial layer, having a subsequent composition, over or on the first epitaxial layer. A dopant concentration of the subsequent composition is greater than a dopant concentration of the first composition, and a carbon concentration of the first composition ranges from 0 to 1.4 at.-%. Methods of making semiconductor substructures including improved source/drain structures are also described.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, Ying-Min Chou, Yi-Fang Pai
  • Patent number: 10128467
    Abstract: The invention relates to a method for depositing a target material onto an organic electrically functional material. The method includes the steps of: providing a substrate with an organic electrically functional material, like an emissive electroluminescent layer; creating a vapor plume of target material by pulsed laser deposition; depositing a first layer of target material on the organic electrically functional material, while maintaining the maximum particle velocity of the deposited particles below a preset value; and depositing a second layer of target material on the first layer of target material, while the maximum particle velocity of the deposited particles is above the preset value. The invention also relates to an intermediate product and to an organic light emitting diode.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: November 13, 2018
    Assignee: Solmates B.V.
    Inventors: Jan Matthijn Dekkers, Jan Arnaud Janssens
  • Patent number: 10128197
    Abstract: Embodiments disclosed herein generally relate to methods and apparatus for processing of the bottom surface of a substrate to counteract thermal stresses thereon. Correcting strains are applied to the bottom surface of the substrate which compensate for undesirable strains and distortions on the top surface of the substrate. Specifically designed films may be formed on the back side of the substrate by any combination of deposition, implant, thermal treatment, and etching to create strains that compensate for unwanted distortions of the substrate. Localized strains may be introduced by locally altering the hydrogen content of a silicon nitride film or a carbon film. Structures may be formed by printing, lithography, or self-assembly techniques. Treatment of the layers of film is determined by the stress map desired and includes annealing, implanting, melting, or other thermal treatments.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: November 13, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Joseph M. Ranish, Aaron Muir Hunter, Swaminathan T. Srinivasan
  • Patent number: 9985013
    Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Lee, Jung Wei Cheng, Hao-Cheng Hou, Tsung-Ding Wang, Jiun Yi Wu, Ming-Chung Sung
  • Patent number: 9935295
    Abstract: According to at least one embodiment, an organic light-emitting component includes a substrate, a first electrode arranged on the substrate, and a second electrode. An organic light-generating layer stack is arranged between the first and second electrodes and includes a first organic OLED functional material. A first organic coupling-out layer is in optical contact with the organic light-generating layer stack and includes an organic material containing a second organic OLED functional material. One of the first and second electrodes is translucent, and the first organic coupling-out layer is arranged on that side of the electrode that faces away from the organic light-generating layer stack.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: April 3, 2018
    Assignee: OSRAM OLED GMBH
    Inventors: Thilo Reusch, Daniel Steffen Setz
  • Patent number: 9837265
    Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 5, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prashant Kumar Kulshreshtha, Sudha Rathi, Praket P. Jha, Saptarshi Basu, Kwangduk Douglas Lee, Martin J. Seamons, Bok Hoen Kim, Ganesh Balasubramanian, Ziqing Duan, Lei Jing, Mandar B. Pandit
  • Patent number: 9773996
    Abstract: The present invention relates to a transparent conducting film and an organic light emitting device comprising the same. The transparent conducting film according to the present invention has a low surface resistance value, a high front surface transmittance and a low light absorptance. The light emission efficiency of the organic light emitting device according to the present invention may be enhanced by comprising a transparent conducting film having low light absorptance. In particular, the organic light emitting device according to the present invention may additionally comprise an internal light extraction layer to improve the light extraction efficiency, and the loss of light generated by the difference between refractive indices of a transparent electrode and a substrate may be minimized.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: September 26, 2017
    Assignee: LG CHEM, LTD.
    Inventors: Yeon Keun Lee, Jungdoo Kim, Jihee Kim
  • Patent number: 9774167
    Abstract: A method of production of a semiconducting structure including a strained portion tied to a support layer by molecular bonding, including the steps in which a cavity is produced situated under a structured part so as to strain a central portion by lateral portions, and the structured part is placed in contact and molecularly bonded with a support layer, wherein a consolidation annealing is performed, and a distal part of the lateral portions in relation to the strained portion is etched.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 26, 2017
    Assignee: Commissariat A l'Energie Atomique et aux Energies Alternatives
    Inventors: Alban Gassenq, Vincent Reboud, Kevin Guilloy, Vincent Calvo, Alexei Tchelnokov
  • Patent number: 9755178
    Abstract: Various embodiments may relate to a method for forming a conductor path structure on an electrode surface of an electronic component. The method includes introducing electrically conductive metal particles into an insulating carrier material, producing a mixed composition by mixing the carrier material with the metal particles, applying the mixed composition to the electrode surface, separating the metal particles from the carrier material, allowing the metal particles to become attached to the electrode surface, fixing the metal particles attached to the electrode surface, and curing the carrier material.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: September 5, 2017
    Assignee: OSRAM OLED GMBH
    Inventors: Silke Scharner, Stefan Dechand
  • Patent number: 9735317
    Abstract: The invention pertains to formation of a semiconducting portion (60) by epitaxial growth on a strained germination portion (40), comprising the steps in which a cavity (21) is produced under a structured part (11) by rendering free a support layer (30) situated facing the structured part (11), a central portion (40), termed the strained germination portion, then being strained; and a semiconducting portion (60) is formed by epitaxial growth on the strained germination portion (40), wherein the structured part (11) is furthermore placed in contact with the support layer (30) in such a way as to bind the structured part (11) of the support layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 15, 2017
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Vincent Reboud, Alban Gassenq, Kevin Guilloy, Vincent Calvo, Alexei Tchelnokov
  • Patent number: 9725810
    Abstract: A liquid displacement is performed by supplying a plating liquid onto a substrate 2 while rotating the substrate 2 at a first rotational speed in a state that a pre-treatment liquid remains on a surface of the substrate 2 (liquid displacement process (block S305)). Then, an initial film is formed on the substrate 2 by stopping the rotation of the substrate 2 or by rotating the substrate 2 at a second rotational speed while continuously supplying the plating liquid onto the substrate 2 (incubation process (block S306)). Thereafter, a plating film is grown by rotating the substrate 2 at a third rotational speed while continuously supplying the plating liquid onto the substrate 2 (plating film growing process (block S307)). Here, the first rotational speed is higher than the third rotational speed, and the third rotational speed is higher than the second rotational speed.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: August 8, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Nobutaka Mizutani, Takashi Tanaka, Mitsuaki Iwashita
  • Patent number: 9666813
    Abstract: A flexible display device includes a flexible substrate doped with a dopant so as to control a work function of the flexible substrate; a display unit formed on the flexible substrate, and including a plurality of pixel circuit layers and a plurality of emission layers; and an encapsulation layer formed to cover the display unit.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 30, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Keun-Soo Lee
  • Patent number: 9659814
    Abstract: Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: May 23, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Annamalai Lakshmanan, Ben-Li Sheu, Guodan Wei, Nicole Lundy, Paul F. Ma