Coating With Electrically Or Thermally Conductive Material Patents (Class 438/584)
  • Patent number: 10373822
    Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: August 6, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prashant Kumar Kulshreshtha, Sudha Rathi, Praket P. Jha, Saptarshi Basu, Kwangduk Douglas Lee, Martin J. Seamons, Bok Hoen Kim, Ganesh Balasubramanian, Ziqing Duan, Lei Jing, Mandar B. Pandit
  • Patent number: 10254614
    Abstract: A process of making an electrochromic or an electrolytic film by Ultrasonic Spray Pyrolysis (USP) deposition on a substrate comprising: mixing a surfactant to an aqueous precursor solution comprising an electrochromic component or an electrolytic component to provide a spray solution; introducing the spray solution into an ultrasonic spray deposition nozzle at a constant flow rate between 0.1 mL/min and 2 mL/min and applying an ultrasonic frequency between 80 and 120 kHz to generate atomized droplets of the precursor solution; entraining the atomized droplets with a controlled jet of air as gas carrier at a pressure between 0.50 to 2.0 psi, onto a pre-heated substrate at a temperature of 200 to 450° C.; thermally converting the atomized droplets when depositing onto the pre-heated substrate to generate an electrochromic or an electrolytic film.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: April 9, 2019
    Assignees: UNIVERSITE DE LIEGE, INISMA
    Inventors: Rudi Cloots, Catherine Henrist, Jessica Denayer, Anthony Maho, Francis Cambier, Véronique Lardot, Geoffroy Bister, Philippe Aubry
  • Patent number: 10236328
    Abstract: A method of manufacturing an organic light-emitting display device includes forming pixel electrodes on a substrate, forming a first protective layer with a first exposure portion that exposes a first pixel electrode of the pixel electrodes, forming on the first pixel electrode a first intermediate layer and a first blocking layer covering the first intermediate layer, removing the first protective layer, forming a second protective with a second exposure portion that exposes a second pixel electrode of the pixel electrodes, forming on the first pixel electrode a second intermediate layer and a second blocking layer covering the second intermediate layer, removing the second protective layer, forming a third protective with a third exposure portion that exposes a third pixel electrode of the pixel electrodes, and forming a third intermediate layer on the third pixel electrode, wherein each of the first and second blocking layers includes a self-assembled monolayer.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: March 19, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaesik Kim, Yeonhwa Lee, Joongu Lee, Sehoon Jeong
  • Patent number: 10174423
    Abstract: Disclosed are Niobium-containing film forming compositions, methods of synthesizing the same, and methods of forming Niobium-containing films on one or more substrates via atomic layer deposition processes using the Niobium-containing film forming compositions.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 8, 2019
    Assignee: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude
    Inventors: Clément Lansalot-Matras, Jooho Lee, Wontae Noh
  • Patent number: 10134896
    Abstract: A semiconductor substructure with an improved source/drain structure is described. The semiconductor substructure can include an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structure is disposed over or on a recess surface of a recess that extends below said upper surface. The source/drain structure includes a first epitaxial layer, having a first composition, over or on the interface surface, and a subsequent epitaxial layer, having a subsequent composition, over or on the first epitaxial layer. A dopant concentration of the subsequent composition is greater than a dopant concentration of the first composition, and a carbon concentration of the first composition ranges from 0 to 1.4 at.-%. Methods of making semiconductor substructures including improved source/drain structures are also described.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, Ying-Min Chou, Yi-Fang Pai
  • Patent number: 10128197
    Abstract: Embodiments disclosed herein generally relate to methods and apparatus for processing of the bottom surface of a substrate to counteract thermal stresses thereon. Correcting strains are applied to the bottom surface of the substrate which compensate for undesirable strains and distortions on the top surface of the substrate. Specifically designed films may be formed on the back side of the substrate by any combination of deposition, implant, thermal treatment, and etching to create strains that compensate for unwanted distortions of the substrate. Localized strains may be introduced by locally altering the hydrogen content of a silicon nitride film or a carbon film. Structures may be formed by printing, lithography, or self-assembly techniques. Treatment of the layers of film is determined by the stress map desired and includes annealing, implanting, melting, or other thermal treatments.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: November 13, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Joseph M. Ranish, Aaron Muir Hunter, Swaminathan T. Srinivasan
  • Patent number: 10128467
    Abstract: The invention relates to a method for depositing a target material onto an organic electrically functional material. The method includes the steps of: providing a substrate with an organic electrically functional material, like an emissive electroluminescent layer; creating a vapor plume of target material by pulsed laser deposition; depositing a first layer of target material on the organic electrically functional material, while maintaining the maximum particle velocity of the deposited particles below a preset value; and depositing a second layer of target material on the first layer of target material, while the maximum particle velocity of the deposited particles is above the preset value. The invention also relates to an intermediate product and to an organic light emitting diode.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: November 13, 2018
    Assignee: Solmates B.V.
    Inventors: Jan Matthijn Dekkers, Jan Arnaud Janssens
  • Patent number: 9985013
    Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsun Lee, Jung Wei Cheng, Hao-Cheng Hou, Tsung-Ding Wang, Jiun Yi Wu, Ming-Chung Sung
  • Patent number: 9935295
    Abstract: According to at least one embodiment, an organic light-emitting component includes a substrate, a first electrode arranged on the substrate, and a second electrode. An organic light-generating layer stack is arranged between the first and second electrodes and includes a first organic OLED functional material. A first organic coupling-out layer is in optical contact with the organic light-generating layer stack and includes an organic material containing a second organic OLED functional material. One of the first and second electrodes is translucent, and the first organic coupling-out layer is arranged on that side of the electrode that faces away from the organic light-generating layer stack.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: April 3, 2018
    Assignee: OSRAM OLED GMBH
    Inventors: Thilo Reusch, Daniel Steffen Setz
  • Patent number: 9837265
    Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 5, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prashant Kumar Kulshreshtha, Sudha Rathi, Praket P. Jha, Saptarshi Basu, Kwangduk Douglas Lee, Martin J. Seamons, Bok Hoen Kim, Ganesh Balasubramanian, Ziqing Duan, Lei Jing, Mandar B. Pandit
  • Patent number: 9774167
    Abstract: A method of production of a semiconducting structure including a strained portion tied to a support layer by molecular bonding, including the steps in which a cavity is produced situated under a structured part so as to strain a central portion by lateral portions, and the structured part is placed in contact and molecularly bonded with a support layer, wherein a consolidation annealing is performed, and a distal part of the lateral portions in relation to the strained portion is etched.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 26, 2017
    Assignee: Commissariat A l'Energie Atomique et aux Energies Alternatives
    Inventors: Alban Gassenq, Vincent Reboud, Kevin Guilloy, Vincent Calvo, Alexei Tchelnokov
  • Patent number: 9773996
    Abstract: The present invention relates to a transparent conducting film and an organic light emitting device comprising the same. The transparent conducting film according to the present invention has a low surface resistance value, a high front surface transmittance and a low light absorptance. The light emission efficiency of the organic light emitting device according to the present invention may be enhanced by comprising a transparent conducting film having low light absorptance. In particular, the organic light emitting device according to the present invention may additionally comprise an internal light extraction layer to improve the light extraction efficiency, and the loss of light generated by the difference between refractive indices of a transparent electrode and a substrate may be minimized.
    Type: Grant
    Filed: November 14, 2012
    Date of Patent: September 26, 2017
    Assignee: LG CHEM, LTD.
    Inventors: Yeon Keun Lee, Jungdoo Kim, Jihee Kim
  • Patent number: 9755178
    Abstract: Various embodiments may relate to a method for forming a conductor path structure on an electrode surface of an electronic component. The method includes introducing electrically conductive metal particles into an insulating carrier material, producing a mixed composition by mixing the carrier material with the metal particles, applying the mixed composition to the electrode surface, separating the metal particles from the carrier material, allowing the metal particles to become attached to the electrode surface, fixing the metal particles attached to the electrode surface, and curing the carrier material.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: September 5, 2017
    Assignee: OSRAM OLED GMBH
    Inventors: Silke Scharner, Stefan Dechand
  • Patent number: 9735317
    Abstract: The invention pertains to formation of a semiconducting portion (60) by epitaxial growth on a strained germination portion (40), comprising the steps in which a cavity (21) is produced under a structured part (11) by rendering free a support layer (30) situated facing the structured part (11), a central portion (40), termed the strained germination portion, then being strained; and a semiconducting portion (60) is formed by epitaxial growth on the strained germination portion (40), wherein the structured part (11) is furthermore placed in contact with the support layer (30) in such a way as to bind the structured part (11) of the support layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 15, 2017
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Vincent Reboud, Alban Gassenq, Kevin Guilloy, Vincent Calvo, Alexei Tchelnokov
  • Patent number: 9725810
    Abstract: A liquid displacement is performed by supplying a plating liquid onto a substrate 2 while rotating the substrate 2 at a first rotational speed in a state that a pre-treatment liquid remains on a surface of the substrate 2 (liquid displacement process (block S305)). Then, an initial film is formed on the substrate 2 by stopping the rotation of the substrate 2 or by rotating the substrate 2 at a second rotational speed while continuously supplying the plating liquid onto the substrate 2 (incubation process (block S306)). Thereafter, a plating film is grown by rotating the substrate 2 at a third rotational speed while continuously supplying the plating liquid onto the substrate 2 (plating film growing process (block S307)). Here, the first rotational speed is higher than the third rotational speed, and the third rotational speed is higher than the second rotational speed.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: August 8, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Nobutaka Mizutani, Takashi Tanaka, Mitsuaki Iwashita
  • Patent number: 9666813
    Abstract: A flexible display device includes a flexible substrate doped with a dopant so as to control a work function of the flexible substrate; a display unit formed on the flexible substrate, and including a plurality of pixel circuit layers and a plurality of emission layers; and an encapsulation layer formed to cover the display unit.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 30, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventor: Keun-Soo Lee
  • Patent number: 9659814
    Abstract: Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: May 23, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Annamalai Lakshmanan, Ben-Li Sheu, Guodan Wei, Nicole Lundy, Paul F. Ma
  • Patent number: 9634066
    Abstract: The disclosure relates to a method of making organic light emitting diode array. A base defining a plurality of convexities is provided. A number of first electrodes are applied on the plurality of convexities. At least one hole injection layer is applied on the first electrodes. A number of hole transport layers are transfer printed on the at least one hole injection layer. Three of the hole transport layers, that correspond to the same pixel unit, have different thickness. A number of electroluminescent layers are applied on the hole transport layers. A patterned second insulative layer is made among the convexities to expose the electroluminescent layers. A second electrode is electrically connected to the electroluminescent layers.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: April 25, 2017
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Liang-Neng Chien, Jung-An Cheng, Dong An, Zhen-Dong Zhu, Chang-Ting Lin, I-Wei Wu, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 9593422
    Abstract: Disclosed is a method of manufacturing a semiconductor device including: performing a pre-process to a substrate, on a surface of which a metal film or a GST film is formed, such that a first film is formed on the metal film or the GST film by executing at least one cycle of alternately performing (i) supplying a first processing gas, and (ii) supplying a second processing gas that is not activated by plasma excitation; and performing a formation process to the substrate to which the pre-process has been performed such that a second film is formed on the first film by executing at least one cycle of alternately (i) supplying the first processing gas, and (ii) supplying the second processing gas that is activated by plasma excitation.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: March 14, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Masayuki Asai, Koichi Honda, Mamoru Umemoto, Kazuyuki Okuda
  • Patent number: 9520370
    Abstract: A method of forming a semiconductor device assembly comprises forming on a first substrate, at least one bond pad comprising a first nickel material over the first substrate, a first copper material on the first nickel material, and a solder-wetting material on the first copper material. On a second substrate is formed at least one conductive pillar comprising a second nickel material, a second copper material directly contacting the second nickel material, and a solder material directly contacting the second copper material. The solder-wetting material is contacted with the solder material. The first copper material, the solder-wetting material, the second copper material, and the solder material are converted into a substantially homogeneous intermetallic compound interconnect structure. Additional methods, semiconductor device assemblies, and interconnect structures are also described.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: December 13, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Jaspreet S. Gandhi
  • Patent number: 9390910
    Abstract: Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: July 12, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Prashant Kumar Kulshreshtha, Sudha Rathi, Praket P. Jha, Saptarshi Basu, Kwangduk Douglas Lee, Martin J. Seamons, Bok Hoen Kim, Ganesh Balasubramanian, Ziqing Duan, Lei Jing, Mandar B. Pandit
  • Patent number: 9368348
    Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a plurality of spacers over a first hard mask layer to form a first mask pattern, and forming a first photoresist over the plurality of spacers. The method further includes patterning the first photoresist to form a second mask pattern, and patterning the first hard mask layer using the first mask pattern and the second mask pattern in a same patterning step.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: June 14, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Min Huang, Chung-Ju Lee
  • Patent number: 9362167
    Abstract: A method of supplying cobalt to a recess formed in an insulation film of an object to be processed is disclosed. In one embodiment, the method includes forming a cobalt nitride film on a surface of the insulation film comprising a surface defining the recess, forming a cobalt film on the cobalt nitride film, and heating the cobalt film.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: June 7, 2016
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Atsushi Shimada, Shinji Furukawa, Tatsuo Hatano
  • Patent number: 9343549
    Abstract: A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: May 17, 2016
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Min-Chul Sun, Byung-Gook Park
  • Patent number: 9330933
    Abstract: A method for planarizing a polymer layer is provided which includes providing a substrate having the polymer layer formed thereon, providing a structure having a substantially flat surface, pressing the flat surface of the structure to a top surface of the polymer layer such that the top surface of the polymer layer substantially conforms to the flat surface of the structure, and separating the flat surface of the structure from the top surface of the polymer material layer.
    Type: Grant
    Filed: June 11, 2008
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Burn Jeng Lin
  • Patent number: 9322777
    Abstract: Systems, devices, and methods are described for identifying, classifying, differentiating, etc., objects. For example a hyperspectral imaging system can include a dark-field module operably coupled to at least one of an optical assembly, a dark-field illuminator, and a hyperspectral imaging module. The dark-field module can include circuitry having one or more sensors operable to acquire one or more dark-field micrographs associated with scattered electromagnetic energy from an object interrogated by the dark-field interrogation stimulus. The hyperspectral imaging module can be operably coupled to the dark-field module, and can include circuitry configured to generate an angular-resolved and spectrally resolved scattering matrix based on the one or more dark-field micrographs of the object.
    Type: Grant
    Filed: October 29, 2012
    Date of Patent: April 26, 2016
    Assignee: Tokitae LLC
    Inventors: Michael C. Hegg, Benjamin K. Wilson
  • Patent number: 9324793
    Abstract: An ashing chemistry employing a combination of Cl2 and N2 is provided, which removes residual material from sidewalls of a patterned metallic hard mask layer without residue such that the sidewalls of the patterned metallic hard mask layer are vertical. The vertical profiled of the sidewalls of the patterned metallic hard mask layer can be advantageously employed to reduce pattern factor dependency in the etch bias between the pattern transferred into an underlying layer and the pattern as formed on the metallic hard mask layer. Further, the ashing chemistry can be employed to enhance removal of stringers in vertical portions of a metallic material layer.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: April 26, 2016
    Assignees: International Business Machines Corporation, STMICROELECTRONICS, INC.
    Inventors: Lawrence A. Clevenger, Carl J. Radens, Richard S. Wise, Edem Wornyo, Yiheng Xu, John Zhang
  • Patent number: 9242271
    Abstract: Room temperature electrochemical methods to deposit thin films of chalcogenide glasses.
    Type: Grant
    Filed: September 19, 2012
    Date of Patent: January 26, 2016
    Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Keith J. Stevenson, Sankaran Murugesan, Patrick Keams, Arunkumar Akkineni
  • Patent number: 9209182
    Abstract: The described embodiments of mechanisms for placing dummy gate structures next to and/or near a number of wide gate structures reduce dishing effect for gate structures during chemical-mechanical polishing of gate layers. The arrangements of dummy gate structures and the ranges of metal pattern density have been described. Wide gate structures, such as analog devices, can greatly benefit from the reduction of dishing effect.
    Type: Grant
    Filed: July 8, 2013
    Date of Patent: December 8, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Jacklyn Chang, Julie Tran
  • Patent number: 9162337
    Abstract: A polishing apparatus includes: a pure water supply line configured to supply deaerated pure water into the polishing apparatus; a gas dissolving unit coupled to the pure water supply line and configured to dissolve a gas in the deaerated pure water to produce gas-dissolved pure water; a gas-dissolved pure water delivery line coupled to the gas dissolving unit and configured to deliver the gas-dissolved pure water; an ultrasonic cleaning unit coupled to the gas-dissolved pure water delivery line and configured to impart an ultrasonic vibration energy to the gas-dissolved pure water, which has been delivered through the gas-dissolved pure water delivery line, and then eject the gas-dissolved pure water onto an object to be cleaned; and a controller configured to control the gas dissolving unit and the ultrasonic cleaning unit.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: October 20, 2015
    Assignee: Ebara Corporation
    Inventor: Tomoatsu Ishibashi
  • Patent number: 9135476
    Abstract: A method for producing a radio frequency identification transponder includes providing a conductive sheet covered by a mask layer, processing the mask layer by a laser beam so as to form an exposed portion of the conductive sheet, wherein the processing is carried out after a radio frequency identification chip has been attached to the conductive sheet, and etching the exposed portion so as to form a groove in the conductive sheet, wherein the groove defines an edge of an antenna element of the transponder.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: September 15, 2015
    Assignee: Smartrac IP B.V.
    Inventor: Juhani Virtanen
  • Patent number: 9093411
    Abstract: A pad structure in a semiconductor wafer for wafer testing is described. The pad structure includes at least two metal pads connected there-between by a plurality of conductive visa in one or more insulation layers. A plurality of contact bars in contact with the bottom-most metal pad extends substantially vertically from the bottom-most metal pad into the substrate. An isolation structure substantially surrounds the plurality of contact bars to isolate the pad structure.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: July 28, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ying-Ju Chen, Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii
  • Patent number: 9066035
    Abstract: An object is to achieve low-power consumption by reducing the off-state current of a transistor in a photosensor. A semiconductor device including a photosensor having a photodiode, a first transistor, and a second transistor; and a read control circuit including a read control transistor, in which the photodiode has a function of supplying charge based on incident light to a gate of the first transistor; the first transistor has a function of storing charge supplied to its gate and converting the charge stored into an output signal; the second transistor has a function of controlling reading of the output signal; the read control transistor functions as a resistor converting the output signal into a voltage signal; and semiconductor layers of the first transistor, the second transistor, and the read control transistor are formed using an oxide semiconductor.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: June 23, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma
  • Patent number: 9040413
    Abstract: A nonvolatile memory device contains a resistive switching memory element with improved device switching performance and lifetime by custom tailoring the average concentration of defects in the resistive switching film and methods of forming the same. The nonvolatile memory element includes a first electrode layer, a second electrode layer, and a resistive switching layer disposed between the first electrode layer and the second electrode layer. The resistive switching layer comprises a first sub-layer and a second sub-layer, wherein the first sub-layer has more defects than the first sub-layer. A method includes forming a first sub-layer on the first electrode layer by a first ALD process and forming a second sub-layer on the first sub-layer by a second ALD process, where the first sub-layer has a different amount of defects than the second sub-layer.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: May 26, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Randall J. Higuchi, Chien-Lan Hsueh, Yun Wang
  • Patent number: 9040403
    Abstract: Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bounded by the first and second sidewall spacers. The method removes an upper portion of the first sidewall spacer and deposits a layer of metal in the trench and over a remaining portion of the first sidewall spacer to form a gate electrode and an interconnect.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: May 26, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Thilo Scheiper, Stefan Flachowsky, Andy Wei
  • Patent number: 9029253
    Abstract: Nitrogen-containing phase-stabilized films, methods of forming phase-stabilized films, and structures and devices including the phase-stabilized films are disclosed. The phase-stabilized films include a matrix material and a phase stabilizer, which provides a morphologically stabilizing effect to a matrix material within the films. The phase-stabilized films may be used as, for example, gate electrodes and similar films in microelectronic devices.
    Type: Grant
    Filed: May 1, 2013
    Date of Patent: May 12, 2015
    Assignee: ASM IP Holding B.V.
    Inventors: Robert Brennan Milligan, Fred Alokozai
  • Patent number: 9024326
    Abstract: In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: May 5, 2015
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Robert Actis, Pane-chane Chao, Robert J. Lender, Jr., Kanin Chu, Bernard J. Schmanski, Sue May Jessup
  • Patent number: 9023688
    Abstract: A method for processing a semiconductor device, the method including; providing a first semiconductor layer including first transistors; forming interconnection layers overlying the transistors, where the interconnection layers include copper or aluminum; forming a shielding heat conducting layer overlaying the interconnection layers; forming an isolation layer overlaying the shielding heat conducting layer; forming a second semiconductor layer overlying the isolation layer, and processing the second semiconductor layer at a temperature greater than about 400° C., where the interconnection layers are kept at a temperature below about 400° C.
    Type: Grant
    Filed: June 7, 2014
    Date of Patent: May 5, 2015
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Albert Karl Henning
  • Patent number: 9012887
    Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: April 21, 2015
    Assignee: Qunano AB
    Inventors: Lars Samuelson, Jonas Ohlsson, Thomas Mårtensson, Patrik Svensson
  • Patent number: 8999842
    Abstract: A method of manufacturing a semiconductor device with a cap layer for a copper interconnect structure formed in a dielectric layer is provided. In an embodiment, a conductive material is embedded within a dielectric layer, the conductive material comprising a first material and having either a recess, a convex surface, or is planar. The conductive material is silicided to form an alloy layer. The alloy layer comprises the first material and a second material of germanium, arsenic, tungsten, or gallium.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui-Lin Chang, Hung Chun Tsai, Yung-Cheng Lu, Syun-Ming Jang
  • Publication number: 20150084128
    Abstract: Disclosed are semiconductor-on-insulator (SOI) structures comprising an SOI device (e.g., an SOI metal oxide semiconductor field effect transistor (MOSFET)) with local heat dissipater(s). Each heat dissipater comprises an opening, which is adjacent an active region of the SOI device, which extends through the insulator layer on which the SOI device sits to the semiconductor substrate below, and which is at least partially filled with a fill material. This fill material is a thermal conductor so as to dissipate heat generated by the SOI device and is also an electrical isolator so as to minimize current leakage. In the case of MOSFET, the local heat dissipater(s) can be aligned below the source/drain extension(s) or the source/drain(s). Alternatively, the local heat dissipater(s) can be aligned below the channel or parallel and adjacent to opposing sides of the channel. Also disclosed herein are methods of forming these SOI structures.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Jeffrey P. Gambino, Qizhi Liu, Zhenzhen Ye, Yan Zhang
  • Publication number: 20150087141
    Abstract: A method for making a metal grating is provided. The method includes providing a substrate, applying a metal layer on a surface of the substrate, forming a number of protrusions spaced from each other on a surface of the metal layer, wherein each of the number of protrusions is made of two resist layer, one of the two resist layers being made of silicone oligomer, etching the surface of the metal layer exposed out of the number of protrusions using a physical etching gas and a reactive etching gas, and dissolving the number of protrusions on the surface of the metal layer.
    Type: Application
    Filed: April 28, 2014
    Publication date: March 26, 2015
    Applicants: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: ZHEN-DONG ZHU, QUN-QING LI, LI-HUI ZHANG, MO CHEN, SHOU-SHAN FAN
  • Patent number: 8987119
    Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 24, 2015
    Assignee: Sandisk 3D LLC
    Inventors: Vance Dunton, S. Brad Herner, Paul Wai Kie Poon, Chuanbin Pan, Michael Chan, Michael Konevecki, Usha Raghuram
  • Patent number: 8975189
    Abstract: A method of forming a fine pattern comprises depositing a modifying layer on a substrate. A photoresist layer is deposited on the modifying layer, the photoresist layer having a first pattern. The modifying layer is etched according to the first pattern of the photoresist layer. A treatment is performed to the etched modifying layer to form a second pattern, the second pattern having a smaller line width roughness (LWR) and/or line edge roughness (LER) than the first pattern. The second pattern is then etched into the substrate.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih Wei Lu, Chung-Ju Lee, Tien-I Bao
  • Patent number: 8975187
    Abstract: Disclosed is a method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N2/H2 plasma gas treatment. During its formation, the stress to be carried by the TiN hard mask is controlled by controlling the number of TiN sub-layers and the plasma gas treatment duration such that the stress may counter-balance predetermined external stress anticipated on a conventionally made TiN hard mask, which causes trench sidewall distortion, trench opening shrinkage, and gap filling problem.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rueijer Lin, Chun-Chieh Lin, Hung-Wen Su, Minghsing Tsai
  • Patent number: 8962431
    Abstract: A method of forming metal silicide-comprising material includes forming a substrate which includes a first stack having second metal over first metal over silicon and a second stack having second metal over silicon. The first and second metals are of different compositions. The substrate is subjected to conditions which react the second metal with the silicon in the second stack to form metal silicide-comprising material from the second stack. The first metal between the second metal and the silicon in the first stack precludes formation of a silicide comprising the second metal and silicon from the first stack. After forming the metal silicide-comprising material, the first metal, the second metal and the metal silicide-comprising material are subjected to an etching chemistry that etches at least some remaining of the first and second metals from the substrate selectively relative to the metal silicide-comprising material.
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, John Mark Meldrim, Rita J. Klein
  • Patent number: 8951900
    Abstract: The present disclosure is directed to, among other things, an illustrative method that includes forming an opening in a dielectric material of a contact level of a semiconductor device, and selectively depositing a conductive material in the opening to form a contact element therein, the contact element extending to a contact area of a circuit element and having a laterally restricted excess portion formed outside of the opening and above the dielectric material. The disclosed method further includes forming a sacrificial material layer above the dielectric material and the contact element, the sacrificial material layer surrounding the laterally restricted excess portion. Additionally, the method includes planarizing a surface topography of the contact level in the presence of the sacrificial material so as to remove the laterally restricted excess portion from above the dielectric material.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: February 10, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Axel Preusse, Norbert Schroeder, Uwe Stoeckgen
  • Patent number: 8946087
    Abstract: A method for providing metal filled features in a layer is provided. A metal seed layer is deposited on tops and bottoms of the features. Metal seed layer on tops of the features and overhangs is removed without removing metal seed layer on bottoms of features. An electroless deposition of metal is provided to fill the features, wherein the electroless deposition first deposits on the metal seed layer on bottoms of the features.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: February 3, 2015
    Assignee: Lam Research Corporation
    Inventor: Praveen Reddy Nalla
  • Publication number: 20150024582
    Abstract: A method of making a Si containing gas distribution member for a semiconductor plasma processing chamber comprises forming a carbon member into an internal cavity structure of the Si containing gas distribution member. The method includes depositing Si containing material on the formed carbon member such that the Si containing material forms a shell around the formed carbon member. The Si containing shell is machined into the structure of the Si containing gas distribution member wherein the machining forms gas inlet and outlet holes exposing a portion of the formed carbon member in an interior region of the Si containing gas distribution member.
    Type: Application
    Filed: October 9, 2014
    Publication date: January 22, 2015
    Inventor: Travis Robert Taylor
  • Patent number: RE45481
    Abstract: An interconnector line of thin film comprising 0.001 to 30 at % of at least one kind of a first element capable of constituting an intermetallic compound of aluminum and/or having a higher standard electrode potential than aluminum, for example, at least one kind of the first element selected from Y, Sc, La, Ce, Nd, Sm, Gd, Tb, Dy, Er, Th, Sr, Ti, Zr, V, Nb, Ta, Cr, Mo, W, Mn, Tc, Re, Fe, Co, Ni, Pd, Ir, Pt, Cu, Ag, Au, Cd, Si, Pb and B; and one kind of a second element selected from C, O, N and H in a proportion of 0.01 at ppm to 50 at % of the first element, with the balance comprising substantially Al. In addition to having low resistance, such an Al interconnector line of thin film can prevent the occurrence of hillocks and the electrochemical reaction with an ITO electrode. The interconnector line of thin film can be obtained by sputtering in a dust-free manner by using a sputter target having a similar composition.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Ishigami, Koichi Watanabe, Akihisa Nitta, Toshihiro Maki, Noriaki Yagi