With Epitaxial Conductor Formation Patents (Class 438/607)
  • Patent number: 6083818
    Abstract: A semiconductor device having a barrier film comprising an extremely thin film formed of one or more monolayers each comprised of a two-dimensional array of metal atoms. In one exemplary aspect, the barrier film is used for preventing the diffusion of atoms of another material, such as a copper conductor, into a substrate, such as a semiconducting material or an insulating material. In one mode of making the semiconductor device, the barrier film is formed by depositing a precursor, such as a metal halide (e.g., BaF.sub.2), onto the substrate material, and then annealing the resulting film on the substrate material to remove all of the constituents of the temporary heteroepitaxial film except for a monolayer of metal atoms left behind as attached to the surface of the substrate. A conductor, such as copper, deposited onto the barrier film is effectively prevented from diffusing into the substrate material even when the barrier film is only one or several monolayers in thickness.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: July 4, 2000
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Michael F. Stumborg, Francisco Santiago, Tak Kin Chu, Kevin A. Boulais
  • Patent number: 6080644
    Abstract: An epitaxial layer is formed on a P type silicon substrate in which a plurality of P+ buried layer regions, a plurality of N+ buried layer regions, and a P+ field layer region occupying most of the substrate surface are diffused. The substrate is loaded in a reactor with a carrier gas. The substrate is pre-baked at a temperature of approximately 850.degree. C. As the substrate is heated to a temperature of 1050.degree. C. N+ dopant gas is injected into the carrier gas to suppress autodoping due to P+ atoms that escape from the P+ buried layer regions. The substrate is subjected to a high temperature bake cycle in the presence of the N+ dopant gas. A first thin intrinsic epitaxial cap layer is deposited on the substrate, which then is subjected to a high temperature gas purge cycle at 1080.degree. C. A second thin intrinsic epitaxial cap layer then is deposited on the first, and a second high temperature gas purge cycle is performed at 1080.degree. C.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: June 27, 2000
    Assignee: Burr-Brown Corporation
    Inventors: Vladimir F. Drobny, Kevin X. Bao
  • Patent number: 5973372
    Abstract: A method, and structure resulting therefrom, of forming a metal silicide at a shallow junction in a single crystal substrate without encroaching on the shallow junction by forming a metal layer on the substrate over the junction followed by forming a layer of a silicon material which reacts with the metal faster than the silicon in the single crystal substrate. Titanium is the preferred metal and amorphous silicon is the preferred silicon layer and is of a thickness to react with all of the titanium. The two layers are rapid thermal annealed to form titanium silicide. A second rapid thermal anneal is performed which converts the majority of the C49 phase of the titanium silicide to a less resistive and more conductive C54 phase and causes a silicon epitaxial layer to form between silicon substrate and the titanium silicide.
    Type: Grant
    Filed: December 6, 1997
    Date of Patent: October 26, 1999
    Inventors: Farrokh Omid-Zohoor, Nader Radjy
  • Patent number: 5920795
    Abstract: A method for manufacturing a semiconductor device is disclosed herein by which the contamination of an epitaxial film-Si substrate interface with carbon can be solved without allowing boron to remain in the epitaxial film-Si substrate interface. The method for manufacturing a semiconductor device according to the present invention comprises a step of ion-implanting, into an Si substrate, an element or a compound which easily reacts with carbon, a step of removing a natural oxide film on the Si substrate, a step of annealing, at a temperature of 800.degree. C. or less in a CVD device, the Si substrate which has been subjected to the ion-implantation and the removal of the natural oxide film by the above two steps, and a step of carrying out an Si epitaxial growth or an Si.sub.1-x Ge.sub.x epitaxial growth on the annealed substrate by the CVD device.
    Type: Grant
    Filed: May 5, 1997
    Date of Patent: July 6, 1999
    Assignee: NEC Corporation
    Inventor: Tatsuya Suzuki
  • Patent number: 5918143
    Abstract: A method for fabricating a sub-micron structure of etch-resistant metal/semiconductor compound on a substrate of semiconductor material comprises the step of depositing onto the substrate a layer of metal capable of reacting with the semiconductor material to form etch-resistant metal/semiconductor compound, and the step of producing a focused electron beam. The focused electron beam is applied to the layer of metal to locally heat the metal and semiconductor material and cause diffusion of the metal and semiconductor material in each other to form etch-resistant metal/semiconductor compound. The focused electron beam is displaced onto the layer of metal to form the structure of etch-resistant metal/semiconductor compound. Finally, the layer of metal is wet etched to leave on the substrate only the structure of metal/semiconductor compound.
    Type: Grant
    Filed: March 20, 1997
    Date of Patent: June 29, 1999
    Assignee: Universite de Sherbrooke
    Inventors: Jacques Beauvais, Dominique Drouin, Eric Lavallee
  • Patent number: 5904564
    Abstract: Disclosed herein is a method for fabricating a metal oxide semiconductor field effect transistor having cobalt silicide. According to the method, there is first provided a semiconductor substrate having exposed silicon portions on the surface thereof. The exposed silicon is either single crystalline silicon or polycrystalline silicon, and may include junction regions in which N typed or P typed impurity such as arsenic, phosphorous, or boron is formed. Niobium and cobalt are sequentially deposited on the exposed silicon portions by electron-beam evaporation method. Afterwards, annealing step is performed to form a cobalt silicide film on the exposed silicon portions.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: May 18, 1999
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Sang Hoon Park
  • Patent number: 5897366
    Abstract: A method of resistless gate metal etch in the formation of a field effect transistor is disclosed, which includes providing a first layer of a first semiconductor material having a surface. A second layer of a second semiconductor material is formed on the surface and resistlessly patterned to define a masked and an unmasked portions. The unmasked portion of the second layer is etched away to the first layer to enable gate formation.
    Type: Grant
    Filed: March 10, 1997
    Date of Patent: April 27, 1999
    Assignee: Motorola, Inc.
    Inventors: Kumar Shiralagi, Saied N. Tehrani
  • Patent number: 5773357
    Abstract: A method of forming a silicon-based thin film for burying contact holes having a high aspect ratio is disclosed. The method comprises the steps of forming contact holes in an insulating film provided on a semiconductor substrate, and growing a silicon-based (silicon or silicon alloys) film containing impurities by Chemical Vapor Deposition to bury the contact holes. The growth is performed by simultaneously feeding a material gas for forming the silicon-based film and an etching gas for etching the silicon-based film, where the material gas is fed under surface reaction limiting conditions to equalize gas concentrations inside and outside said contact holes, and the etching gas is fed under supply rate limiting conditions to make the gas concentration outside the contact hole higher than that at the bottom of the contact hole.
    Type: Grant
    Filed: January 25, 1996
    Date of Patent: June 30, 1998
    Assignee: NEC Corporation
    Inventor: Seiichi Shishiguchi
  • Patent number: 5629236
    Abstract: The method of manufacturing a semiconductor device, according to the present invention, includes the steps of forming a polycrystal lower-level Al wiring layer on a silicon substrate, forming an interlayer insulation film for covering the lower-level Al wiring layer on the entire surface, forming a connection hole which reaches the lower-level Al wiring layer in the interlayer insulation film, forming a polycrystal upper-level Al wiring layer on a surface of the interlayer insulation film, forming an interlayer insulation film for covering the upper-level Al wiring layer on the entire surface, and forming a single-crystal lower-level Al wiring layer and upper-layer Al wiring layer which are connected to each other in the connection hole by heating the silicon substrate so that the lower-level Al wiring layer and the upper-level Al wiring layer are converted from a polycrystal phase to an amorphous phase, and then cooling the silicon substrate so that the upper-level Al wiring layer is set in a supercooling st
    Type: Grant
    Filed: July 25, 1995
    Date of Patent: May 13, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun-ichi Wada, Hisashi Kaneko, Nobuo Hayasaka