To Form Ohmic Contact To Semiconductive Material Patents (Class 438/597)
  • Patent number: 11042091
    Abstract: The present invention relates to a composition comprising; components a. c. and d; and optional component b. wherein, component a. is a metal compound having the structure (I), optional component b., is a polyol additive, having structure (VI), component c. is a high performance polymer additive, and component d. is a solvent. The present invention further relates to using this compositions in methods for manufacturing electronic devices through either the formation of a patterned films of high K material comprised of a metal oxide on a semiconductor substrate, or through the formation of patterned metal oxide comprised layer overlaying a semiconductor substrate which may be used to selectively etch the semiconductor substrate with a fluorine plasma.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: June 22, 2021
    Assignee: Merck Patent GmbH
    Inventors: Huirong Yao, JoonYeon Cho, M. Dalil Rahman
  • Patent number: 11024504
    Abstract: A semiconductor device includes a substrate, a gate structure over the substrate, gate spacers on opposite sidewalls of the gate structure, an inhibitor residue over gate structure and between the gate spacers, and source/drain structures on opposite sides of the gate structure. The inhibitor residue lines a sidewall of one of the gate spacers.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Su, Fu-Ting Yen, Ting-Ting Chen, Teng-Chun Tsai
  • Patent number: 10978439
    Abstract: A method of generating a layout diagram includes: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Hui-Ting Yang, Ko-Bin Kao, Ru-Gun Liu, Shun Li Chen
  • Patent number: 10957644
    Abstract: Some embodiments include an integrated structure having a conductive region which contains one or more elements from Group 2 of the periodic table. Some embodiments include an integrated structure which has a conductive region over and directly against a base material. The conductive region includes one or more elements from Group 2 of the periodic table, and has a pair of opposing sidewalls along a cross-section. A capping material is over and directly against the conductive region. Protective material is along and directly against the sidewalls of the protective region.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Christopher W. Petz, Everett A. McTeer
  • Patent number: 10927468
    Abstract: Copper electroplating compositions which include an imidazole compound enables the electroplating of copper having uniform morphology on substrates. The composition and methods of enable copper electroplating of photoresist defined features. Such features include pillars, bond pads and line space features.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: February 23, 2021
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventor: Ravi Pokhrel
  • Patent number: 10879075
    Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Jyh-Cherng Sheu, Huang-Yi Huang, Chih-Wei Chang, Chi On Chui
  • Patent number: 10876159
    Abstract: The present invention provides technology that uses current measurements to identify nucleotides and determine a nucleotide sequence in polynucleotides. The present invention calculates a modal value of a tunnel current that arises when a nucleotide or polynucleotide for analysis passes through between electrodes, and then employs the calculated modal value. The present invention accordingly enables direct rapid implementation to identify nucleotides and to determine a nucleotide sequence in a polynucleotide without marking.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: December 29, 2020
    Assignee: QUANTUM BIOSYSTEMS INC.
    Inventors: Masateru Taniguchi, Makusu Tsutsui, Kazumichi Yokota, Tomoji Kawai
  • Patent number: 10867840
    Abstract: A method includes depositing a second dielectric layer over a first dielectric layer, depositing a third dielectric layer over the second dielectric layer, patterning a plurality of first openings in the third dielectric layer, etching the second dielectric layer through the first openings to form second openings in the second dielectric layer, performing a plasma etching process directed at the second dielectric layer from a first direction, the plasma etching process extending the second openings in the first direction, and etching the first dielectric layer through the second openings to form third openings in the first dielectric layer.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Nien Su, Shu-Huei Suen, Jyu-Horng Shieh, Ru-Gun Liu
  • Patent number: 10868185
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductive substrate, and a first contact plug formed on the semiconductive substrate. The semiconductor structure further includes a dielectric layer encircling the first contact plug. The semiconductor structure further includes a multilayer structure deposited on the dielectric layer and encircling the first contact plug. The dielectric layer produces a tensile stress pulling the first contact plug outward along a width direction. The multilayer structure produces a compressive stress that compensates for the tensile stress caused by the dielectric layer. A method of forming the semiconductor structure is also provided.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin-Shan Wang, Yi-Miaw Lin, Ming-Yih Wang
  • Patent number: 10858246
    Abstract: A semiconductor device comprises a structured metal layer. The structured metal layer lies above a semiconductor substrate. In addition, a thickness of the structured metal layer is more than 100 nm. Furthermore, the semiconductor device comprises a covering layer. The covering layer lies adjacent to at least one part of a front side of the structured metal layer and adjacent to a side wall of the structured metal layer. In addition, the covering layer comprises amorphous silicon carbide.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: December 8, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Markus Kahn, Anna-Katharina Kaiser, Soenke Pirk, Juergen Steinbrenner, Julia-Magdalena Straeussnigg
  • Patent number: 10821034
    Abstract: Various methods for detecting moisture in briefs compatible with high volume manufacturing are disclosed. The embodiments herein facilitate protection of the method of adding moisture sensing to a diaper, but could also be used to add sensing to pads and bandages. The primary design intent is optimal moisture detection and low per unit cost. Electrodes within a garment measure electrical properties of the electrodes to determine if the item has contacted moisture. The target moisture is urine, however, other sources and types of moisture can also be sensed. Additional analysis capabilities can be added by selecting particular electrodes or add materials that may react with chemical components of the moisture. Applications of the research Include monitor of incontinence using smart brief (e.g. diaper); monitor perspiration, bleeding, or failure of the protective garment; and monitoring exposure of an item to moisture, including but not limited to inanimate items.
    Type: Grant
    Filed: December 14, 2019
    Date of Patent: November 3, 2020
    Assignee: BioLink Systems, LLC
    Inventors: Ken Heyl, Doug Jackson, John Naber, Roger King
  • Patent number: 10756016
    Abstract: A method includes receiving a substrate having a substrate feature; forming a first material layer over the substrate and in physical contact with the substrate feature; forming an etch mask over the first material layer; and applying a dynamic-angle (DA) plasma etching process to the first material layer through the etch mask to form a first material feature. Plasma flux of the DA plasma etching process has an angle of incidence with respect to a normal of the first material layer and the angle of incidence changes in a dynamic mode during the DA plasma etching process.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chih-Tsung Shih
  • Patent number: 10755969
    Abstract: Multi-patterning methods are provided for use in fabricating an array of metal lines comprising metal lines with different widths. For example, patterning methods implement spacer-is-dielectric (SID)-based self-aligned double patterning (SADP) methods for fabricating an array of metal lines comprising elongated metal lines with different widths, wherein an “unblock” mask is utilized as part of the process flow to overlap mandrel assigned and non-mandrel assigned features in a given SADP pattern to define regions to unblock a metal fill (remove dielectric material between wires) in a dielectric layer between defined metal lines of an a SADP pattern thus enabling the formation of wide metal lines within any region of a pattern of elongated metal lines formed with a minimum feature width.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Albert Chu, Kafai Lai, Lawrence A. Clevenger
  • Patent number: 10748896
    Abstract: A semiconductor device includes a first fin field effect transistor (FinFET) and a contact bar (source/drain (S/D) contact layer). The first FinFET includes a first fin structure extending in a first direction, a first gate structure extending in a second direction crossing the first direction, and a first S/D structure. The contact bar is disposed over the first S/D structure and extends in the second direction crossing the first S/D structure in plan view. The contact bar includes a first portion disposed over the first S/D structure and a second portion. The second portion overlaps no fin structure and no S/D structure. A width of the second portion in the first direction is smaller than a width of the first portion in the first direction in plan view.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hao Chang, Yi-Shien Mor, Wen-Huei Guo
  • Patent number: 10741493
    Abstract: A structure includes a non-insulator structure, an etch stop layer, a dielectric layer, a conductive feature, and a first diffusion barrier layer. The etch stop layer is over the non-insulator structure. The dielectric layer is over the etch stop layer. The conductive feature is in the dielectric layer. The first diffusion barrier layer wraps around the conductive feature, the first diffusion barrier layer has a base portion between the non-insulator structure and the conductive feature, and the first diffusion barrier layer has a lateral extension from the base portion of the first diffusion barrier layer.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee
  • Patent number: 10707122
    Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: July 7, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Sree Rangasai V. Kesapragada, Kevin Moraes, Srinivas Guggilla, He Ren, Mehul Naik, David Thompson, Weifeng Ye, Yana Cheng, Yong Cao, Xianmin Tang, Paul F. Ma, Deenesh Padhi
  • Patent number: 10700164
    Abstract: Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Nam Kim, Rak-Hwan Kim, Byung-Hee Kim, Jong-Min Baek, Sang-Hoon Ahn, Nae-In Lee, Jong-Jin Lee, Ho-Yun Jeon, Eun-Ji Jung
  • Patent number: 10679996
    Abstract: A construction of integrated circuitry comprises a structure comprising conductive material having insulative material there-above. The conductive material and the insulative material respectively have opposing sides in a vertical cross-section. A first insulating material is laterally outward of the opposing sides of the conductive material in the vertical cross-section. A second insulating material is laterally outward of the first insulating material in the vertical cross-section. The second insulating material is of different composition from that of the first insulating material. The second insulating material laterally covers a lower portion of the opposing sides of the insulative material in the vertical cross-section. The second insulating material does not laterally cover an upper portion of the opposing sides of the insulative material in the vertical cross-section. A third insulating material is laterally outward of the second insulating material in the vertical cross-section.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kazuyoshi Yuki, Takayoshi Tashiro
  • Patent number: 10647141
    Abstract: An aqueous ink for inkjet printing contains silver particles having a particle size of 60 nm or less at a cumulative volume of 90%.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: May 12, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masayuki Ikegami, Yuhei Shimizu, Akira Kuriyama, Yoko Taira
  • Patent number: 10516095
    Abstract: According to one embodiment, a magnetic memory device includes a lower region, and a stacked structure provided on the lower region, wherein the stacked structure includes a conductive oxide layer containing boron (B), a first magnetic layer provided between the lower region and the conductive oxide layer, having a variable magnetization direction, and containing iron (Fe) and boron (B), a second magnetic layer provided between the lower region and the first magnetic layer, having a fixed magnetization direction, and containing iron (Fe) and boron (B), and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: December 24, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Koji Yamakawa, Koji Ueda
  • Patent number: 10505008
    Abstract: An insulated gate field effect transistor with (a) a base having source/drain regions, a channel forming region, a gate insulating film formed on the channel forming region, an insulating layer covering the source/drain regions, and a gate electrode formation opening provided in a partial portion of the insulating layer above the channel forming region; (b) a gate electrode formed by burying a conducive material layer in the gate electrode formation opening; (c) a first interlayer insulating layer formed on the insulating layer and the gate electrode and containing no oxygen atom as a constituent element; and (d) a second interlayer insulating layer on the first interlayer insulating layer.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: December 10, 2019
    Assignee: SONY CORPORATION
    Inventor: Fumiaki Okazaki
  • Patent number: 10483527
    Abstract: Provided is a cathode material for a rechargeable magnesium battery, represented by the chemical formula of Ag2SxSe1-x (0?x?1), a highly stable cathode material and a rechargeable magnesium battery including the same. The cathode material for a rechargeable magnesium battery has a higher discharge capacity and higher discharge voltage as compared to a typical commercially available cathode material, Chevrel phase, and shows excellent stability in an electrolyte for a rechargeable magnesium battery including chloride ions. In addition, after evaluating the cycle life of the cathode material, the cathode material shows an excellent discharge capacity per unit weight after 500 charge/discharge cycles, and thus is useful for a cathode material for a rechargeable magnesium battery.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: November 19, 2019
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Si Hyoung Oh, Byung Won Cho, Won Young Chang, Jung Hoon Ha, Boeun Lee, Hyo Ree Seo
  • Patent number: 10446687
    Abstract: A semiconductor package includes a leadframe, having perimeter package leads and a ground voltage lead, a bottom semiconductor die flip-chip mounted to the leadframe, and a top semiconductor die. The bottom semiconductor die has a first frontside active layer with first frontside electrical contacts electrically connected to the leadframe, a first backside portion, and a buried oxide layer situated between the first frontside active layer and the first backside portion. The top semiconductor die is mounted to the first backside portion. The first frontside active layer includes a circuit electrically connected to the first backside portion by a backside electrical connection through the buried oxide layer. The first backside portion of the bottom semiconductor die is electrically connected to the ground voltage lead through a first electrical contact of the first frontside electrical contacts to minimize crosstalk.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: October 15, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Shanghui Larry Tu, Michael A. Stuber, Befruz Tasbas, Stuart B. Molin, Raymond Jiang
  • Patent number: 10429434
    Abstract: Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John A. Fifield, Eric Hunt-Schroeder, Mark D. Jacunski
  • Patent number: 10396114
    Abstract: A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: August 27, 2019
    Assignee: Invensas Corporation
    Inventors: Charles G. Woychik, Cyprian Emeka Uzoh, Michael Newman, Terrence Caskey
  • Patent number: 10283638
    Abstract: A stack for a semiconductor device and a method for making the stack are disclosed. The stack comprises a plurality of sacrificial layers in which each sacrificial layer comprises a first lattice parameter; and at least one channel layer comprising a second lattice parameter that is different from the first lattice parameter and in which each channel layer is disposed between and in contact with two sacrificial layers. The stack is formed on an underlayer in which a sacrificial layer is in contact with the underlayer. The underlayer comprises a third lattice parameter that substantially matches the lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were was allow to relax coherently.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 7, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jorge A. Kittl, Ganesh Hegde, Robert C. Bowen, Mark S. Rodder
  • Patent number: 10269631
    Abstract: As a barrier metal film, a titanium film is formed by a sputtering process, and a titanium nitride film is formed to cover the titanium film by a CVD process. Next, the back surface of a semiconductor substrate is cleaned by spraying a cleaning chemical liquid toward the back surface thereof, and a portion of the barrier metal film located in the outer peripheral portion is removed by causing the cleaning chemical liquid to wrap around toward the surface side of the outer peripheral portion from the back surface side. Next, a tungsten film is formed to cover the barrier metal film by a CVD process.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: April 23, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kentaro Kita, Takeshi Hayashi, Koji Ikuta
  • Patent number: 10179954
    Abstract: Bipolar wave current, is used to electrodeposit a nanocrystalline grain size. Polarity Ratio is the ratio of absolute value of time integrated amplitude of negative and positive polarity current. Grain size can be controlled in alloys of two or more components, at least one of which is a metal, and at least one of which is most electro-active, such as nickel and tungsten and molybdenum. Typically, the more electro-active material is preferentially lessened during negative current. Coatings can be layered, each having an average grain size, which can vary layer to layer and also graded through a region. Deposits can be substantially free of either cracks or voids.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: January 15, 2019
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Andrew J. Detor, Christopher A. Schuh
  • Patent number: 10141260
    Abstract: A method of forming an interconnection structure includes forming a dielectric structure over a non-insulator structure; forming a hole in the dielectric structure to expose the non-insulator structure; forming a first diffusion barrier layer into the hole in the dielectric structure using a first deposition process; forming a second diffusion barrier layer over the first diffusion barrier layer using a second deposition process that is different from the first deposition process; and forming a metal over the second diffusion barrier layer.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 27, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chen Chan, Shin-Yi Yang, Ming-Han Lee
  • Patent number: 10109553
    Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alan B. Botula, Max L. Lifson, James A. Slinkman, Theodore G. Van Kessel, Randy L. Wolf
  • Patent number: 10062734
    Abstract: A method for fabricating a semiconductor device includes the steps of: forming a channel layer on a substrate; forming a gate dielectric layer on the channel layer; forming a source layer near one side of the gate dielectric layer and a drain layer near another side of the gate dielectric layer; forming a bottom gate on the gate dielectric layer; forming a phase change layer on the bottom gate; and forming a top gate on the phase change layer.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: August 28, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wanxun He, Su Xing
  • Patent number: 10027086
    Abstract: A device including a non-polarization material includes a number of layers. A first layer of silicon (100) defines a U-shaped groove having a bottom portion (100) and silicon sidewalls (111) at an angle to the bottom portion (100). A second layer of a patterned dielectric on top of the silicon (100) defines vertical sidewalls of the U-shaped groove. A third layer of a buffer covers the first layer and the second layer. A fourth layer of gallium nitride is deposited on the buffer within the U-shaped groove, the fourth layer including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111), wherein a deposition thickness (h) of the gallium nitride above the first layer of silicon (100) is such that the c-GaN completely covers the h-GaN between the vertical sidewalls.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: July 17, 2018
    Assignee: Board of Trustees of the University of Illinois
    Inventors: Can Bayram, Richard Liu
  • Patent number: 10014268
    Abstract: A semiconductor device includes a substrate main body, a plurality of first bump pads, and redistribution layer (RDL). The first bump pads are disposed adjacent to a surface of the substrate main body, each of the first bump pads has a first profile from a top view, the first profile has a first width along a first direction and a second width along a second direction perpendicular to the first direction, and the first width of the first profile is greater than the second width of the first profile. The RDL is disposed adjacent to the surface of the substrate main body, and the RDL includes a first portion disposed between two first bump pads.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: July 3, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chun-Jun Zhuang, Hung-Chun Kuo, Chun-Chin Huang
  • Patent number: 10014269
    Abstract: The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed at a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top layer of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the semiconductor wafer is exposed.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: July 3, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yueh-Chuan Lee, Chia-Chan Chen
  • Patent number: 9978666
    Abstract: A method for is used for forming a semiconductor device. The method includes forming an ILD layer on a substrate and a buffer layer on the ILD layer, wherein at least one contact is formed in the ILD layer; forming an opening through the buffer layer, the ILD layer, and the substrate; forming a liner structure layer over the substrate, wherein an exposed surface of the opening is covered by the liner structure layer; depositing a conductive material over the substrate to fill the opening; performing a polishing process, to polish over the substrate and stop at the buffer layer, wherein the liner structure layer and the conductive material remaining in the opening form a conductive via; performing an etching back process, to remove the buffer layer and expose the ILD layer, wherein a top portion of the conductive via is also exposed and higher than the ILD layer.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 22, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Kuei-Sheng Wu, Ming-Tse Lin
  • Patent number: 9978641
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate; forming a plurality of gate structures on the plurality of fins and sidewall spacers on side surfaces of the gate structures; forming a first dielectric layer on the semiconductor substrate; recessing the gate structures to form a plurality of trenches on top surfaces of the gate structures; forming a mask material layer filling the trenches and on the first dielectric layer; forming a protective layer on the top surfaces of the remaining gate structures and a mask layer on a portion of the first dielectric layer between adjacent gate structures by etching the mask material layer; forming contact through-holes in the first dielectric layer between adjacent gates structure at both sides of the mask layer; and forming a metal contact via in each of the contact through-holes.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: May 22, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Chenglong Zhang, Haiyang Zhang
  • Patent number: 9941200
    Abstract: A first semiconductor substrate layer supports a first transistor including a first source-drain formed by a doped region of the substrate layer. A second semiconductor substrate layer supports a second transistor including a second source-drain formed by a doped region of the substrate layer. The second semiconductor substrate layer is stacked over the first semiconductor substrate layer and separated therefrom by an insulating layer. A metal wiring extends from an electrical contact with the doped region for the first source-drain, through the insulating layer and passing through an electrical isolation structure in the second semiconductor substrate layer to make an electrical contact with the doped region for the second source-drain. The electrical isolation structure is formed by one of a trench isolation or the doped region of the second source-drain itself. The isolation structure has a thickness equal to a thickness of the second semiconductor substrate layer.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: April 10, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventor: Francois Roy
  • Patent number: 9932662
    Abstract: A mask frame assembly includes a mask having pattern openings and a frame including a first support portion configured to support an end of the mask and having a clamping slot and a support slot adjacent to the clamping slot; and a second support portion connected to the first support portion.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: April 3, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sangshin Lee
  • Patent number: 9911698
    Abstract: A semiconductor device is provided which comprises a metal interconnect structure having a metal alloy capping layer formed within a surface region of the metal interconnect structure, as well as methods for fabricating the semiconductor device. For example, a method comprises forming a metal interconnect structure in a dielectric layer, and applying a surface treatment to a surface of the metal interconnect structure to form a point defect layer in the surface of the metal interconnect structure. A metallic capping layer is then formed on the point defect layer of the metal interconnect structure, and a thermal anneal process is performed to convert the point defect layer into a metal alloy capping layer by infusion of metal atoms of the metallic capping layer into the point defect layer. The resulting metal alloy capping layer comprises an alloy of metallic materials of the metal capping layer and the metal interconnect structure.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 9852964
    Abstract: Techniques are disclosed for forming a through-body-via (TBV) in a semiconductor die. In accordance with some embodiments, a TBV provided using the disclosed techniques includes a polymer-based barrier layer and an electrically conductive seed layer formed by applying an electrically conductive ink directly to the barrier layer and then curing it in situ. In some embodiments, after curing, the resultant seed layer may be a thin, substantially conformal, electrically conductive metal film over which the TBV interconnect metal can be deposited. In some example cases, a polyimide, parylene, benzocyclobutene (BCB), and/or polypropylene carbonate (PPC) barrier layer and an ink containing copper (Cu) and/or silver (Ag), of nanoparticle-based or metal complex-based formulation, may be used in forming the TBV.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: December 26, 2017
    Assignee: INTEL CORPORATION
    Inventor: Kevin J. Lee
  • Patent number: 9842734
    Abstract: A method is provided for forming a feature of a target material on a substrate. The method including: forming a feature of a sacrificial material on the substrate; and forming the feature of the target material by a deposition process during which the feature of the sacrificial material is removed from the substrate by forming a volatile reaction product with a precursor of the deposition process, wherein the sacrificial material is replaced by the target material and the target material is selectively deposited on surface portions of the substrate, which portions were covered by the feature of the sacrificial material, to form the feature of the target material.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 12, 2017
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Annelies Delabie, Markus Heyne
  • Patent number: 9790083
    Abstract: A vibrator includes a base, a lid, and a functional element that is stored in a cavity formed by the base and the lid, in which the lid is provided with a sealing hole that penetrates through the lid and a sealing member that air-tightly seals the sealing hole, and in which the functional element includes a diffusion object shielding portion having a region of an accommodation opening which overlaps at least part of a region of a first opening of the sealing hole on a surface of the lid on the cavity side in a plan view of the functional element and the lid.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: October 17, 2017
    Assignee: Seiko Epson Corporation
    Inventor: Teruo Takizawa
  • Patent number: 9714351
    Abstract: A composition for the marking of assets comprising: a base material; and two or more encoding compounds wherein each of the two or more encoding compounds are provided at measurable concentrations.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: July 25, 2017
    Assignee: Chameleon Innovations Australia (CIA) Pty Ltd
    Inventors: Cameron Jay Scadding, Rachel Louis Scadding, Roger John Watling, Christopher David May, Craig Manuel Pages-Oliver, Nina Hobson
  • Patent number: 9659882
    Abstract: A system, method and apparatus for making a semiconductor die includes forming multiple semiconductor devices in a respective portion of a semiconductor wafer. An electrical interconnect structure is formed over the semiconductor devices and provide electrical connections to the semiconductor devices. The electrical interconnect structure including one or more metallization layers. Each of the metallization layers includes conductive lines. At least one portion of at least one of the metallization layers includes a density of the conductive lines that varies as compared to the other portions of the metallization layers. At least one support structure is formed in the electrical interconnect structure. The semiconductor wafer can be a thinned semiconductor wafer.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: May 23, 2017
    Assignee: SanDisk Technologies LLC
    Inventor: Manuel A. d'Abreu
  • Patent number: 9644256
    Abstract: A mask assembly and a thin film deposition method using the same are provided. The mask assembly includes a mask frame including first to fourth sides. The first to fourth sides form a rectangle. Inner sides of the rectangle define a window. The mask frame has a plurality of substrate seating portions provided to project toward the window from at least two corners. The two corners face each other in a diagonal direction. The mask assembly includes four corners positioned where the first to fourth sides of the mask assembly meet each other. A mask includes a plurality of openings for deposition. The plurality of openings are arranged to correspond to the window.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: May 9, 2017
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Jung Woo Ko
  • Patent number: 9631291
    Abstract: Controlling dimensions of nanowires includes lithographically forming a trench in a layer of a polymer resin with a width less than one micrometer where the polymer resin has a thickness less than one micrometer and is deposited over an electrically conductive substrate, depositing a nanowire material within the trench to form a nanowire, and obtaining the nanowire from the trench with a removal mechanism.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: April 25, 2017
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Graeme Scott, Kevin Dooley, Lorraine Byrne, Pat J. Reilly
  • Patent number: 9620370
    Abstract: A method of forming a Ti film on a substrate disposed in a chamber by introducing a processing gas containing a TiCl4 gas as a Ti source and a H2 gas as a reducing gas and by generating plasma in the chamber, includes introducing an Ar gas as a plasma generation gas into the chamber, converting the Ar gas into plasma to generate Ar ions, and acting the Ar ions on the Ti film to promote desorption of Cl from the Ti film.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 11, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Seishi Murakami, Takaya Shimizu, Satoshi Wakabayashi
  • Patent number: 9613909
    Abstract: Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings. An intermediate semiconductor device is also disclosed.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: April 4, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sunil Kumar Singh, Ravi Prakash Srivastava, Nicholas Robert Stokes
  • Patent number: 9613850
    Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a dataset specifying a plurality features to be formed on the workpiece. A first patterning of a hard mask of the workpiece is performed based on a first set of features of the plurality of features, and a first spacer material is deposited on a sidewall of the patterned hard mask. A second patterning is performed based on a second set of features, and a second spacer material is deposited on a sidewall of the first spacer material. A third patterning is performed based on a third set of features. A portion of the workpiece is selectively processed using a pattern defined by a remainder of at least one of the patterned hard mask layer, the first spacer material, or the second spacer material.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: April 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Sung Yen, Chun-Kuang Chen, Ko-Bin Kao, Ken-Hsien Hsieh, Ru-Gun Liu
  • Patent number: 9594867
    Abstract: A range-pattern-matching-type DRC-based process hotspot detection is provided that considers edge tolerances and incomplete specification (“don't care”) regions in foundry-provided hotspot patterns. First, all possible topological patterns are enumerated for the foundry-provided hotspot pattern. Next, critical topological features are extracted from each pattern topology and converted to critical design rules using Modified Transitive Closure Graphs (MTCGs). Third, the extracted critical design rules are arranged in an order that facilitates searching space reduction techniques, and then the DRC process is sequentially repeated on a user's entire layout pattern for each critical design rule in a first group, then searching space reduction is performed to generate a reduced layout pattern, and then DRC process is performed for all remaining critical design rules using the reduced layout pattern.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 14, 2017
    Assignee: Synopsys, Inc.
    Inventors: Yen Ting Yu, Hui-Ru Jiang, Yumin Zhang, Charles C. Chiang